Thierry Reding 1ec7032ad5 clk: tegra: Add fixed factor peripheral clock type
Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-28 12:41:47 +02:00
..
2016-03-02 17:47:19 -08:00
2016-02-02 15:49:27 +01:00
2015-07-20 11:11:17 -07:00
2016-03-02 17:47:19 -08:00