581 Commits

Author SHA1 Message Date
f214be50f3 clocksource: marco: Fix the affinity set for local timer of CPU1
irqchip will reject the affinity set to CPUs which is not online
yet. but in the CPU1 wakeup stage, OS only sets CPU1 to be online
after local timer is set, so that causes the irq_set_affinity not
work. this patch moves to irq_force_affinity() for the low level
boot stage.

Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-05-22 18:54:47 +02:00
efca0a3e85 exynos_mct update for v3.16
- register sched_clock callback to use clocksource mct-frc
 
 Note that got ack from Daniel
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Merge tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung driver update for 3.16" from Kukjin Kim:

exynos_mct update for v3.16

- register sched_clock callback to use clocksource mct-frc

* tag 'samsung-drivers' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  clocksource: exynos_mct: register sched_clock callback

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-21 22:32:57 -07:00
486ad2ede1 ARM Versatile Express updates for 3.16
This series reworks VE's platform configuration infrastructure by:
 
 - making it possible to instantiate selected devices from the
   Device Tree, prior to massive population,
 - converting custom "func" API into standard "regmap",
 - splitting the existing MFD driver into smaller ones and placing
   them into relevant directories.
 
 The common clock framework driver can now be selected individually
 (mostly for arm64 sake, where some of them are not used at all).
 
 It also simplifies the machine code, by:
 
 - moving the shed clock info clocksource driver,
 - simplifying SMP operations to base them entirely of the DT data,
 - moving platform ID checks into relevant driver.
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Merge tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux into next/cleanup

Merge "ARM Versatile Express updates for 3.16" from Pawel Moll:

This series reworks VE's platform configuration infrastructure by:

- making it possible to instantiate selected devices from the
  Device Tree, prior to massive population,
- converting custom "func" API into standard "regmap",
- splitting the existing MFD driver into smaller ones and placing
  them into relevant directories.

The common clock framework driver can now be selected individually
(mostly for arm64 sake, where some of them are not used at all).

It also simplifies the machine code, by:

- moving the shed clock info clocksource driver,
- simplifying SMP operations to base them entirely of the DT data,
- moving platform ID checks into relevant driver.

* tag 'vexpress/updates-for-3.16' of git://git.linaro.org/people/pawel.moll/linux:
  ARM: vexpress: move HBI check to sysreg driver
  ARM: vexpress: Simplify SMP operations for DT-powered system
  ARM: vexpress: remove redundant vexpress_dt_cpus_num to get cpu count
  clocksource: Sched clock source for Versatile Express
  clk: versatile: Split config options for sp810 and vexpress_osc
  mfd: vexpress: Define the device as MFD cells
  mfd: syscon: Add platform data with a regmap config name
  mfd: vexpress: Convert custom func API to regmap
  of: Keep track of populated platform devices
  + Linux 3.15-rc5

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-21 14:23:56 -07:00
91f0f06ccb Merge branch 'depends/clockevents-cleanups' into next/boards
Bringing in as an external dependency that the renesas/clock-cleanup2 branch
relies on.

* depends/clockevents-cleanups: (52 commits)
  clocksource: sh_mtu2: Sort headers alphabetically
  clocksource: sh_mtu2: Remove FSF mail address from GPL notice
  clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy case
  clocksource: sh_mtu2: Add support for multiple channels per device
  clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200
  clocksource: sh_mtu2: Set cpumask to cpu_possible_mask
  clocksource: sh_mtu2: Replace hardcoded register values with macros
  clocksource: sh_mtu2: Allocate channels dynamically
  clocksource: sh_mtu2: Replace kmalloc + memset with kzalloc
  clocksource: sh_mtu2: Add index to struct sh_mtu2_channel
  clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure
  clocksource: sh_mtu2: Constify name argument to sh_mtu2_register()
  clocksource: sh_mtu2: Split channel setup to separate function
  clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_device
  clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv
  clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables
  clocksource: sh_mtu2: Use request_irq() instead of setup_irq()
  clocksource: sh_tmu: Sort headers alphabetically
  clocksource: sh_tmu: Remove FSF mail address from GPL notice
  clocksource: sh_tmu: Rename clock to "fck" in the non-legacy case
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-05-21 14:05:27 -07:00
54196ccbe0 of: consolidate linker section OF match table declarations
We now have several OF match tables using linker sections that are
nearly the same definition. The only variation is the callback function
prototype. Create a common define for creating linker section OF match
table entries which each table declaration can use.

Acked-by: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
2014-05-20 14:25:24 -05:00
87ab4361be clocksource: cadence_ttc: Use readl/writel_relaxed instead of __raw
For supporting ARM big-endian is necessary to use
proper IO endianess accessors.

Based on Ben Dooks BE guide.
Similar conversion is done here:
"mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}"
(sha1: 5733c38ae3473115ac7df3fe19bd2502149d8c51)

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2014-05-20 16:16:05 +02:00
c54697ae18 clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case
In the legacy platform data case each TMU platform device handles a
single channel with a single IRQ for the platform device. Retrieve the
IRQ using the logical channel number instead of the hardware channel
number.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-05-19 16:15:17 +02:00
013be5adf5 clocksource: qcom: Implement read_current_timer for udelay
Setup the same timer used as the clocksource to be used as the
read_current_timer implementation. This allows us to support a
stable udelay implementation on MSMs where it's possible for the
CPUs to scale speeds independently of one another.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-05-19 11:30:11 +02:00
3f04e3d3eb Merge remote-tracking branch 'tip/timers/core/timers/core' into clockevents/3.16 2014-05-16 16:08:32 +02:00
220e2a8d22 clocksource: Sched clock source for Versatile Express
This patch adds a trival sched clock source using free
running, 24MHz clocked counter present in the ARM Ltd.
reference platforms (Versatile, RealView, Versatile
Express) System Registers block.

This code replaces the call in the VE machine code.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-15 17:02:20 +01:00
c7cff54d59 clocksource:sirf: remove the hardcode for the clk of timers
Nobody want to know the connection between io clk and timer clk,
so exposing this information to timer module is not reasonable.
this patch moves to define the timers' clk in dt.

Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-05-12 21:43:49 +08:00
4c1ad70921 clocksource: prima2: fix some minor checkpatch issues
Fix the "line over 80 characters". users of the codes - key customers
really care about that.

WARNING: line over 80 characters
64: FILE: timer-prima2.c:64:
+       WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));

WARNING: line over 80 characters
80: FILE: timer-prima2.c:80:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
82: FILE: timer-prima2.c:82:
+       cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);

WARNING: line over 80 characters
92: FILE: timer-prima2.c:92:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
96: FILE: timer-prima2.c:96:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
111: FILE: timer-prima2.c:111:
+               writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

WARNING: line over 80 characters
114: FILE: timer-prima2.c:114:
+               writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);

WARNING: line over 80 characters
126: FILE: timer-prima2.c:126:
+       writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);

WARNING: line over 80 characters
129: FILE: timer-prima2.c:129:
+               sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

WARNING: line over 80 characters
137: FILE: timer-prima2.c:137:
+               writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);

WARNING: line over 80 characters
139: FILE: timer-prima2.c:139:
+       writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);

WARNING: line over 80 characters
140: FILE: timer-prima2.c:140:
+       writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);

WARNING: line over 80 characters
216: FILE: timer-prima2.c:216:
+CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init);

total: 0 errors, 13 warnings, 216 lines checked

timer-prima2.c has style problems, please review.

If any of these errors are false positives, please report
them to the maintainer, see CHECKPATCH in MAINTAINERS.

Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
2014-05-12 21:43:49 +08:00
93bfb76975 clocksource: exynos_mct: register sched_clock callback
Use the clocksource mct-frc for sched_clock

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-05-02 22:27:01 +09:00
fb0095da19 Merge branch 'clockevents/3.15-fixes' of git://git.linaro.org/people/daniel.lezcano/linux into timers/urgent
clockevent fixes for 3.15 from Daniel Lezcano:
 * Lorenzo Pieralizi fixed an issue with the arch_arm_timer where the
   C3STOP flag for all the arch can cause some trouble by setting the
   flag only if the power domain is not always on
 * Alexander Shiyan fixed a compilation by changing the init function
   to the right prototype
2014-04-29 19:26:58 +02:00
9afa27ce94 clocksource: nspire: Fix compiler warning
CC      drivers/clocksource/zevio-timer.o
drivers/clocksource/zevio-timer.c:215:1: warning: comparison of distinct pointer types lacks a cast [enabled by default]

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-29 15:06:43 +02:00
82a5619410 clocksource: arch_arm_timer: Fix age-old arch timer C3STOP detection issue
ARM arch timers are tightly coupled with the CPU logic and lose context
on platform implementing HW power management when cores are powered
down at run-time. Marking the arch timers as C3STOP regardless of power
management capabilities causes issues on platforms with no power management,
since in that case the arch timers cannot possibly enter states where the
timer loses context at runtime and therefore can always be used as a high
resolution clockevent device.

In order to fix the C3STOP issue in a way compliant with how real HW
works, this patch adds a boolean property to the arch timer bindings
to define if the arch timer is managed by an always-on power domain.

This power domain is present on all ARM platforms to date, and manages
HW that must not be turned off, whatever the state of other HW
components (eg power controller). On platforms with no power management
capabilities, it is the only power domain present, which encompasses
and manages power supply for all HW components in the system.

If the timer is powered by the always-on power domain, the always-on
property must be present in the bindings which means that the timer cannot
be shutdown at runtime, so it is not a C3STOP clockevent device.
If the timer binding does not contain the always-on property, the timer is
assumed to be power-gateable, hence it must be defined as a C3STOP
clockevent device.

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Magnus Damm <damm@opensource.se>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-29 15:06:36 +02:00
e50a00be5c clocksource: sun5i: Add support for reset controller
The Allwinner A31 that uses this timer has the timer IP asserted in reset.
Add an optional reset property to the DT, and deassert the timer from reset if
it's there.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-22 13:56:50 +02:00
a5e1111785 Merge branch 'clockevents/cmt-mtu2-tmu-cleanups' into clockevents/3.16
This patch set cleans up the Renesas CMT and TMU drivers in preparation for DT
support.

The first 35 patches are a bunch of necessary cleanups that reorganize the CMT
and TMU drivers, their platform data, and the memory, interrupt and clock
resources they expect. As a result the drivers accept a new platform data
model close to the hardware with supports for all the timer channels using a
single device.

The next 13 patches (36/52 to 48/52) move all CMT and TMU platforms from the
old to the new platform data model. Patches 49/52 to 52/52 then drop support
for the old model and perform one more cleanup.

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-22 11:53:25 +02:00
63cc122381 clocksource: efm32: use $vendor,$device scheme for compatible string
Wolfram Sang pointed out that "efm32,$device" is non-standard. So use the
common scheme and prefix device with "efm32-". The old compatible string
is left in place until arch/arm/boot/dts/efm32* is fixed.

Acked-by: Wolfram Sang <wsa@the-dreams.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-22 11:44:28 +02:00
2cf2ff9f1f clocksource: arm_global_timer: Only check for unusable timer on A9
The check for a usable global timer in the probe code does not enquire
which CPU we are currently running on. This can cause the driver to
incorrectly assume we have an unusable global timer if we are running
on a CPU other than A9.

Before checking the CPU revision, ensure we are running on an A9 CPU.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
2014-04-22 11:44:24 +02:00
8db6e5104b clocksource: Exynos_mct: Register clock event after request_irq()
After hotplugging CPU1 the first call of interrupt handler for CPU1
oneshot timer was called on CPU0 because it fired before setting IRQ
affinity. Affected are SoCs where Multi Core Timer interrupts are
shared (SPI), e.g. Exynos 4210.

During setup of the MCT timers the clock event device should be
registered after setting the affinity for interrupt. This will prevent
starting the timer too early.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.299247848@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-04-17 23:36:28 +02:00
30ccf03b4a clocksource: Exynos_mct: Use irq_force_affinity() in cpu bringup
The starting cpu is not yet in the online mask so irq_set_affinity()
fails which results in per cpu timers for this cpu ending up on some
other online cpu, ususally cpu 0.

Use irq_force_affinity() which disables the online mask check and
makes things work.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>,
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>,
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: linux-arm-kernel@lists.infradead.org,
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/20140416143316.106665251@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2014-04-17 23:36:28 +02:00
346f5e76b3 clocksource: sh_mtu2: Sort headers alphabetically
This helps locating duplicates and inserting new headers.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:34 +02:00
24c8f71707 clocksource: sh_mtu2: Remove FSF mail address from GPL notice
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:33 +02:00
6dc9693bb3 clocksource: sh_mtu2: Rename clock to "fck" in the non-legacy case
The sh_mtu2 driver gets the MTU2 functional clock using a connection ID
of "mtu2_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "mtu2_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.

Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:33 +02:00
faf3f4f8c8 clocksource: sh_mtu2: Add support for multiple channels per device
MTU2 hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_mtu2 driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.

Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.

Support for the legacy model is kept and will be removed after all
platforms switch to the new model.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:32 +02:00
207e21a973 clocksource: sh_mtu2: Hardcode MTU2 clock event rating to 200
All boards use clock event ratings of 200 for the MTU2, hardcode it in
the driver.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:32 +02:00
3cc9504798 clocksource: sh_mtu2: Set cpumask to cpu_possible_mask
The MTU2 is not tied to CPU0, make it usable on any CPU.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:31 +02:00
f992c2410b clocksource: sh_mtu2: Replace hardcoded register values with macros
Define symbolic macros for all used registers bits.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:30 +02:00
c54ccb431c clocksource: sh_mtu2: Allocate channels dynamically
This prepares the driver for multi-channel support.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:30 +02:00
810c651369 clocksource: sh_mtu2: Replace kmalloc + memset with kzalloc
One kzalloc a day keeps the bugs away.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:29 +02:00
d2b9317706 clocksource: sh_mtu2: Add index to struct sh_mtu2_channel
Use the index as the timer start/stop bit and when printing messages to
identify the channel.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:29 +02:00
da90a1c677 clocksource: sh_mtu2: Add memory base to sh_mtu2_channel structure
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:28 +02:00
aa83804af7 clocksource: sh_mtu2: Constify name argument to sh_mtu2_register()
The name argument is assigned to const structure fields only, constify
it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:28 +02:00
2e1a53265d clocksource: sh_mtu2: Split channel setup to separate function
Move the channel setup code from sh_mtu2_setup to a new
sh_mtu2_setup_channel function and call it from sh_mtu2_setup.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:27 +02:00
7dad72de1b clocksource: sh_mtu2: Rename struct sh_mtu2_priv to sh_mtu2_device
Channel data is private as well, rename priv to device to make the
distrinction between the core device and the channels clearer.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:27 +02:00
42752cc619 clocksource: sh_mtu2: Split channel fields from sh_mtu2_priv
Create a new sh_mtu2_channel structure to hold the channel-specific
fields in preparation for multiple channels per device support.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:26 +02:00
f92d62f539 clocksource: sh_mtu2: Turn sh_mtu2_priv fields into local variables
The rate and periodic fields are used in a single function only, as
local variables. Remove them from the structure.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:25 +02:00
276bee05d8 clocksource: sh_mtu2: Use request_irq() instead of setup_irq()
The driver claims it needs to register an interrupt handler too early
for request_irq(). This might have been true in the past, but the only
meaningful difference between request_irq() and setup_irq() today is an
additional kzalloc() call in request_irq(). As the driver calls
kmalloc() itself we know that the slab allocator is available, we can
thus switch to request_irq().

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Wolfram Sang <wsa@sang-engineering.com>
2014-04-16 12:03:25 +02:00
13931f8065 clocksource: sh_tmu: Sort headers alphabetically
This helps locating duplicates and inserting new headers.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:24 +02:00
6b96c15b03 clocksource: sh_tmu: Remove FSF mail address from GPL notice
Do not include the paragraph about writing to the Free Software
Foundation's mailing address from the sample GPL notice. The FSF has
changed addresses in the past, and may do so again. Linux already
includes a copy of the GPL.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:24 +02:00
a27d922749 clocksource: sh_tmu: Rename clock to "fck" in the non-legacy case
The sh_tmu driver gets the TMU functional clock using a connection ID of
"tmu_fck". While all SH SoCs create clock lookup entries with a NULL
device ID and a "tmu_fck" connection ID, the ARM SoCs use the device ID
only with a NULL connection ID. This works on legacy platforms but will
break on ARM with DT boot.

Fix the situation by using a connection ID of "fck" in the non-legacy
platform data case. Clock lookup entries will be renamed to use the
device ID as well as the connection ID as platforms get moved to new
platform data. The legacy code will eventually be dropped, leaving us
with device ID based clock lookup, compatible with DT boot.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:23 +02:00
8c7f21e673 clocksource: sh_tmu: Add support for multiple channels per device
TMU hardware devices can support multiple channels, with global
registers and per-channel registers. The sh_tmu driver currently models
the hardware with one Linux device per channel. This model makes it
difficult to handle global registers in a clean way.

Add support for a new model that uses one Linux device per timer with
multiple channels per device. This requires changes to platform data,
add new channel configuration fields.

Support for the legacy model is kept and will be removed after all
platforms switch to the new model.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:23 +02:00
f1010ed1a1 clocksource: sh_tmu: Hardcode TMU clock event and source ratings to 200
All boards use clock event and clock source ratings of 200 for the TMU,
hardcode it in the driver.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:22 +02:00
5cfe2d151f clocksource: sh_tmu: Replace hardcoded register values with macros
Define symbolic macros for all used registers bits.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:22 +02:00
a5de49f436 clocksource: sh_tmu: Allocate channels dynamically
This prepares the driver for multi-channel support.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:21 +02:00
3b77a83eea clocksource: sh_tmu: Replace kmalloc + memset with kzalloc
One kzalloc a day keeps the bugs away.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:20 +02:00
fe68eb802e clocksource: sh_tmu: Add index to struct sh_tmu_channel
Use the index as the timer start/stop bit and when printing messages to
identify the channel.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:20 +02:00
de693461bf clocksource: sh_tmu: Add memory base to sh_tmu_channel structure
The channel memory base is channel-specific, add it to the channel
structure in preparation for support of multiple channels per device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:19 +02:00
84876d0505 clocksource: sh_tmu: Constify name argument to sh_tmu_register()
The name argument is assigned to const structure fields only, constify
it.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
2014-04-16 12:03:19 +02:00