drm/exynos: control blending of mixer graphic layer 0
The mixer graphic layer 0 isn't blended as default by commit 0377f4ed9f1aed30292c4e3c87f24e028ae26f36(drm/exynos: Don't blend mixer layer 0). But it needs to be blended with graphic layer 0 if video layer is enabled by vp because video layer is bottom. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -365,6 +365,11 @@ static void mixer_cfg_layer(struct mixer_context *ctx, int win, bool enable)
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vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
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vp_reg_writemask(res, VP_ENABLE, val, VP_ENABLE_ON);
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mixer_reg_writemask(res, MXR_CFG, val,
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mixer_reg_writemask(res, MXR_CFG, val,
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MXR_CFG_VP_ENABLE);
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MXR_CFG_VP_ENABLE);
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/* control blending of graphic layer 0 */
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mixer_reg_writemask(res, MXR_GRAPHIC_CFG(0), val,
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MXR_GRP_CFG_BLEND_PRE_MUL |
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MXR_GRP_CFG_PIXEL_BLEND_EN);
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}
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}
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break;
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break;
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}
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}
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