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Merge "driver: llcc_perfmon: Add ADDR_MASK filter"

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This commit is contained in:
qctecmdr 2022-06-16 06:59:12 -07:00 committed by Gerrit - the friendly Code Review server
commit edfd54ff28
3 changed files with 124 additions and 23 deletions
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1
drivers/soc/qcom/llcc_events.h
View File

@ -294,6 +294,7 @@ enum filter_type {
MEMTAGOPS,
MULTISCID,
DIRTYINFO,
ADDR_MASK,
UNKNOWN,
};

105
drivers/soc/qcom/llcc_perfmon.c
View File

@ -48,8 +48,8 @@ struct event_port_ops {
unsigned int type, unsigned int *num, bool enable);
void (*event_enable)(struct llcc_perfmon_private *priv, bool enable);
void (*event_filter_config)(struct llcc_perfmon_private *priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable);
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable);
};
/**
@ -363,6 +363,8 @@ static enum filter_type find_filter_type(char *filter)
ret = MULTISCID;
else if (!strcmp(filter, "DIRTYINFO"))
ret = DIRTYINFO;
else if (!strcmp(filter, "ADDR_MASK"))
ret = ADDR_MASK;
return ret;
}
@ -372,7 +374,8 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
size_t count)
{
struct llcc_perfmon_private *llcc_priv = dev_get_drvdata(dev);
unsigned long port, mask, match;
unsigned long long mask, match;
unsigned long port;
struct event_port_ops *port_ops;
char *token, *delim = DELIM_CHAR;
enum filter_type filter = UNKNOWN;
@ -398,7 +401,7 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
goto filter_config_free;
}
if (kstrtoul(token, 0, &match)) {
if (kstrtoull(token, 0, &match)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_config_free;
}
@ -414,7 +417,7 @@ static ssize_t perfmon_filter_config_store(struct device *dev,
goto filter_config_free;
}
if (kstrtoul(token, 0, &mask)) {
if (kstrtoull(token, 0, &mask)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_config_free;
}
@ -452,7 +455,8 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
{
struct llcc_perfmon_private *llcc_priv = dev_get_drvdata(dev);
struct event_port_ops *port_ops;
unsigned long port, mask, match;
unsigned long long mask, match;
unsigned long port;
char *token, *delim = DELIM_CHAR;
enum filter_type filter = UNKNOWN;
@ -472,7 +476,7 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
goto filter_remove_free;
}
if (kstrtoul(token, 0, &match)) {
if (kstrtoull(token, 0, &match)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_remove_free;
}
@ -488,7 +492,7 @@ static ssize_t perfmon_filter_remove_store(struct device *dev,
goto filter_remove_free;
}
if (kstrtoul(token, 0, &mask)) {
if (kstrtoull(token, 0, &mask)) {
pr_err("filter configuration failed, Wrong format\n");
goto filter_remove_free;
}
@ -771,10 +775,11 @@ static void feac_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void feac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
uint64_t val = 0;
uint32_t mask_val, offset;
if (filter == SCID) {
if (llcc_priv->version == REV_0) {
@ -851,6 +856,29 @@ static void feac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
offset = FEAC_PROF_FILTER_0_CFG7(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
} else if (filter == ADDR_MASK) {
if (enable)
val = (match & ADDR_LOWER_MASK) << FEAC_ADDR_LOWER_MATCH_SHIFT;
mask_val = FEAC_ADDR_LOWER_MATCH_MASK;
offset = FEAC_PROF_FILTER_0_CFG1(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
if (enable)
val = (mask & ADDR_LOWER_MASK) << FEAC_ADDR_LOWER_MASK_SHIFT;
mask_val = FEAC_ADDR_LOWER_MASK_MASK;
offset = FEAC_PROF_FILTER_0_CFG2(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
if (enable) {
match = (match & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
mask = (mask & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
val = (match << FEAC_ADDR_UPPER_MATCH_SHIFT) |
(mask << FEAC_ADDR_UPPER_MASK_SHIFT);
}
mask_val = FEAC_ADDR_UPPER_MATCH_MASK | FEAC_ADDR_UPPER_MASK_MASK;
offset = FEAC_PROF_FILTER_0_CFG3(llcc_priv->drv_ver);
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
} else {
pr_err("unknown filter/not supported\n");
}
@ -900,8 +928,8 @@ static void ferc_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void ferc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -948,8 +976,8 @@ static void fewc_event_config(struct llcc_perfmon_private *llcc_priv,
}
static void fewc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -1056,10 +1084,11 @@ static void beac_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void beac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val;
uint64_t val = 0;
uint32_t mask_val;
unsigned int mc_cnt, offset;
if (filter == PROFILING_TAG) {
@ -1084,6 +1113,38 @@ static void beac_event_filter_config(struct llcc_perfmon_private *llcc_priv,
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
} else if (filter == ADDR_MASK) {
if (enable)
val = (match & ADDR_LOWER_MASK) << BEAC_ADDR_LOWER_MATCH_SHIFT;
mask_val = BEAC_ADDR_LOWER_MATCH_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG4(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
if (enable)
val = (mask & ADDR_LOWER_MASK) << BEAC_ADDR_LOWER_MASK_SHIFT;
mask_val = BEAC_ADDR_LOWER_MASK_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG3(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
if (enable) {
match = (match & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
mask = (mask & ADDR_UPPER_MASK) >> ADDR_UPPER_SHIFT;
val = (match << FEAC_ADDR_UPPER_MATCH_SHIFT) |
(mask << FEAC_ADDR_UPPER_MASK_SHIFT);
}
mask_val = BEAC_ADDR_UPPER_MATCH_MASK | BEAC_ADDR_UPPER_MASK_MASK;
for (mc_cnt = 0; mc_cnt < llcc_priv->num_mc; mc_cnt++) {
offset = BEAC0_PROF_FILTER_0_CFG5(llcc_priv->drv_ver)
+ mc_cnt * BEAC_INST_OFF;
llcc_bcast_modify(llcc_priv, offset, val, mask_val);
}
} else {
pr_err("unknown filter/not supported\n");
return;
@ -1143,8 +1204,8 @@ static void berc_event_enable(struct llcc_perfmon_private *llcc_priv,
}
static void berc_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val, offset;
@ -1197,8 +1258,8 @@ static void trp_event_config(struct llcc_perfmon_private *llcc_priv,
}
static void trp_event_filter_config(struct llcc_perfmon_private *llcc_priv,
enum filter_type filter, unsigned long match,
unsigned long mask, bool enable)
enum filter_type filter, unsigned long long match,
unsigned long long mask, bool enable)
{
uint32_t val = 0, mask_val;

41
drivers/soc/qcom/llcc_perfmon.h
View File

@ -15,13 +15,15 @@
#define LLCC_COMMON_STATUS0(v) (VER_CHK(v) ? 0x3400C : 0x3000C)
/* FEAC */
#define FEAC_PROF_FILTER_0_CFG1(v) (VER_CHK(v) ? 0x43004 : 0x037004)
#define FEAC_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x43008 : 0x037008)
#define FEAC_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x4300C : 0x03700C)
#define FEAC_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x43014 : 0x037014)
#define FEAC_PROF_FILTER_0_CFG6(v) (VER_CHK(v) ? 0x43018 : 0x037018)
#define FEAC_PROF_FILTER_0_CFG7(v) (VER_CHK(v) ? 0x4301C : 0x03701C)
#define FEAC_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x43060 : 0x037060) \
+ 4 * (n))
#define FEAC_PROF_CFG(v) (VER_CHK(v) ? 0x430A0 : 0x0370A0)
#define FEAC_PROF_CFG(v) (VER_CHK(v) ? 0x430A0 : 0x370A0)
/* FERC */
#define FERC_PROF_FILTER_0_CFG0(v) (VER_CHK(v) ? 0x49000 : 0x03B000)
@ -35,6 +37,8 @@
+ 4 * (n))
/* BEAC */
#define BEAC0_PROF_FILTER_0_CFG3(v) (VER_CHK(v) ? 0x6100C : 0x04900C)
#define BEAC0_PROF_FILTER_0_CFG4(v) (VER_CHK(v) ? 0x61010 : 0x049010)
#define BEAC0_PROF_FILTER_0_CFG5(v) (VER_CHK(v) ? 0x61014 : 0x049014)
#define BEAC0_PROF_FILTER_0_CFG2(v) (VER_CHK(v) ? 0x61008 : 0x049008)
#define BEAC0_PROF_EVENT_n_CFG(v, n) ((VER_CHK(v) ? 0x61040 : 0x049040) \
@ -236,6 +240,22 @@
+ 0, \
FEAC_RD_BYTE_FILTER_EN_SHIFT)
#define FEAC_RD_BYTE_FILTER_EN BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)
#define FEAC_ADDR_LOWER_MATCH_SHIFT (0)
#define FEAC_ADDR_LOWER_MATCH_MASK GENMASK(FEAC_ADDR_LOWER_MATCH_SHIFT \
+31, \
FEAC_ADDR_LOWER_MATCH_SHIFT)
#define FEAC_ADDR_LOWER_MASK_SHIFT (0)
#define FEAC_ADDR_LOWER_MASK_MASK GENMASK(FEAC_ADDR_LOWER_MASK_SHIFT \
+31, \
FEAC_ADDR_LOWER_MASK_SHIFT)
#define FEAC_ADDR_UPPER_MATCH_SHIFT (0)
#define FEAC_ADDR_UPPER_MATCH_MASK GENMASK(FEAC_ADDR_UPPER_MATCH_SHIFT \
+4, \
FEAC_ADDR_UPPER_MATCH_SHIFT)
#define FEAC_ADDR_UPPER_MASK_SHIFT (4)
#define FEAC_ADDR_UPPER_MASK_MASK GENMASK(FEAC_ADDR_UPPER_MASK_SHIFT \
+4, \
FEAC_ADDR_UPPER_MASK_SHIFT)
/* BEAC */
#define BEAC_PROFTAG_MASK_SHIFT (14)
#define BEAC_PROFTAG_MASK_MASK GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\
@ -264,6 +284,22 @@
+ 0, \
BEAC_RD_BEAT_FILTER_EN_SHIFT)
#define BEAC_RD_BEAT_FILTER_EN BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)
#define BEAC_ADDR_LOWER_MATCH_SHIFT (0)
#define BEAC_ADDR_LOWER_MATCH_MASK GENMASK(BEAC_ADDR_LOWER_MATCH_SHIFT \
+31, \
BEAC_ADDR_LOWER_MATCH_SHIFT)
#define BEAC_ADDR_LOWER_MASK_SHIFT (0)
#define BEAC_ADDR_LOWER_MASK_MASK GENMASK(BEAC_ADDR_LOWER_MASK_SHIFT \
+31, \
BEAC_ADDR_LOWER_MASK_SHIFT)
#define BEAC_ADDR_UPPER_MATCH_SHIFT (0)
#define BEAC_ADDR_UPPER_MATCH_MASK GENMASK(BEAC_ADDR_UPPER_MATCH_SHIFT \
+4, \
BEAC_ADDR_UPPER_MATCH_SHIFT)
#define BEAC_ADDR_UPPER_MASK_SHIFT (4)
#define BEAC_ADDR_UPPER_MASK_MASK GENMASK(BEAC_ADDR_UPPER_MASK_SHIFT \
+4, \
BEAC_ADDR_UPPER_MASK_SHIFT)
/* TRP */
#define TRP_SCID_MATCH_SHIFT (0)
#define TRP_SCID_MATCH_MASK GENMASK(TRP_SCID_MATCH_SHIFT + 4,\
@ -303,6 +339,9 @@
TRP_SCID_STATUS_CURRENT_CAP_SHIFT_v31)
#define ADDR_LOWER_MASK (0xFFFFFFFF)
#define ADDR_UPPER_MASK (0xF00000000)
#define ADDR_UPPER_SHIFT (32)
#define MAJOR_VER_MASK (0xFF000000)
#define BRANCH_MASK (0x00FF0000)
#define MINOR_MASK (0x0000FF00)