clk: meson8b: clean up fixed rate clocks
Remove the fixed_rate registration function and helpers from clkc.[ch]. Replace unnecessary configuration struct with static initialization of the desired clock type. While we're here, begin the transition to a proper platform_driver and call of_clk_add_hw_provider with a shiny new struct clk_hw_onecell_data. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
This commit is contained in:
@ -167,36 +167,6 @@ meson_clk_register_fixed_factor(const struct clk_conf *clk_conf,
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return clk;
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return clk;
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}
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}
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static struct clk * __init
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meson_clk_register_fixed_rate(const struct clk_conf *clk_conf,
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void __iomem *clk_base)
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{
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struct clk *clk;
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const struct fixed_rate_conf *fixed_rate_conf;
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const struct parm *r;
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unsigned long rate;
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u32 reg;
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fixed_rate_conf = &clk_conf->conf.fixed_rate;
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rate = fixed_rate_conf->rate;
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if (!rate) {
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r = &fixed_rate_conf->rate_parm;
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reg = readl(clk_base + clk_conf->reg_off + r->reg_off);
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rate = PARM_GET(r->width, r->shift, reg);
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}
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rate *= 1000000;
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clk = clk_register_fixed_rate(NULL,
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clk_conf->clk_name,
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clk_conf->num_parents
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? clk_conf->clks_parent[0] : NULL,
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clk_conf->flags, rate);
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return clk;
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}
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void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
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void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
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unsigned int nr_confs,
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unsigned int nr_confs,
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void __iomem *clk_base)
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void __iomem *clk_base)
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@ -208,10 +178,6 @@ void __init meson_clk_register_clks(const struct clk_conf *clk_confs,
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const struct clk_conf *clk_conf = &clk_confs[i];
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const struct clk_conf *clk_conf = &clk_confs[i];
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switch (clk_conf->clk_type) {
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switch (clk_conf->clk_type) {
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case CLK_FIXED_RATE:
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clk = meson_clk_register_fixed_rate(clk_conf,
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clk_base);
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break;
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case CLK_FIXED_FACTOR:
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case CLK_FIXED_FACTOR:
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clk = meson_clk_register_fixed_factor(clk_conf,
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clk = meson_clk_register_fixed_factor(clk_conf,
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clk_base);
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clk_base);
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@ -69,11 +69,6 @@ struct fixed_fact_conf {
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struct parm mult_parm;
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struct parm mult_parm;
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};
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};
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struct fixed_rate_conf {
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unsigned long rate;
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struct parm rate_parm;
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};
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struct composite_conf {
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struct composite_conf {
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struct parm mux_parm;
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struct parm mux_parm;
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struct parm div_parm;
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struct parm div_parm;
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@ -89,7 +84,6 @@ struct composite_conf {
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enum clk_type {
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enum clk_type {
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CLK_FIXED_FACTOR,
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CLK_FIXED_FACTOR,
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CLK_FIXED_RATE,
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CLK_COMPOSITE,
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CLK_COMPOSITE,
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CLK_CPU,
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CLK_CPU,
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CLK_PLL,
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CLK_PLL,
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@ -105,32 +99,12 @@ struct clk_conf {
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unsigned long flags;
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unsigned long flags;
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union {
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union {
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struct fixed_fact_conf fixed_fact;
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struct fixed_fact_conf fixed_fact;
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struct fixed_rate_conf fixed_rate;
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const struct composite_conf *composite;
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const struct composite_conf *composite;
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struct pll_conf *pll;
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struct pll_conf *pll;
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const struct clk_div_table *div_table;
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const struct clk_div_table *div_table;
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} conf;
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} conf;
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};
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};
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#define FIXED_RATE_P(_ro, _ci, _cn, _f, _c) \
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{ \
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.reg_off = (_ro), \
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.clk_type = CLK_FIXED_RATE, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.flags = (_f), \
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.conf.fixed_rate.rate_parm = _c, \
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} \
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#define FIXED_RATE(_ci, _cn, _f, _r) \
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{ \
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.clk_type = CLK_FIXED_RATE, \
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.clk_id = (_ci), \
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.clk_name = (_cn), \
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.flags = (_f), \
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.conf.fixed_rate.rate = (_r), \
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} \
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#define PLL(_ro, _ci, _cn, _cp, _f, _c) \
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#define PLL(_ro, _ci, _cn, _cp, _f, _c) \
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{ \
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{ \
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.reg_off = (_ro), \
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.reg_off = (_ro), \
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@ -33,7 +33,6 @@
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*
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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*/
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#define MESON8B_REG_CTL0_ADDR 0x0000
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#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
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#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */
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#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
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#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */
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#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
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#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */
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@ -149,12 +148,25 @@ static const struct composite_conf mali_conf __initconst = {
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.gate_parm = PARM(0x00, 8, 1),
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.gate_parm = PARM(0x00, 8, 1),
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};
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};
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static const struct clk_conf meson8b_xtal_conf __initconst =
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static struct clk_fixed_rate meson8b_xtal = {
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FIXED_RATE_P(MESON8B_REG_CTL0_ADDR, CLKID_XTAL, "xtal", 0,
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.fixed_rate = 24000000,
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PARM(0x00, 4, 7));
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.hw.init = &(struct clk_init_data){
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.name = "xtal",
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.num_parents = 0,
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.ops = &clk_fixed_rate_ops,
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},
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};
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static struct clk_fixed_rate meson8b_zero = {
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.fixed_rate = 0,
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.hw.init = &(struct clk_init_data){
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.name = "zero",
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.num_parents = 0,
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.ops = &clk_fixed_rate_ops,
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},
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};
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static const struct clk_conf meson8b_clk_confs[] __initconst = {
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static const struct clk_conf meson8b_clk_confs[] __initconst = {
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FIXED_RATE(CLKID_ZERO, "zero", 0, 0),
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PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll",
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PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll",
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p_xtal, 0, &pll_confs),
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p_xtal, 0, &pll_confs),
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PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll",
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PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll",
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@ -174,23 +186,29 @@ static const struct clk_conf meson8b_clk_confs[] __initconst = {
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CLK_IGNORE_UNUSED, &mali_conf),
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CLK_IGNORE_UNUSED, &mali_conf),
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};
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};
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/*
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* FIXME we cannot register two providers w/o breaking things. Luckily only
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* clk81 is actually used by any drivers. Convert clk81 to use
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* clk_hw_onecell_data last and flip the switch to call of_clk_add_hw_provider
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* instead of of_clk_add_provider in the clk81 conversion patch to keep from
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* breaking bisect. Then delete this comment ;-)
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*/
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static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
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.hws = {
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[CLKID_XTAL] = &meson8b_xtal.hw,
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[CLKID_ZERO] = &meson8b_zero.hw,
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},
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.num = CLK_NR_CLKS,
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};
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static void __init meson8b_clkc_init(struct device_node *np)
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static void __init meson8b_clkc_init(struct device_node *np)
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{
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{
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void __iomem *clk_base;
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void __iomem *clk_base;
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int ret, clkid;
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if (!meson_clk_init(np, CLK_NR_CLKS))
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if (!meson_clk_init(np, CLK_NR_CLKS))
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return;
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return;
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/* XTAL */
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clk_base = of_iomap(np, 0);
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if (!clk_base) {
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pr_err("%s: Unable to map xtal base\n", __func__);
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return;
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}
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meson_clk_register_clks(&meson8b_xtal_conf, 1, clk_base);
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iounmap(clk_base);
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/* Generic clocks and PLLs */
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/* Generic clocks and PLLs */
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clk_base = of_iomap(np, 1);
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clk_base = of_iomap(np, 1);
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if (!clk_base) {
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if (!clk_base) {
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@ -198,8 +216,29 @@ static void __init meson8b_clkc_init(struct device_node *np)
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return;
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return;
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}
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}
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/*
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* register all clks
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* CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
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*/
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for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
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/* array might be sparse */
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if (!meson8b_hw_onecell_data.hws[clkid])
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continue;
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/* FIXME convert to devm_clk_register */
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ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[clkid]);
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if (ret)
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goto unregister;
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}
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meson_clk_register_clks(meson8b_clk_confs,
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meson_clk_register_clks(meson8b_clk_confs,
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ARRAY_SIZE(meson8b_clk_confs),
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ARRAY_SIZE(meson8b_clk_confs),
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clk_base);
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clk_base);
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return;
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/* FIXME remove after converting to platform_driver/devm_clk_register */
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unregister:
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for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
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clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
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}
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}
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CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);
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CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);
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