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dts: vt8500: Correct reference clock on WM8850 SoCs

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WM8850 SoCs use a 24Mhz reference clock for the PLLs but the SoC file
currently parents all PLLs to the 25Mhz reference clock.

This patch corrects the PLL parent clock references.

Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
This commit is contained in:
Tony Prisk
2013-05-17 21:30:05 +12:00
parent 9e7b6d3eda
commit e36572b64d
1 changed files with 7 additions and 7 deletions
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14
arch/arm/boot/dts/wm8850.dtsi
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@ -84,49 +84,49 @@
plla: plla { plla: plla {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x200>; reg = <0x200>;
}; };
pllb: pllb { pllb: pllb {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x204>; reg = <0x204>;
}; };
pllc: pllc { pllc: pllc {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x208>; reg = <0x208>;
}; };
plld: plld { plld: plld {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x20c>; reg = <0x20c>;
}; };
plle: plle { plle: plle {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x210>; reg = <0x210>;
}; };
pllf: pllf { pllf: pllf {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x214>; reg = <0x214>;
}; };
pllg: pllg { pllg: pllg {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "wm,wm8850-pll-clock"; compatible = "wm,wm8850-pll-clock";
clocks = <&ref25>; clocks = <&ref24>;
reg = <0x218>; reg = <0x218>;
}; };