This is the 5.10.187 stable release
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This commit is contained in:
Greg Kroah-Hartman
commit
db023c4bb0
2
Makefile
2
Makefile
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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PATCHLEVEL = 10
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SUBLEVEL = 186
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SUBLEVEL = 187
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EXTRAVERSION =
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NAME = Dare mighty things
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@ -5,6 +5,7 @@
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#include <asm/cpu.h>
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#include <linux/earlycpio.h>
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#include <linux/initrd.h>
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#include <asm/microcode_amd.h>
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struct ucode_patch {
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struct list_head plist;
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@ -48,11 +48,13 @@ extern void __init load_ucode_amd_bsp(unsigned int family);
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extern void load_ucode_amd_ap(unsigned int family);
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extern int __init save_microcode_in_initrd_amd(unsigned int family);
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void reload_ucode_amd(unsigned int cpu);
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extern void amd_check_microcode(void);
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#else
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static inline void __init load_ucode_amd_bsp(unsigned int family) {}
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static inline void load_ucode_amd_ap(unsigned int family) {}
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static inline int __init
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save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
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static inline void reload_ucode_amd(unsigned int cpu) {}
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static inline void amd_check_microcode(void) {}
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#endif
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#endif /* _ASM_X86_MICROCODE_AMD_H */
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@ -497,6 +497,7 @@
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#define MSR_AMD64_DE_CFG 0xc0011029
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT 1
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#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
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#define MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT 9
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#define MSR_AMD64_BU_CFG2 0xc001102a
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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@ -28,11 +28,6 @@
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#include "cpu.h"
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static const int amd_erratum_383[];
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static const int amd_erratum_400[];
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static const int amd_erratum_1054[];
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static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
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/*
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* nodes_per_socket: Stores the number of nodes per socket.
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* Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
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@ -40,6 +35,78 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
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*/
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static u32 nodes_per_socket = 1;
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/*
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* AMD errata checking
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*
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* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
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* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
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* have an OSVW id assigned, which it takes as first argument. Both take a
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* variable number of family-specific model-stepping ranges created by
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* AMD_MODEL_RANGE().
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*
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* Example:
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*
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* const int amd_erratum_319[] =
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* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
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* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
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* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
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*/
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#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
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#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
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#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
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((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
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#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
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#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
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#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
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static const int amd_erratum_400[] =
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AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
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AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
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static const int amd_erratum_383[] =
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AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
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/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
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static const int amd_erratum_1054[] =
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AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
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static const int amd_zenbleed[] =
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AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf),
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AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf),
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AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf));
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static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
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{
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int osvw_id = *erratum++;
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u32 range;
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u32 ms;
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if (osvw_id >= 0 && osvw_id < 65536 &&
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cpu_has(cpu, X86_FEATURE_OSVW)) {
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u64 osvw_len;
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rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
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if (osvw_id < osvw_len) {
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u64 osvw_bits;
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rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
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osvw_bits);
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return osvw_bits & (1ULL << (osvw_id & 0x3f));
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}
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}
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/* OSVW unavailable or ID unknown, match family-model-stepping range */
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ms = (cpu->x86_model << 4) | cpu->x86_stepping;
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while ((range = *erratum++))
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if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
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(ms >= AMD_MODEL_RANGE_START(range)) &&
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(ms <= AMD_MODEL_RANGE_END(range)))
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return true;
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return false;
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}
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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@ -968,6 +1035,47 @@ static void init_amd_zn(struct cpuinfo_x86 *c)
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}
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}
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static bool cpu_has_zenbleed_microcode(void)
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{
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u32 good_rev = 0;
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switch (boot_cpu_data.x86_model) {
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case 0x30 ... 0x3f: good_rev = 0x0830107a; break;
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case 0x60 ... 0x67: good_rev = 0x0860010b; break;
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case 0x68 ... 0x6f: good_rev = 0x08608105; break;
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case 0x70 ... 0x7f: good_rev = 0x08701032; break;
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case 0xa0 ... 0xaf: good_rev = 0x08a00008; break;
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default:
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return false;
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break;
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}
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if (boot_cpu_data.microcode < good_rev)
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return false;
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return true;
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}
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static void zenbleed_check(struct cpuinfo_x86 *c)
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{
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if (!cpu_has_amd_erratum(c, amd_zenbleed))
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return;
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if (cpu_has(c, X86_FEATURE_HYPERVISOR))
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return;
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if (!cpu_has(c, X86_FEATURE_AVX))
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return;
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if (!cpu_has_zenbleed_microcode()) {
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pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n");
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msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
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} else {
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msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT);
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}
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}
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static void init_amd(struct cpuinfo_x86 *c)
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{
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early_init_amd(c);
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@ -1058,6 +1166,8 @@ static void init_amd(struct cpuinfo_x86 *c)
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msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT);
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check_null_seg_clears_base(c);
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zenbleed_check(c);
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}
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#ifdef CONFIG_X86_32
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@ -1153,73 +1263,6 @@ static const struct cpu_dev amd_cpu_dev = {
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cpu_dev_register(amd_cpu_dev);
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/*
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* AMD errata checking
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*
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* Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
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* AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
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* have an OSVW id assigned, which it takes as first argument. Both take a
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* variable number of family-specific model-stepping ranges created by
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* AMD_MODEL_RANGE().
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*
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* Example:
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*
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* const int amd_erratum_319[] =
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* AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
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* AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
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* AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
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*/
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#define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
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#define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
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#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
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((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
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#define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
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#define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
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#define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
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static const int amd_erratum_400[] =
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AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
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AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
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static const int amd_erratum_383[] =
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AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
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/* #1054: Instructions Retired Performance Counter May Be Inaccurate */
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static const int amd_erratum_1054[] =
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AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));
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static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
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{
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int osvw_id = *erratum++;
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u32 range;
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u32 ms;
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if (osvw_id >= 0 && osvw_id < 65536 &&
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cpu_has(cpu, X86_FEATURE_OSVW)) {
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u64 osvw_len;
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rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
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if (osvw_id < osvw_len) {
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u64 osvw_bits;
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rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
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osvw_bits);
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return osvw_bits & (1ULL << (osvw_id & 0x3f));
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}
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}
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/* OSVW unavailable or ID unknown, match family-model-stepping range */
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ms = (cpu->x86_model << 4) | cpu->x86_stepping;
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while ((range = *erratum++))
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if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
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(ms >= AMD_MODEL_RANGE_START(range)) &&
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(ms <= AMD_MODEL_RANGE_END(range)))
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return true;
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return false;
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}
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void set_dr_addr_mask(unsigned long mask, int dr)
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{
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if (!boot_cpu_has(X86_FEATURE_BPEXT))
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@ -1238,3 +1281,15 @@ void set_dr_addr_mask(unsigned long mask, int dr)
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break;
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}
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}
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static void zenbleed_check_cpu(void *unused)
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{
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struct cpuinfo_x86 *c = &cpu_data(smp_processor_id());
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zenbleed_check(c);
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}
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void amd_check_microcode(void)
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{
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on_each_cpu(zenbleed_check_cpu, NULL, 1);
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}
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@ -2165,6 +2165,8 @@ void microcode_check(struct cpuinfo_x86 *prev_info)
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perf_check_microcode();
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amd_check_microcode();
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store_cpu_caps(&curr_info);
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if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
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@ -700,7 +700,7 @@ static enum ucode_state apply_microcode_amd(int cpu)
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rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
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/* need to apply patch? */
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if (rev >= mc_amd->hdr.patch_id) {
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if (rev > mc_amd->hdr.patch_id) {
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ret = UCODE_OK;
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goto out;
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}
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