mmc: sdhci-esdhc-imx: add tuning-step setting support
tuning-step is the delay cell steps in tuning procedure. The default value of tuning-step is 1. Some boards or cards need another value to pass the tuning procedure. For example, imx7d-sdb board need the tuning-step value as 2, otherwise it can't pass the tuning procedure. So this patch add the tuning-step setting in driver, so that user can set the tuning-step value in dts. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -75,6 +75,7 @@
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#define ESDHC_STD_TUNING_EN (1 << 24)
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#define ESDHC_STD_TUNING_EN (1 << 24)
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/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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#define ESDHC_TUNING_START_TAP 0x1
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#define ESDHC_TUNING_START_TAP 0x1
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#define ESDHC_TUNING_STEP_SHIFT 16
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/* pinctrl state */
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/* pinctrl state */
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#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
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#define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
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@ -474,6 +475,7 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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} else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
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} else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
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u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
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u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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u32 tuning_ctrl;
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if (val & SDHCI_CTRL_TUNED_CLK) {
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if (val & SDHCI_CTRL_TUNED_CLK) {
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v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
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v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
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} else {
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} else {
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@ -484,6 +486,11 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
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if (val & SDHCI_CTRL_EXEC_TUNING) {
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if (val & SDHCI_CTRL_EXEC_TUNING) {
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v |= ESDHC_MIX_CTRL_EXE_TUNE;
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v |= ESDHC_MIX_CTRL_EXE_TUNE;
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m |= ESDHC_MIX_CTRL_FBCLK_SEL;
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m |= ESDHC_MIX_CTRL_FBCLK_SEL;
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tuning_ctrl = readl(host->ioaddr + ESDHC_TUNING_CTRL);
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tuning_ctrl |= ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP;
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if (imx_data->boarddata.tuning_step)
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tuning_ctrl |= imx_data->boarddata.tuning_step << ESDHC_TUNING_STEP_SHIFT;
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writel(tuning_ctrl, host->ioaddr + ESDHC_TUNING_CTRL);
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} else {
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} else {
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v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
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v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
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}
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}
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@ -963,6 +970,8 @@ sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
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if (gpio_is_valid(boarddata->wp_gpio))
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if (gpio_is_valid(boarddata->wp_gpio))
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boarddata->wp_type = ESDHC_WP_GPIO;
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boarddata->wp_type = ESDHC_WP_GPIO;
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of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step);
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if (of_find_property(np, "no-1-8-v", NULL))
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if (of_find_property(np, "no-1-8-v", NULL))
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boarddata->support_vsel = false;
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boarddata->support_vsel = false;
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else
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else
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@ -45,5 +45,6 @@ struct esdhc_platform_data {
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int max_bus_width;
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int max_bus_width;
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bool support_vsel;
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bool support_vsel;
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unsigned int delay_line;
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unsigned int delay_line;
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unsigned int tuning_step; /* The delay cell steps in tuning procedure */
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};
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};
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#endif /* __ASM_ARCH_IMX_ESDHC_H */
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#endif /* __ASM_ARCH_IMX_ESDHC_H */
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