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pinctrl: sunxi: Add I/O bias setting for H6 R-PIO

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commit fc153c8f283bf5925615195fc9d4056414d7b168 upstream.

H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.

The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.

Fixes: cc62383fce ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Samuel Holland 2022-07-12 21:52:29 -05:00 committed by Greg Kroah-Hartman
parent e8f5699a82
commit d35d9bba29
2 changed files with 5 additions and 3 deletions
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1
drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
View File

@ -105,6 +105,7 @@ static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
.npins = ARRAY_SIZE(sun50i_h6_r_pins), .npins = ARRAY_SIZE(sun50i_h6_r_pins),
.pin_base = PL_BASE, .pin_base = PL_BASE,
.irq_banks = 2, .irq_banks = 2,
.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
}; };
static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev) static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)

7
drivers/pinctrl/sunxi/pinctrl-sunxi.c
View File

@ -624,7 +624,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
unsigned pin, unsigned pin,
struct regulator *supply) struct regulator *supply)
{ {
unsigned short bank = pin / PINS_PER_BANK; unsigned short bank;
unsigned long flags; unsigned long flags;
u32 val, reg; u32 val, reg;
int uV; int uV;
@ -640,6 +640,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
if (uV == 0) if (uV == 0)
return 0; return 0;
pin -= pctl->desc->pin_base;
bank = pin / PINS_PER_BANK;
switch (pctl->desc->io_bias_cfg_variant) { switch (pctl->desc->io_bias_cfg_variant) {
case BIAS_VOLTAGE_GRP_CONFIG: case BIAS_VOLTAGE_GRP_CONFIG:
/* /*
@ -657,8 +660,6 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
else else
val = 0xD; /* 3.3V */ val = 0xD; /* 3.3V */
pin -= pctl->desc->pin_base;
reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
reg &= ~IO_BIAS_MASK; reg &= ~IO_BIAS_MASK;
writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));