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Merge 5.10.201 into android12-5.10-lts

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Changes in 5.10.201
	iov_iter, x86: Be consistent about the __user tag on copy_mc_to_user()
	sched/uclamp: Ignore (util == 0) optimization in feec() when p_util_max = 0
	vfs: fix readahead(2) on block devices
	x86/srso: Fix SBPB enablement for (possible) future fixed HW
	futex: Don't include process MM in futex key on no-MMU
	x86/boot: Fix incorrect startup_gdt_descr.size
	pstore/platform: Add check for kstrdup
	genirq/matrix: Exclude managed interrupts in irq_matrix_allocated()
	i40e: fix potential memory leaks in i40e_remove()
	udp: add missing WRITE_ONCE() around up->encap_rcv
	tcp: call tcp_try_undo_recovery when an RTOd TFO SYNACK is ACKed
	overflow: Implement size_t saturating arithmetic helpers
	gve: Use size_add() in call to struct_size()
	mlxsw: Use size_mul() in call to struct_size()
	tipc: Use size_add() in calls to struct_size()
	net: spider_net: Use size_add() in call to struct_size()
	wifi: rtw88: debug: Fix the NULL vs IS_ERR() bug for debugfs_create_file()
	wifi: mt76: mt7603: rework/fix rx pse hang check
	tcp_metrics: add missing barriers on delete
	tcp_metrics: properly set tp->snd_ssthresh in tcp_init_metrics()
	tcp_metrics: do not create an entry from tcp_init_metrics()
	wifi: rtlwifi: fix EDCA limit set by BT coexistence
	can: dev: can_restart(): don't crash kernel if carrier is OK
	can: dev: can_restart(): fix race condition between controller restart and netif_carrier_on()
	PM / devfreq: rockchip-dfi: Make pmu regmap mandatory
	thermal: core: prevent potential string overflow
	r8169: use tp_to_dev instead of open code
	r8169: fix rare issue with broken rx after link-down on RTL8125
	chtls: fix tp->rcv_tstamp initialization
	tcp: fix cookie_init_timestamp() overflows
	ACPI: sysfs: Fix create_pnp_modalias() and create_of_modalias()
	ipv6: avoid atomic fragment on GSO packets
	net: add DEV_STATS_READ() helper
	ipvlan: properly track tx_errors
	regmap: debugfs: Fix a erroneous check after snprintf()
	clk: qcom: clk-rcg2: Fix clock rate overflow for high parent frequencies
	clk: qcom: mmcc-msm8998: Add hardware clockgating registers to some clks
	clk: qcom: mmcc-msm8998: Don't check halt bit on some branch clks
	clk: qcom: mmcc-msm8998: Set bimc_smmu_gdsc always on
	clk: qcom: mmcc-msm8998: Fix the SMMU GDSC
	clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents
	clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src
	clk: imx: Select MXC_CLK for CLK_IMX8QXP
	clk: imx: imx8mq: correct error handling path
	clk: asm9260: use parent index to link the reference clock
	clk: linux/clk-provider.h: fix kernel-doc warnings and typos
	spi: nxp-fspi: use the correct ioremap function
	clk: keystone: pll: fix a couple NULL vs IS_ERR() checks
	clk: ti: Add ti_dt_clk_name() helper to use clock-output-names
	clk: ti: Update pll and clockdomain clocks to use ti_dt_clk_name()
	clk: ti: Update component clocks to use ti_dt_clk_name()
	clk: ti: change ti_clk_register[_omap_hw]() API
	clk: ti: fix double free in of_ti_divider_clk_setup()
	clk: npcm7xx: Fix incorrect kfree
	clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data
	clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data
	clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data
	clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data
	clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data
	clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data
	clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM
	platform/x86: wmi: Fix probe failure when failing to register WMI devices
	platform/x86: wmi: remove unnecessary initializations
	platform/x86: wmi: Fix opening of char device
	hwmon: (axi-fan-control) Support temperature vs pwm points
	hwmon: (axi-fan-control) Fix possible NULL pointer dereference
	hwmon: (coretemp) Fix potentially truncated sysfs attribute name
	drm/rockchip: vop: Fix reset of state in duplicate state crtc funcs
	drm/rockchip: vop: Fix call to crtc reset helper
	drm/radeon: possible buffer overflow
	drm/bridge: tc358768: Fix use of uninitialized variable
	drm/bridge: tc358768: Disable non-continuous clock mode
	drm/bridge: tc358768: Fix bit updates
	drm/mediatek: Fix iommu fault during crtc enabling
	drm/rockchip: cdn-dp: Fix some error handling paths in cdn_dp_probe()
	arm64/arm: xen: enlighten: Fix KPTI checks
	drm/rockchip: Fix type promotion bug in rockchip_gem_iommu_map()
	xen-pciback: Consider INTx disabled when MSI/MSI-X is enabled
	arm64: dts: qcom: msm8916: Fix iommu local address range
	arm64: dts: qcom: sdm845-mtp: fix WiFi configuration
	ARM: dts: qcom: mdm9615: populate vsdcc fixed regulator
	soc: qcom: llcc: Handle a second device without data corruption
	firmware: ti_sci: Mark driver as non removable
	clk: scmi: Free scmi_clk allocated when the clocks with invalid info are skipped
	selftests/pidfd: Fix ksft print formats
	selftests/resctrl: Ensure the benchmark commands fits to its array
	crypto: hisilicon/hpre - Fix a erroneous check after snprintf()
	hwrng: geode - fix accessing registers
	libnvdimm/of_pmem: Use devm_kstrdup instead of kstrdup and check its return value
	nd_btt: Make BTT lanes preemptible
	crypto: caam/qi2 - fix Chacha20 + Poly1305 self test failure
	crypto: caam/jr - fix Chacha20 + Poly1305 self test failure
	crypto: qat - mask device capabilities with soft straps
	crypto: qat - increase size of buffers
	hid: cp2112: Fix duplicate workqueue initialization
	ARM: 9321/1: memset: cast the constant byte to unsigned char
	ext4: move 'ix' sanity check to corrent position
	ASoC: fsl: mpc5200_dma.c: Fix warning of Function parameter or member not described
	IB/mlx5: Fix rdma counter binding for RAW QP
	RDMA/hns: Fix uninitialized ucmd in hns_roce_create_qp_common()
	RDMA/hns: Fix signed-unsigned mixed comparisons
	ASoC: fsl: Fix PM disable depth imbalance in fsl_easrc_probe
	scsi: ufs: core: Leave space for '\0' in utf8 desc string
	RDMA/hfi1: Workaround truncation compilation error
	hid: cp2112: Fix IRQ shutdown stopping polling for all IRQs on chip
	sh: bios: Revive earlyprintk support
	Revert "HID: logitech-hidpp: add a module parameter to keep firmware gestures"
	HID: logitech-hidpp: Remove HIDPP_QUIRK_NO_HIDINPUT quirk
	HID: logitech-hidpp: Don't restart IO, instead defer hid_connect() only
	HID: logitech-hidpp: Revert "Don't restart communication if not necessary"
	HID: logitech-hidpp: Move get_wireless_feature_index() check to hidpp_connect_event()
	ASoC: Intel: Skylake: Fix mem leak when parsing UUIDs fails
	padata: Convert from atomic_t to refcount_t on parallel_data->refcnt
	padata: Fix refcnt handling in padata_free_shell()
	ASoC: ams-delta.c: use component after check
	mfd: core: Un-constify mfd_cell.of_reg
	mfd: core: Ensure disabled devices are skipped without aborting
	mfd: dln2: Fix double put in dln2_probe
	leds: pwm: Don't disable the PWM when the LED should be off
	leds: trigger: ledtrig-cpu:: Fix 'output may be truncated' issue for 'cpu'
	tty: tty_jobctrl: fix pid memleak in disassociate_ctty()
	livepatch: Fix missing newline character in klp_resolve_symbols()
	usb: dwc2: fix possible NULL pointer dereference caused by driver concurrency
	dmaengine: ti: edma: handle irq_of_parse_and_map() errors
	misc: st_core: Do not call kfree_skb() under spin_lock_irqsave()
	tools: iio: privatize globals and functions in iio_generic_buffer.c file
	tools: iio: iio_generic_buffer: Fix some integer type and calculation
	tools: iio: iio_generic_buffer ensure alignment
	USB: usbip: fix stub_dev hub disconnect
	dmaengine: pxa_dma: Remove an erroneous BUG_ON() in pxad_free_desc()
	f2fs: fix to initialize map.m_pblk in f2fs_precache_extents()
	interconnect: qcom: sc7180: Retire DEFINE_QBCM
	interconnect: qcom: sc7180: Set ACV enable_mask
	modpost: fix tee MODULE_DEVICE_TABLE built on big-endian host
	powerpc/40x: Remove stale PTE_ATOMIC_UPDATES macro
	powerpc/xive: Fix endian conversion size
	powerpc/imc-pmu: Use the correct spinlock initializer.
	powerpc/pseries: fix potential memory leak in init_cpu_associativity()
	xhci: Loosen RPM as default policy to cover for AMD xHC 1.1
	usb: host: xhci-plat: fix possible kernel oops while resuming
	perf machine: Avoid out of bounds LBR memory read
	perf hist: Add missing puts to hist__account_cycles
	i3c: Fix potential refcount leak in i3c_master_register_new_i3c_devs
	rtc: pcf85363: fix wrong mask/val parameters in regmap_update_bits call
	pcmcia: cs: fix possible hung task and memory leak pccardd()
	pcmcia: ds: fix refcount leak in pcmcia_device_add()
	pcmcia: ds: fix possible name leak in error path in pcmcia_device_add()
	media: i2c: max9286: Fix some redundant of_node_put() calls
	media: bttv: fix use after free error due to btv->timeout timer
	media: s3c-camif: Avoid inappropriate kfree()
	media: vidtv: psi: Add check for kstrdup
	media: vidtv: mux: Add check and kfree for kstrdup
	media: cedrus: Fix clock/reset sequence
	media: dvb-usb-v2: af9035: fix missing unlock
	regmap: prevent noinc writes from clobbering cache
	pwm: sti: Avoid conditional gotos
	pwm: sti: Reduce number of allocations and drop usage of chip_data
	pwm: brcmstb: Utilize appropriate clock APIs in suspend/resume
	Input: synaptics-rmi4 - fix use after free in rmi_unregister_function()
	llc: verify mac len before reading mac header
	hsr: Prevent use after free in prp_create_tagged_frame()
	tipc: Change nla_policy for bearer-related names to NLA_NUL_STRING
	inet: shrink struct flowi_common
	dccp: Call security_inet_conn_request() after setting IPv4 addresses.
	dccp/tcp: Call security_inet_conn_request() after setting IPv6 addresses.
	net: r8169: Disable multicast filter for RTL8168H and RTL8107E
	Fix termination state for idr_for_each_entry_ul()
	net: stmmac: xgmac: Enable support for multiple Flexible PPS outputs
	net/smc: fix dangling sock under state SMC_APPFINCLOSEWAIT
	net/smc: allow cdc msg send rather than drop it with NULL sndbuf_desc
	net/smc: put sk reference if close work was canceled
	tg3: power down device only on SYSTEM_POWER_OFF
	r8169: respect userspace disabling IFF_MULTICAST
	netfilter: xt_recent: fix (increase) ipv6 literal buffer length
	netfilter: nft_redir: use `struct nf_nat_range2` throughout and deduplicate eval call-backs
	netfilter: nat: fix ipv6 nat redirect with mapped and scoped addresses
	x86: Share definition of __is_canonical_address()
	x86/sev-es: Allow copy_from_kernel_nofault() in earlier boot
	drm/syncobj: fix DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE
	spi: spi-zynq-qspi: add spi-mem to driver kconfig dependencies
	fbdev: imsttfb: Fix error path of imsttfb_probe()
	fbdev: imsttfb: fix a resource leak in probe
	fbdev: fsl-diu-fb: mark wr_reg_wa() static
	tracing/kprobes: Fix the order of argument descriptions
	Revert "mmc: core: Capture correct oemid-bits for eMMC cards"
	btrfs: use u64 for buffer sizes in the tree search ioctls
	Linux 5.10.201

Change-Id: I0ce874e25eb6aeebf5826d6ef843fdbbf55d7c7d
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
This commit is contained in:
Greg Kroah-Hartman 2023-11-26 14:09:19 +00:00
commit cf3a19d56e
207 changed files with 1779 additions and 980 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
Documentation/process/deprecated.rst
View File

@ -70,6 +70,9 @@ Instead, the 2-factor form of the allocator should be used::
foo = kmalloc_array(count, size, GFP_KERNEL); foo = kmalloc_array(count, size, GFP_KERNEL);
Specifically, kmalloc() can be replaced with kmalloc_array(), and
kzalloc() can be replaced with kcalloc().
If no 2-factor form is available, the saturate-on-overflow helpers should If no 2-factor form is available, the saturate-on-overflow helpers should
be used:: be used::
@ -90,9 +93,20 @@ Instead, use the helper::
array usage and switch to a `flexible array member array usage and switch to a `flexible array member
<#zero-length-and-one-element-arrays>`_ instead. <#zero-length-and-one-element-arrays>`_ instead.
See array_size(), array3_size(), and struct_size(), For other calculations, please compose the use of the size_mul(),
for more details as well as the related check_add_overflow() and size_add(), and size_sub() helpers. For example, in the case of::
check_mul_overflow() family of functions.
foo = krealloc(current_size + chunk_size * (count - 3), GFP_KERNEL);
Instead, use the helpers::
foo = krealloc(size_add(current_size,
size_mul(chunk_size,
size_sub(count, 3))), GFP_KERNEL);
For more details, also see array3_size() and flex_array_size(),
as well as the related check_mul_overflow(), check_add_overflow(),
check_sub_overflow(), and check_shl_overflow() family of functions.
simple_strtol(), simple_strtoll(), simple_strtoul(), simple_strtoull() simple_strtol(), simple_strtoll(), simple_strtoul(), simple_strtoull()
---------------------------------------------------------------------- ----------------------------------------------------------------------

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0 # SPDX-License-Identifier: GPL-2.0
VERSION = 5 VERSION = 5
PATCHLEVEL = 10 PATCHLEVEL = 10
SUBLEVEL = 200 SUBLEVEL = 201
EXTRAVERSION = EXTRAVERSION =
NAME = Dare mighty things NAME = Dare mighty things

14
arch/arm/boot/dts/qcom-mdm9615.dtsi
View File

@ -82,14 +82,12 @@ cxo_board {
}; };
}; };
regulators { vsdcc_fixed: vsdcc-regulator {
vsdcc_fixed: vsdcc-regulator { compatible = "regulator-fixed";
compatible = "regulator-fixed"; regulator-name = "SDCC Power";
regulator-name = "SDCC Power"; regulator-min-microvolt = <2700000>;
regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2700000>;
regulator-max-microvolt = <2700000>; regulator-always-on;
regulator-always-on;
};
}; };
soc: soc { soc: soc {

1
arch/arm/lib/memset.S
View File

@ -16,6 +16,7 @@
ENTRY(mmioset) ENTRY(mmioset)
ENTRY(memset) ENTRY(memset)
UNWIND( .fnstart ) UNWIND( .fnstart )
and r1, r1, #255 @ cast to unsigned char
ands r3, r0, #3 @ 1 unaligned? ands r3, r0, #3 @ 1 unaligned?
mov ip, r0 @ preserve r0 as return value mov ip, r0 @ preserve r0 as return value
bne 6f @ 1 bne 6f @ 1

25
arch/arm/xen/enlighten.c
View File

@ -159,9 +159,6 @@ static int xen_starting_cpu(unsigned int cpu)
BUG_ON(err); BUG_ON(err);
per_cpu(xen_vcpu, cpu) = vcpup; per_cpu(xen_vcpu, cpu) = vcpup;
if (!xen_kernel_unmapped_at_usr())
xen_setup_runstate_info(cpu);
after_register_vcpu_info: after_register_vcpu_info:
enable_percpu_irq(xen_events_irq, 0); enable_percpu_irq(xen_events_irq, 0);
return 0; return 0;
@ -394,9 +391,6 @@ static int __init xen_guest_init(void)
return -EINVAL; return -EINVAL;
} }
if (!xen_kernel_unmapped_at_usr())
xen_time_setup_guest();
if (xen_initial_domain()) if (xen_initial_domain())
pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier); pvclock_gtod_register_notifier(&xen_pvclock_gtod_notifier);
@ -406,7 +400,13 @@ static int __init xen_guest_init(void)
} }
early_initcall(xen_guest_init); early_initcall(xen_guest_init);
static int __init xen_pm_init(void) static int xen_starting_runstate_cpu(unsigned int cpu)
{
xen_setup_runstate_info(cpu);
return 0;
}
static int __init xen_late_init(void)
{ {
if (!xen_domain()) if (!xen_domain())
return -ENODEV; return -ENODEV;
@ -419,9 +419,16 @@ static int __init xen_pm_init(void)
do_settimeofday64(&ts); do_settimeofday64(&ts);
} }
return 0; if (xen_kernel_unmapped_at_usr())
return 0;
xen_time_setup_guest();
return cpuhp_setup_state(CPUHP_AP_ARM_XEN_RUNSTATE_STARTING,
"arm/xen_runstate:starting",
xen_starting_runstate_cpu, NULL);
} }
late_initcall(xen_pm_init); late_initcall(xen_late_init);
/* empty stubs */ /* empty stubs */

2
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -1175,7 +1175,7 @@ apps_iommu: iommu@1ef0000 {
#size-cells = <1>; #size-cells = <1>;
#iommu-cells = <1>; #iommu-cells = <1>;
compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x01e20000 0x40000>; ranges = <0 0x01e20000 0x20000>;
reg = <0x01ef0000 0x3000>; reg = <0x01ef0000 0x3000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>, clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_CLK>; <&gcc GCC_APSS_TCU_CLK>;

2
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View File

@ -564,6 +564,8 @@ &wifi {
vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
}; };
/* PINCTRL - additions to nodes defined in sdm845.dtsi */ /* PINCTRL - additions to nodes defined in sdm845.dtsi */

3
arch/powerpc/include/asm/nohash/32/pte-40x.h
View File

@ -69,9 +69,6 @@
#define _PTE_NONE_MASK 0 #define _PTE_NONE_MASK 0
/* Until my rework is finished, 40x still needs atomic PTE updates */
#define PTE_ATOMIC_UPDATES 1
#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED) #define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
#define _PAGE_BASE (_PAGE_BASE_NC) #define _PAGE_BASE (_PAGE_BASE_NC)

2
arch/powerpc/perf/imc-pmu.c
View File

@ -50,7 +50,7 @@ static int trace_imc_mem_size;
* core and trace-imc * core and trace-imc
*/ */
static struct imc_pmu_ref imc_global_refc = { static struct imc_pmu_ref imc_global_refc = {
.lock = __SPIN_LOCK_INITIALIZER(imc_global_refc.lock), .lock = __SPIN_LOCK_UNLOCKED(imc_global_refc.lock),
.id = 0, .id = 0,
.refc = 0, .refc = 0,
}; };

4
arch/powerpc/platforms/pseries/lpar.c
View File

@ -523,8 +523,10 @@ static ssize_t vcpudispatch_stats_write(struct file *file, const char __user *p,
if (cmd) { if (cmd) {
rc = init_cpu_associativity(); rc = init_cpu_associativity();
if (rc) if (rc) {
destroy_cpu_associativity();
goto out; goto out;
}
for_each_possible_cpu(cpu) { for_each_possible_cpu(cpu) {
disp = per_cpu_ptr(&vcpu_disp_data, cpu); disp = per_cpu_ptr(&vcpu_disp_data, cpu);

2
arch/powerpc/sysdev/xive/native.c
View File

@ -779,7 +779,7 @@ int xive_native_get_queue_info(u32 vp_id, u32 prio,
if (out_qpage) if (out_qpage)
*out_qpage = be64_to_cpu(qpage); *out_qpage = be64_to_cpu(qpage);
if (out_qsize) if (out_qsize)
*out_qsize = be32_to_cpu(qsize); *out_qsize = be64_to_cpu(qsize);
if (out_qeoi_page) if (out_qeoi_page)
*out_qeoi_page = be64_to_cpu(qeoi_page); *out_qeoi_page = be64_to_cpu(qeoi_page);
if (out_escalate_irq) if (out_escalate_irq)

11
arch/sh/Kconfig.debug
View File

@ -25,6 +25,17 @@ config STACK_DEBUG
every function call and will therefore incur a major every function call and will therefore incur a major
performance hit. Most users should say N. performance hit. Most users should say N.
config EARLY_PRINTK
bool "Early printk"
depends on SH_STANDARD_BIOS
help
Say Y here to redirect kernel printk messages to the serial port
used by the SH-IPL bootloader, starting very early in the boot
process and ending when the kernel's serial console is initialised.
This option is only useful while porting the kernel to a new machine,
when the kernel may crash or hang before the serial console is
initialised. If unsure, say N.
config 4KSTACKS config 4KSTACKS
bool "Use 4Kb for kernel stacks instead of 8Kb" bool "Use 4Kb for kernel stacks instead of 8Kb"
depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB

14
arch/x86/events/intel/pt.c
View File

@ -1360,20 +1360,10 @@ static void pt_addr_filters_fini(struct perf_event *event)
} }
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
static u64 canonical_address(u64 vaddr, u8 vaddr_bits)
{
return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits);
}
static u64 is_canonical_address(u64 vaddr, u8 vaddr_bits)
{
return canonical_address(vaddr, vaddr_bits) == vaddr;
}
/* Clamp to a canonical address greater-than-or-equal-to the address given */ /* Clamp to a canonical address greater-than-or-equal-to the address given */
static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits) static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits)
{ {
return is_canonical_address(vaddr, vaddr_bits) ? return __is_canonical_address(vaddr, vaddr_bits) ?
vaddr : vaddr :
-BIT_ULL(vaddr_bits - 1); -BIT_ULL(vaddr_bits - 1);
} }
@ -1381,7 +1371,7 @@ static u64 clamp_to_ge_canonical_addr(u64 vaddr, u8 vaddr_bits)
/* Clamp to a canonical address less-than-or-equal-to the address given */ /* Clamp to a canonical address less-than-or-equal-to the address given */
static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits) static u64 clamp_to_le_canonical_addr(u64 vaddr, u8 vaddr_bits)
{ {
return is_canonical_address(vaddr, vaddr_bits) ? return __is_canonical_address(vaddr, vaddr_bits) ?
vaddr : vaddr :
BIT_ULL(vaddr_bits - 1) - 1; BIT_ULL(vaddr_bits - 1) - 1;
} }

10
arch/x86/include/asm/page.h
View File

@ -71,6 +71,16 @@ static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
extern bool __virt_addr_valid(unsigned long kaddr); extern bool __virt_addr_valid(unsigned long kaddr);
#define virt_addr_valid(kaddr) __virt_addr_valid((unsigned long) (kaddr)) #define virt_addr_valid(kaddr) __virt_addr_valid((unsigned long) (kaddr))
static __always_inline u64 __canonical_address(u64 vaddr, u8 vaddr_bits)
{
return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits);
}
static __always_inline u64 __is_canonical_address(u64 vaddr, u8 vaddr_bits)
{
return __canonical_address(vaddr, vaddr_bits) == vaddr;
}
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
#include <asm-generic/memory_model.h> #include <asm-generic/memory_model.h>

2
arch/x86/include/asm/uaccess.h
View File

@ -446,7 +446,7 @@ copy_mc_to_kernel(void *to, const void *from, unsigned len);
#define copy_mc_to_kernel copy_mc_to_kernel #define copy_mc_to_kernel copy_mc_to_kernel
unsigned long __must_check unsigned long __must_check
copy_mc_to_user(void *to, const void *from, unsigned len); copy_mc_to_user(void __user *to, const void *from, unsigned len);
#endif #endif
/* /*

2
arch/x86/kernel/cpu/bugs.c
View File

@ -2407,7 +2407,7 @@ static void __init srso_select_mitigation(void)
pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode")); pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode"));
pred_cmd: pred_cmd:
if ((boot_cpu_has(X86_FEATURE_SRSO_NO) || srso_cmd == SRSO_CMD_OFF) && if ((!boot_cpu_has_bug(X86_BUG_SRSO) || srso_cmd == SRSO_CMD_OFF) &&
boot_cpu_has(X86_FEATURE_SBPB)) boot_cpu_has(X86_FEATURE_SBPB))
x86_pred_cmd = PRED_CMD_SBPB; x86_pred_cmd = PRED_CMD_SBPB;
} }

2
arch/x86/kernel/head64.c
View File

@ -80,7 +80,7 @@ static struct desc_struct startup_gdt[GDT_ENTRIES] = {
* while the kernel still uses a direct mapping. * while the kernel still uses a direct mapping.
*/ */
static struct desc_ptr startup_gdt_descr = { static struct desc_ptr startup_gdt_descr = {
.size = sizeof(startup_gdt), .size = sizeof(startup_gdt)-1,
.address = 0, .address = 0,
}; };

4
arch/x86/kvm/emulate.c
View File

@ -688,7 +688,7 @@ static inline u8 ctxt_virt_addr_bits(struct x86_emulate_ctxt *ctxt)
static inline bool emul_is_noncanonical_address(u64 la, static inline bool emul_is_noncanonical_address(u64 la,
struct x86_emulate_ctxt *ctxt) struct x86_emulate_ctxt *ctxt)
{ {
return get_canonical(la, ctxt_virt_addr_bits(ctxt)) != la; return !__is_canonical_address(la, ctxt_virt_addr_bits(ctxt));
} }
/* /*
@ -738,7 +738,7 @@ static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
case X86EMUL_MODE_PROT64: case X86EMUL_MODE_PROT64:
*linear = la; *linear = la;
va_bits = ctxt_virt_addr_bits(ctxt); va_bits = ctxt_virt_addr_bits(ctxt);
if (get_canonical(la, va_bits) != la) if (!__is_canonical_address(la, va_bits))
goto bad; goto bad;
*max_size = min_t(u64, ~0u, (1ull << va_bits) - la); *max_size = min_t(u64, ~0u, (1ull << va_bits) - la);

2
arch/x86/kvm/x86.c
View File

@ -1640,7 +1640,7 @@ static int __kvm_set_msr(struct kvm_vcpu *vcpu, u32 index, u64 data,
* value, and that something deterministic happens if the guest * value, and that something deterministic happens if the guest
* invokes 64-bit SYSENTER. * invokes 64-bit SYSENTER.
*/ */
data = get_canonical(data, vcpu_virt_addr_bits(vcpu)); data = __canonical_address(data, vcpu_virt_addr_bits(vcpu));
} }
msr.data = data; msr.data = data;

7
arch/x86/kvm/x86.h
View File

@ -156,14 +156,9 @@ static inline u8 vcpu_virt_addr_bits(struct kvm_vcpu *vcpu)
return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48; return kvm_read_cr4_bits(vcpu, X86_CR4_LA57) ? 57 : 48;
} }
static inline u64 get_canonical(u64 la, u8 vaddr_bits)
{
return ((int64_t)la << (64 - vaddr_bits)) >> (64 - vaddr_bits);
}
static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu) static inline bool is_noncanonical_address(u64 la, struct kvm_vcpu *vcpu)
{ {
return get_canonical(la, vcpu_virt_addr_bits(vcpu)) != la; return !__is_canonical_address(la, vcpu_virt_addr_bits(vcpu));
} }
static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu, static inline void vcpu_cache_mmio_info(struct kvm_vcpu *vcpu,

8
arch/x86/lib/copy_mc.c
View File

@ -74,23 +74,23 @@ unsigned long __must_check copy_mc_to_kernel(void *dst, const void *src, unsigne
} }
EXPORT_SYMBOL_GPL(copy_mc_to_kernel); EXPORT_SYMBOL_GPL(copy_mc_to_kernel);
unsigned long __must_check copy_mc_to_user(void *dst, const void *src, unsigned len) unsigned long __must_check copy_mc_to_user(void __user *dst, const void *src, unsigned len)
{ {
unsigned long ret; unsigned long ret;
if (copy_mc_fragile_enabled) { if (copy_mc_fragile_enabled) {
__uaccess_begin(); __uaccess_begin();
ret = copy_mc_fragile(dst, src, len); ret = copy_mc_fragile((__force void *)dst, src, len);
__uaccess_end(); __uaccess_end();
return ret; return ret;
} }
if (static_cpu_has(X86_FEATURE_ERMS)) { if (static_cpu_has(X86_FEATURE_ERMS)) {
__uaccess_begin(); __uaccess_begin();
ret = copy_mc_enhanced_fast_string(dst, src, len); ret = copy_mc_enhanced_fast_string((__force void *)dst, src, len);
__uaccess_end(); __uaccess_end();
return ret; return ret;
} }
return copy_user_generic(dst, src, len); return copy_user_generic((__force void *)dst, src, len);
} }

24
arch/x86/mm/maccess.c
View File

@ -4,22 +4,26 @@
#include <linux/kernel.h> #include <linux/kernel.h>
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
static __always_inline u64 canonical_address(u64 vaddr, u8 vaddr_bits)
{
return ((s64)vaddr << (64 - vaddr_bits)) >> (64 - vaddr_bits);
}
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)
{ {
unsigned long vaddr = (unsigned long)unsafe_src; unsigned long vaddr = (unsigned long)unsafe_src;
/* /*
* Range covering the highest possible canonical userspace address * Do not allow userspace addresses. This disallows
* as well as non-canonical address range. For the canonical range * normal userspace and the userspace guard page:
* we also need to include the userspace guard page.
*/ */
return vaddr >= TASK_SIZE_MAX + PAGE_SIZE && if (vaddr < TASK_SIZE_MAX + PAGE_SIZE)
canonical_address(vaddr, boot_cpu_data.x86_virt_bits) == vaddr; return false;
/*
* Allow everything during early boot before 'x86_virt_bits'
* is initialized. Needed for instruction decoding in early
* exception handlers.
*/
if (!boot_cpu_data.x86_virt_bits)
return true;
return __is_canonical_address(vaddr, boot_cpu_data.x86_virt_bits);
} }
#else #else
bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size) bool copy_from_kernel_nofault_allowed(const void *unsafe_src, size_t size)

10
drivers/acpi/device_sysfs.c
View File

@ -156,8 +156,8 @@ static int create_pnp_modalias(struct acpi_device *acpi_dev, char *modalias,
return 0; return 0;
len = snprintf(modalias, size, "acpi:"); len = snprintf(modalias, size, "acpi:");
if (len <= 0) if (len >= size)
return len; return -ENOMEM;
size -= len; size -= len;
@ -210,8 +210,10 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer); len = snprintf(modalias, size, "of:N%sT", (char *)buf.pointer);
ACPI_FREE(buf.pointer); ACPI_FREE(buf.pointer);
if (len <= 0) if (len >= size)
return len; return -ENOMEM;
size -= len;
of_compatible = acpi_dev->data.of_compatible; of_compatible = acpi_dev->data.of_compatible;
if (of_compatible->type == ACPI_TYPE_PACKAGE) { if (of_compatible->type == ACPI_TYPE_PACKAGE) {

2
drivers/base/regmap/regmap-debugfs.c
View File

@ -48,7 +48,7 @@ static ssize_t regmap_name_read_file(struct file *file,
name = map->dev->driver->name; name = map->dev->driver->name;
ret = snprintf(buf, PAGE_SIZE, "%s\n", name); ret = snprintf(buf, PAGE_SIZE, "%s\n", name);
if (ret < 0) { if (ret >= PAGE_SIZE) {
kfree(buf); kfree(buf);
return ret; return ret;
} }

16
drivers/base/regmap/regmap.c
View File

@ -1643,17 +1643,19 @@ static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg,
} }
if (!map->cache_bypass && map->format.parse_val) { if (!map->cache_bypass && map->format.parse_val) {
unsigned int ival; unsigned int ival, offset;
int val_bytes = map->format.val_bytes; int val_bytes = map->format.val_bytes;
for (i = 0; i < val_len / val_bytes; i++) {
ival = map->format.parse_val(val + (i * val_bytes)); /* Cache the last written value for noinc writes */
ret = regcache_write(map, i = noinc ? val_len - val_bytes : 0;
reg + regmap_get_offset(map, i), for (; i < val_len; i += val_bytes) {
ival); ival = map->format.parse_val(val + i);
offset = noinc ? 0 : regmap_get_offset(map, i / val_bytes);
ret = regcache_write(map, reg + offset, ival);
if (ret) { if (ret) {
dev_err(map->dev, dev_err(map->dev,
"Error in caching of register: %x ret: %d\n", "Error in caching of register: %x ret: %d\n",
reg + regmap_get_offset(map, i), ret); reg + offset, ret);
return ret; return ret;
} }
} }

6
drivers/char/hw_random/geode-rng.c
View File

@ -58,7 +58,8 @@ struct amd_geode_priv {
static int geode_rng_data_read(struct hwrng *rng, u32 *data) static int geode_rng_data_read(struct hwrng *rng, u32 *data)
{ {
void __iomem *mem = (void __iomem *)rng->priv; struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv;
void __iomem *mem = priv->membase;
*data = readl(mem + GEODE_RNG_DATA_REG); *data = readl(mem + GEODE_RNG_DATA_REG);
@ -67,7 +68,8 @@ static int geode_rng_data_read(struct hwrng *rng, u32 *data)
static int geode_rng_data_present(struct hwrng *rng, int wait) static int geode_rng_data_present(struct hwrng *rng, int wait)
{ {
void __iomem *mem = (void __iomem *)rng->priv; struct amd_geode_priv *priv = (struct amd_geode_priv *)rng->priv;
void __iomem *mem = priv->membase;
int data, i; int data, i;
for (i = 0; i < 20; i++) { for (i = 0; i < 20; i++) {

29
drivers/clk/clk-asm9260.c
View File

@ -80,7 +80,7 @@ struct asm9260_mux_clock {
u8 mask; u8 mask;
u32 *table; u32 *table;
const char *name; const char *name;
const char **parent_names; const struct clk_parent_data *parent_data;
u8 num_parents; u8 num_parents;
unsigned long offset; unsigned long offset;
unsigned long flags; unsigned long flags;
@ -232,10 +232,10 @@ static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
HW_AHBCLKCTRL1, 16 }, HW_AHBCLKCTRL1, 16 },
}; };
static const char __initdata *main_mux_p[] = { NULL, NULL }; static struct clk_parent_data __initdata main_mux_p[] = { { .index = 0, }, { .name = "pll" } };
static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"}; static struct clk_parent_data __initdata i2s0_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s0m_div"} };
static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"}; static struct clk_parent_data __initdata i2s1_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "i2s1m_div"} };
static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"}; static struct clk_parent_data __initdata clkout_mux_p[] = { { .index = 0, }, { .name = "pll" }, { .name = "rtc"} };
static u32 three_mux_table[] = {0, 1, 3}; static u32 three_mux_table[] = {0, 1, 3};
static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
@ -255,9 +255,10 @@ static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
static void __init asm9260_acc_init(struct device_node *np) static void __init asm9260_acc_init(struct device_node *np)
{ {
struct clk_hw *hw; struct clk_hw *hw, *pll_hw;
struct clk_hw **hws; struct clk_hw **hws;
const char *ref_clk, *pll_clk = "pll"; const char *pll_clk = "pll";
struct clk_parent_data pll_parent_data = { .index = 0 };
u32 rate; u32 rate;
int n; int n;
@ -274,21 +275,15 @@ static void __init asm9260_acc_init(struct device_node *np)
/* register pll */ /* register pll */
rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
/* TODO: Convert to DT parent scheme */ pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data,
ref_clk = of_clk_get_parent_name(np, 0); 0, rate);
hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk, if (IS_ERR(pll_hw))
ref_clk, NULL, NULL, 0, rate, 0,
CLK_FIXED_RATE_PARENT_ACCURACY);
if (IS_ERR(hw))
panic("%pOFn: can't register REFCLK. Check DT!", np); panic("%pOFn: can't register REFCLK. Check DT!", np);
for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
mc->parent_names[0] = ref_clk; hw = clk_hw_register_mux_table_parent_data(NULL, mc->name, mc->parent_data,
mc->parent_names[1] = pll_clk;
hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
mc->num_parents, mc->flags, base + mc->offset, mc->num_parents, mc->flags, base + mc->offset,
0, mc->mask, 0, mc->table, &asm9260_clk_lock); 0, mc->mask, 0, mc->table, &asm9260_clk_lock);
} }

2
drivers/clk/clk-npcm7xx.c
View File

@ -647,7 +647,7 @@ static void __init npcm7xx_clk_init(struct device_node *clk_np)
return; return;
npcm7xx_init_fail: npcm7xx_init_fail:
kfree(npcm7xx_clk_data->hws); kfree(npcm7xx_clk_data);
npcm7xx_init_np_err: npcm7xx_init_np_err:
iounmap(clk_base); iounmap(clk_base);
npcm7xx_init_error: npcm7xx_init_error:

1
drivers/clk/clk-scmi.c
View File

@ -177,6 +177,7 @@ static int scmi_clocks_probe(struct scmi_device *sdev)
sclk->info = clk_ops->info_get(ph, idx); sclk->info = clk_ops->info_get(ph, idx);
if (!sclk->info) { if (!sclk->info) {
dev_dbg(dev, "invalid clock info for idx %d\n", idx); dev_dbg(dev, "invalid clock info for idx %d\n", idx);
devm_kfree(dev, sclk);
continue; continue;
} }

1
drivers/clk/imx/Kconfig
View File

@ -96,5 +96,6 @@ config CLK_IMX8QXP
depends on (ARCH_MXC && ARM64) || COMPILE_TEST depends on (ARCH_MXC && ARM64) || COMPILE_TEST
depends on IMX_SCU && HAVE_ARM_SMCCC depends on IMX_SCU && HAVE_ARM_SMCCC
select MXC_CLK_SCU select MXC_CLK_SCU
select MXC_CLK
help help
Build the driver for IMX8QXP SCU based clocks. Build the driver for IMX8QXP SCU based clocks.

17
drivers/clk/imx/clk-imx8mq.c
View File

@ -280,8 +280,7 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
void __iomem *base; void __iomem *base;
int err; int err;
clk_hw_data = kzalloc(struct_size(clk_hw_data, hws, clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws, IMX8MQ_CLK_END), GFP_KERNEL);
IMX8MQ_CLK_END), GFP_KERNEL);
if (WARN_ON(!clk_hw_data)) if (WARN_ON(!clk_hw_data))
return -ENOMEM; return -ENOMEM;
@ -298,10 +297,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4"); hws[IMX8MQ_CLK_EXT4] = imx_obtain_fixed_clk_hw(np, "clk_ext4");
np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop"); np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-anatop");
base = of_iomap(np, 0); base = devm_of_iomap(dev, np, 0, NULL);
of_node_put(np); of_node_put(np);
if (WARN_ON(!base)) if (WARN_ON(IS_ERR(base))) {
return -ENOMEM; err = PTR_ERR(base);
goto unregister_hws;
}
hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MQ_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels)); hws[IMX8MQ_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
@ -373,8 +374,10 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
np = dev->of_node; np = dev->of_node;
base = devm_platform_ioremap_resource(pdev, 0); base = devm_platform_ioremap_resource(pdev, 0);
if (WARN_ON(IS_ERR(base))) if (WARN_ON(IS_ERR(base))) {
return PTR_ERR(base); err = PTR_ERR(base);
goto unregister_hws;
}
/* CORE */ /* CORE */
hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000); hws[IMX8MQ_CLK_A53_DIV] = imx8m_clk_hw_composite_core("arm_a53_div", imx8mq_a53_sels, base + 0x8000);

15
drivers/clk/keystone/pll.c
View File

@ -281,12 +281,13 @@ static void __init of_pll_div_clk_init(struct device_node *node)
clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift, clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
mask, 0, NULL); mask, 0, NULL);
if (clk) { if (IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
} else {
pr_err("%s: error registering divider %s\n", __func__, clk_name); pr_err("%s: error registering divider %s\n", __func__, clk_name);
iounmap(reg); iounmap(reg);
return;
} }
of_clk_add_provider(node, of_clk_src_simple_get, clk);
} }
CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init); CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
@ -328,10 +329,12 @@ static void __init of_pll_mux_clk_init(struct device_node *node)
clk = clk_register_mux(NULL, clk_name, (const char **)&parents, clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
ARRAY_SIZE(parents) , 0, reg, shift, mask, ARRAY_SIZE(parents) , 0, reg, shift, mask,
0, NULL); 0, NULL);
if (clk) if (IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
else
pr_err("%s: error registering mux %s\n", __func__, clk_name); pr_err("%s: error registering mux %s\n", __func__, clk_name);
return;
}
of_clk_add_provider(node, of_clk_src_simple_get, clk);
} }
CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init); CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);

8
drivers/clk/mediatek/clk-mt2701.c
View File

@ -675,6 +675,8 @@ static int mtk_topckgen_init(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR); clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data); clk_data);
@ -742,6 +744,8 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
if (!infra_clk_data) { if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return;
for (i = 0; i < CLK_INFRA_NR; i++) for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
@ -768,6 +772,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
if (!infra_clk_data) { if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return -ENOMEM;
} else { } else {
for (i = 0; i < CLK_INFRA_NR; i++) { for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
@ -896,6 +902,8 @@ static int mtk_pericfg_init(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR); clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data); clk_data);

6
drivers/clk/mediatek/clk-mt6765.c
View File

@ -785,6 +785,8 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
} }
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
@ -820,6 +822,8 @@ static int clk_mt6765_top_probe(struct platform_device *pdev)
} }
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
clk_data); clk_data);
@ -860,6 +864,8 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev)
} }
clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
clk_data); clk_data);

4
drivers/clk/mediatek/clk-mt6779.c
View File

@ -1216,6 +1216,8 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node; struct device_node *node = pdev->dev.of_node;
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
@ -1236,6 +1238,8 @@ static int clk_mt6779_top_probe(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data); clk_data);

6
drivers/clk/mediatek/clk-mt6797.c
View File

@ -391,6 +391,8 @@ static int mtk_topckgen_init(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR); clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs), mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data); clk_data);
@ -563,6 +565,8 @@ static void mtk_infrasys_init_early(struct device_node *node)
if (!infra_clk_data) { if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return;
for (i = 0; i < CLK_INFRA_NR; i++) for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER); infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
@ -587,6 +591,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
if (!infra_clk_data) { if (!infra_clk_data) {
infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR); infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
if (!infra_clk_data)
return -ENOMEM;
} else { } else {
for (i = 0; i < CLK_INFRA_NR; i++) { for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER)) if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))

4
drivers/clk/mediatek/clk-mt7629-eth.c
View File

@ -83,6 +83,8 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev)
int r; int r;
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data);
@ -105,6 +107,8 @@ static int clk_mt7629_sgmiisys_init(struct platform_device *pdev)
int r; int r;
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK,
clk_data); clk_data);

6
drivers/clk/mediatek/clk-mt7629.c
View File

@ -580,6 +580,8 @@ static int mtk_topckgen_init(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data); clk_data);
@ -603,6 +605,8 @@ static int mtk_infrasys_init(struct platform_device *pdev)
struct clk_onecell_data *clk_data; struct clk_onecell_data *clk_data;
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data); clk_data);
@ -626,6 +630,8 @@ static int mtk_pericfg_init(struct platform_device *pdev)
return PTR_ERR(base); return PTR_ERR(base);
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
if (!clk_data)
return -ENOMEM;
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data); clk_data);

1
drivers/clk/qcom/Kconfig
View File

@ -110,6 +110,7 @@ config IPQ_APSS_6018
tristate "IPQ APSS Clock Controller" tristate "IPQ APSS Clock Controller"
select IPQ_APSS_PLL select IPQ_APSS_PLL
depends on QCOM_APCS_IPC || COMPILE_TEST depends on QCOM_APCS_IPC || COMPILE_TEST
depends on QCOM_SMEM
help help
Support for APSS clock controller on IPQ platforms. The Support for APSS clock controller on IPQ platforms. The
APSS clock controller manages the Mux and enable block that feeds the APSS clock controller manages the Mux and enable block that feeds the

14
drivers/clk/qcom/clk-rcg2.c
View File

@ -147,17 +147,11 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
static unsigned long static unsigned long
calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div) calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
{ {
if (hid_div) { if (hid_div)
rate *= 2; rate = mult_frac(rate, 2, hid_div + 1);
rate /= hid_div + 1;
}
if (mode) { if (mode)
u64 tmp = rate; rate = mult_frac(rate, m, n);
tmp *= m;
do_div(tmp, n);
rate = tmp;
}
return rate; return rate;
} }

98
drivers/clk/qcom/gcc-sm8150.c
View File

@ -241,7 +241,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_cpuss_ahb_clk_src", .name = "gcc_cpuss_ahb_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -264,7 +264,7 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_ptp_clk_src", .name = "gcc_emac_ptp_clk_src",
.parent_data = gcc_parents_5, .parent_data = gcc_parents_5,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -290,7 +290,7 @@ static struct clk_rcg2 gcc_emac_rgmii_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_emac_rgmii_clk_src", .name = "gcc_emac_rgmii_clk_src",
.parent_data = gcc_parents_5, .parent_data = gcc_parents_5,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_5),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -314,7 +314,7 @@ static struct clk_rcg2 gcc_gp1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp1_clk_src", .name = "gcc_gp1_clk_src",
.parent_data = gcc_parents_1, .parent_data = gcc_parents_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -329,7 +329,7 @@ static struct clk_rcg2 gcc_gp2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp2_clk_src", .name = "gcc_gp2_clk_src",
.parent_data = gcc_parents_1, .parent_data = gcc_parents_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -344,7 +344,7 @@ static struct clk_rcg2 gcc_gp3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_gp3_clk_src", .name = "gcc_gp3_clk_src",
.parent_data = gcc_parents_1, .parent_data = gcc_parents_1,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_1),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -365,7 +365,7 @@ static struct clk_rcg2 gcc_pcie_0_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_0_aux_clk_src", .name = "gcc_pcie_0_aux_clk_src",
.parent_data = gcc_parents_2, .parent_data = gcc_parents_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -380,7 +380,7 @@ static struct clk_rcg2 gcc_pcie_1_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_1_aux_clk_src", .name = "gcc_pcie_1_aux_clk_src",
.parent_data = gcc_parents_2, .parent_data = gcc_parents_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -401,7 +401,7 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pcie_phy_refgen_clk_src", .name = "gcc_pcie_phy_refgen_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -423,7 +423,7 @@ static struct clk_rcg2 gcc_pdm2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_pdm2_clk_src", .name = "gcc_pdm2_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -446,7 +446,7 @@ static struct clk_rcg2 gcc_qspi_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qspi_core_clk_src", .name = "gcc_qspi_core_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -480,7 +480,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s0_clk_src", .name = "gcc_qupv3_wrap0_s0_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -495,7 +495,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s1_clk_src", .name = "gcc_qupv3_wrap0_s1_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -510,7 +510,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s2_clk_src", .name = "gcc_qupv3_wrap0_s2_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -525,7 +525,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s3_clk_src", .name = "gcc_qupv3_wrap0_s3_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -540,7 +540,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s4_clk_src", .name = "gcc_qupv3_wrap0_s4_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -555,7 +555,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s5_clk_src", .name = "gcc_qupv3_wrap0_s5_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -570,7 +570,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s6_clk_src", .name = "gcc_qupv3_wrap0_s6_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -585,7 +585,7 @@ static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap0_s7_clk_src", .name = "gcc_qupv3_wrap0_s7_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -600,7 +600,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s0_clk_src", .name = "gcc_qupv3_wrap1_s0_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -615,7 +615,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s1_clk_src", .name = "gcc_qupv3_wrap1_s1_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -630,7 +630,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s2_clk_src", .name = "gcc_qupv3_wrap1_s2_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -645,7 +645,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s3_clk_src", .name = "gcc_qupv3_wrap1_s3_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -660,7 +660,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s4_clk_src", .name = "gcc_qupv3_wrap1_s4_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -675,7 +675,7 @@ static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap1_s5_clk_src", .name = "gcc_qupv3_wrap1_s5_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -690,7 +690,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s0_clk_src", .name = "gcc_qupv3_wrap2_s0_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -705,7 +705,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s1_clk_src", .name = "gcc_qupv3_wrap2_s1_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -720,7 +720,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s2_clk_src", .name = "gcc_qupv3_wrap2_s2_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -735,7 +735,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s3_clk_src", .name = "gcc_qupv3_wrap2_s3_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -750,7 +750,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s4_clk_src", .name = "gcc_qupv3_wrap2_s4_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -765,7 +765,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_qupv3_wrap2_s5_clk_src", .name = "gcc_qupv3_wrap2_s5_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -791,8 +791,8 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc2_apps_clk_src", .name = "gcc_sdcc2_apps_clk_src",
.parent_data = gcc_parents_6, .parent_data = gcc_parents_6,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_6),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_OPS_PARENT_ENABLE,
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
}; };
@ -816,7 +816,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_sdcc4_apps_clk_src", .name = "gcc_sdcc4_apps_clk_src",
.parent_data = gcc_parents_3, .parent_data = gcc_parents_3,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parents_3),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_floor_ops, .ops = &clk_rcg2_floor_ops,
}, },
@ -836,7 +836,7 @@ static struct clk_rcg2 gcc_tsif_ref_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_tsif_ref_clk_src", .name = "gcc_tsif_ref_clk_src",
.parent_data = gcc_parents_7, .parent_data = gcc_parents_7,
.num_parents = 5, .num_parents = ARRAY_SIZE(gcc_parents_7),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -860,7 +860,7 @@ static struct clk_rcg2 gcc_ufs_card_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_axi_clk_src", .name = "gcc_ufs_card_axi_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -883,7 +883,7 @@ static struct clk_rcg2 gcc_ufs_card_ice_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_ice_core_clk_src", .name = "gcc_ufs_card_ice_core_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -903,7 +903,7 @@ static struct clk_rcg2 gcc_ufs_card_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_phy_aux_clk_src", .name = "gcc_ufs_card_phy_aux_clk_src",
.parent_data = gcc_parents_4, .parent_data = gcc_parents_4,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -925,7 +925,7 @@ static struct clk_rcg2 gcc_ufs_card_unipro_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_card_unipro_core_clk_src", .name = "gcc_ufs_card_unipro_core_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -949,7 +949,7 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_axi_clk_src", .name = "gcc_ufs_phy_axi_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -964,7 +964,7 @@ static struct clk_rcg2 gcc_ufs_phy_ice_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_ice_core_clk_src", .name = "gcc_ufs_phy_ice_core_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -979,7 +979,7 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_phy_aux_clk_src", .name = "gcc_ufs_phy_phy_aux_clk_src",
.parent_data = gcc_parents_4, .parent_data = gcc_parents_4,
.num_parents = 2, .num_parents = ARRAY_SIZE(gcc_parents_4),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -994,7 +994,7 @@ static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_ufs_phy_unipro_core_clk_src", .name = "gcc_ufs_phy_unipro_core_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1018,7 +1018,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_master_clk_src", .name = "gcc_usb30_prim_master_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1040,7 +1040,7 @@ static struct clk_rcg2 gcc_usb30_prim_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_prim_mock_utmi_clk_src", .name = "gcc_usb30_prim_mock_utmi_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1055,7 +1055,7 @@ static struct clk_rcg2 gcc_usb30_sec_master_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_master_clk_src", .name = "gcc_usb30_sec_master_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1070,7 +1070,7 @@ static struct clk_rcg2 gcc_usb30_sec_mock_utmi_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb30_sec_mock_utmi_clk_src", .name = "gcc_usb30_sec_mock_utmi_clk_src",
.parent_data = gcc_parents_0, .parent_data = gcc_parents_0,
.num_parents = 4, .num_parents = ARRAY_SIZE(gcc_parents_0),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1085,7 +1085,7 @@ static struct clk_rcg2 gcc_usb3_prim_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_prim_phy_aux_clk_src", .name = "gcc_usb3_prim_phy_aux_clk_src",
.parent_data = gcc_parents_2, .parent_data = gcc_parents_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },
@ -1100,7 +1100,7 @@ static struct clk_rcg2 gcc_usb3_sec_phy_aux_clk_src = {
.clkr.hw.init = &(struct clk_init_data){ .clkr.hw.init = &(struct clk_init_data){
.name = "gcc_usb3_sec_phy_aux_clk_src", .name = "gcc_usb3_sec_phy_aux_clk_src",
.parent_data = gcc_parents_2, .parent_data = gcc_parents_2,
.num_parents = 3, .num_parents = ARRAY_SIZE(gcc_parents_2),
.flags = CLK_SET_RATE_PARENT, .flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_ops, .ops = &clk_rcg2_ops,
}, },

17
drivers/clk/qcom/mmcc-msm8998.c
View File

@ -1211,6 +1211,8 @@ static struct clk_rcg2 vfe1_clk_src = {
static struct clk_branch misc_ahb_clk = { static struct clk_branch misc_ahb_clk = {
.halt_reg = 0x328, .halt_reg = 0x328,
.hwcg_reg = 0x328,
.hwcg_bit = 1,
.clkr = { .clkr = {
.enable_reg = 0x328, .enable_reg = 0x328,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -1241,6 +1243,8 @@ static struct clk_branch video_core_clk = {
static struct clk_branch video_ahb_clk = { static struct clk_branch video_ahb_clk = {
.halt_reg = 0x1030, .halt_reg = 0x1030,
.hwcg_reg = 0x1030,
.hwcg_bit = 1,
.clkr = { .clkr = {
.enable_reg = 0x1030, .enable_reg = 0x1030,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -1315,6 +1319,8 @@ static struct clk_branch video_subcore1_clk = {
static struct clk_branch mdss_ahb_clk = { static struct clk_branch mdss_ahb_clk = {
.halt_reg = 0x2308, .halt_reg = 0x2308,
.hwcg_reg = 0x2308,
.hwcg_bit = 1,
.clkr = { .clkr = {
.enable_reg = 0x2308, .enable_reg = 0x2308,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2481,6 +2487,7 @@ static struct clk_branch fd_ahb_clk = {
static struct clk_branch mnoc_ahb_clk = { static struct clk_branch mnoc_ahb_clk = {
.halt_reg = 0x5024, .halt_reg = 0x5024,
.halt_check = BRANCH_HALT_SKIP,
.clkr = { .clkr = {
.enable_reg = 0x5024, .enable_reg = 0x5024,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2496,6 +2503,9 @@ static struct clk_branch mnoc_ahb_clk = {
static struct clk_branch bimc_smmu_ahb_clk = { static struct clk_branch bimc_smmu_ahb_clk = {
.halt_reg = 0xe004, .halt_reg = 0xe004,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe004,
.hwcg_bit = 1,
.clkr = { .clkr = {
.enable_reg = 0xe004, .enable_reg = 0xe004,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2511,6 +2521,9 @@ static struct clk_branch bimc_smmu_ahb_clk = {
static struct clk_branch bimc_smmu_axi_clk = { static struct clk_branch bimc_smmu_axi_clk = {
.halt_reg = 0xe008, .halt_reg = 0xe008,
.halt_check = BRANCH_HALT_SKIP,
.hwcg_reg = 0xe008,
.hwcg_bit = 1,
.clkr = { .clkr = {
.enable_reg = 0xe008, .enable_reg = 0xe008,
.enable_mask = BIT(0), .enable_mask = BIT(0),
@ -2649,11 +2662,13 @@ static struct gdsc camss_cpp_gdsc = {
static struct gdsc bimc_smmu_gdsc = { static struct gdsc bimc_smmu_gdsc = {
.gdscr = 0xe020, .gdscr = 0xe020,
.gds_hw_ctrl = 0xe024, .gds_hw_ctrl = 0xe024,
.cxcs = (unsigned int []){ 0xe008 },
.cxc_count = 1,
.pd = { .pd = {
.name = "bimc_smmu", .name = "bimc_smmu",
}, },
.pwrsts = PWRSTS_OFF_ON, .pwrsts = PWRSTS_OFF_ON,
.flags = HW_CTRL, .flags = VOTABLE,
}; };
static struct clk_regmap *mmcc_msm8998_clocks[] = { static struct clk_regmap *mmcc_msm8998_clocks[] = {

13
drivers/clk/ti/apll.c
View File

@ -139,6 +139,7 @@ static void __init omap_clk_register_apll(void *user,
struct clk_hw *hw = user; struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *ad = clk_hw->dpll_data; struct dpll_data *ad = clk_hw->dpll_data;
const char *name;
struct clk *clk; struct clk *clk;
const struct clk_init_data *init = clk_hw->hw.init; const struct clk_init_data *init = clk_hw->hw.init;
@ -166,7 +167,8 @@ static void __init omap_clk_register_apll(void *user,
ad->clk_bypass = __clk_get_hw(clk); ad->clk_bypass = __clk_get_hw(clk);
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init->parent_names); kfree(init->parent_names);
@ -198,7 +200,7 @@ static void __init of_dra7_apll_setup(struct device_node *node)
clk_hw->dpll_data = ad; clk_hw->dpll_data = ad;
clk_hw->hw.init = init; clk_hw->hw.init = init;
init->name = node->name; init->name = ti_dt_clk_name(node);
init->ops = &apll_ck_ops; init->ops = &apll_ck_ops;
init->num_parents = of_clk_get_parent_count(node); init->num_parents = of_clk_get_parent_count(node);
@ -347,6 +349,7 @@ static void __init of_omap2_apll_setup(struct device_node *node)
struct dpll_data *ad = NULL; struct dpll_data *ad = NULL;
struct clk_hw_omap *clk_hw = NULL; struct clk_hw_omap *clk_hw = NULL;
struct clk_init_data *init = NULL; struct clk_init_data *init = NULL;
const char *name;
struct clk *clk; struct clk *clk;
const char *parent_name; const char *parent_name;
u32 val; u32 val;
@ -362,7 +365,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
clk_hw->dpll_data = ad; clk_hw->dpll_data = ad;
clk_hw->hw.init = init; clk_hw->hw.init = init;
init->ops = &omap2_apll_ops; init->ops = &omap2_apll_ops;
init->name = node->name; name = ti_dt_clk_name(node);
init->name = name;
clk_hw->ops = &omap2_apll_hwops; clk_hw->ops = &omap2_apll_hwops;
init->num_parents = of_clk_get_parent_count(node); init->num_parents = of_clk_get_parent_count(node);
@ -403,7 +407,8 @@ static void __init of_omap2_apll_setup(struct device_node *node)
if (ret) if (ret)
goto cleanup; goto cleanup;
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);
kfree(init); kfree(init);

2
drivers/clk/ti/autoidle.c
View File

@ -205,7 +205,7 @@ int __init of_ti_clk_autoidle_setup(struct device_node *node)
return -ENOMEM; return -ENOMEM;
clk->shift = shift; clk->shift = shift;
clk->name = node->name; clk->name = ti_dt_clk_name(node);
ret = ti_clk_get_reg_addr(node, 0, &clk->reg); ret = ti_clk_get_reg_addr(node, 0, &clk->reg);
if (ret) { if (ret) {
kfree(clk); kfree(clk);

6
drivers/clk/ti/clk-dra7-atl.c
View File

@ -173,6 +173,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
struct dra7_atl_desc *clk_hw = NULL; struct dra7_atl_desc *clk_hw = NULL;
struct clk_init_data init = { NULL }; struct clk_init_data init = { NULL };
const char **parent_names = NULL; const char **parent_names = NULL;
const char *name;
struct clk *clk; struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
@ -183,7 +184,8 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
clk_hw->hw.init = &init; clk_hw->hw.init = &init;
clk_hw->divider = 1; clk_hw->divider = 1;
init.name = node->name; name = ti_dt_clk_name(node);
init.name = name;
init.ops = &atl_clk_ops; init.ops = &atl_clk_ops;
init.flags = CLK_IGNORE_UNUSED; init.flags = CLK_IGNORE_UNUSED;
init.num_parents = of_clk_get_parent_count(node); init.num_parents = of_clk_get_parent_count(node);
@ -203,7 +205,7 @@ static void __init of_dra7_atl_clock_setup(struct device_node *node)
init.parent_names = parent_names; init.parent_names = parent_names;
clk = ti_clk_register(NULL, &clk_hw->hw, node->name); clk = of_ti_clk_register(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);

52
drivers/clk/ti/clk.c
View File

@ -402,6 +402,24 @@ static const struct of_device_id simple_clk_match_table[] __initconst = {
{ } { }
}; };
/**
* ti_dt_clk_name - init clock name from first output name or node name
* @np: device node
*
* Use the first clock-output-name for the clock name if found. Fall back
* to legacy naming based on node name.
*/
const char *ti_dt_clk_name(struct device_node *np)
{
const char *name;
if (!of_property_read_string_index(np, "clock-output-names", 0,
&name))
return name;
return np->name;
}
/** /**
* ti_clk_add_aliases - setup clock aliases * ti_clk_add_aliases - setup clock aliases
* *
@ -418,7 +436,7 @@ void __init ti_clk_add_aliases(void)
clkspec.np = np; clkspec.np = np;
clk = of_clk_get_from_provider(&clkspec); clk = of_clk_get_from_provider(&clkspec);
ti_clk_add_alias(NULL, clk, np->name); ti_clk_add_alias(clk, ti_dt_clk_name(np));
} }
} }
@ -471,7 +489,6 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
/** /**
* ti_clk_add_alias - add a clock alias for a TI clock * ti_clk_add_alias - add a clock alias for a TI clock
* @dev: device alias for this clock
* @clk: clock handle to create alias for * @clk: clock handle to create alias for
* @con: connection ID for this clock * @con: connection ID for this clock
* *
@ -479,7 +496,7 @@ void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
* and assigns the data to it. Returns 0 if successful, negative error * and assigns the data to it. Returns 0 if successful, negative error
* value otherwise. * value otherwise.
*/ */
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con) int ti_clk_add_alias(struct clk *clk, const char *con)
{ {
struct clk_lookup *cl; struct clk_lookup *cl;
@ -493,8 +510,6 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
if (!cl) if (!cl)
return -ENOMEM; return -ENOMEM;
if (dev)
cl->dev_id = dev_name(dev);
cl->con_id = con; cl->con_id = con;
cl->clk = clk; cl->clk = clk;
@ -504,8 +519,8 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
} }
/** /**
* ti_clk_register - register a TI clock to the common clock framework * of_ti_clk_register - register a TI clock to the common clock framework
* @dev: device for this clock * @node: device node for this clock
* @hw: hardware clock handle * @hw: hardware clock handle
* @con: connection ID for this clock * @con: connection ID for this clock
* *
@ -513,17 +528,18 @@ int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con)
* alias for it. Returns a handle to the registered clock if successful, * alias for it. Returns a handle to the registered clock if successful,
* ERR_PTR value in failure. * ERR_PTR value in failure.
*/ */
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
const char *con) const char *con)
{ {
struct clk *clk; struct clk *clk;
int ret; int ret;
clk = clk_register(dev, hw); ret = of_clk_hw_register(node, hw);
if (IS_ERR(clk)) if (ret)
return clk; return ERR_PTR(ret);
ret = ti_clk_add_alias(dev, clk, con); clk = hw->clk;
ret = ti_clk_add_alias(clk, con);
if (ret) { if (ret) {
clk_unregister(clk); clk_unregister(clk);
return ERR_PTR(ret); return ERR_PTR(ret);
@ -533,8 +549,8 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
} }
/** /**
* ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework * of_ti_clk_register_omap_hw - register a clk_hw_omap to the clock framework
* @dev: device for this clock * @node: device node for this clock
* @hw: hardware clock handle * @hw: hardware clock handle
* @con: connection ID for this clock * @con: connection ID for this clock
* *
@ -543,13 +559,13 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
* Returns a handle to the registered clock if successful, ERR_PTR value * Returns a handle to the registered clock if successful, ERR_PTR value
* in failure. * in failure.
*/ */
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
const char *con) struct clk_hw *hw, const char *con)
{ {
struct clk *clk; struct clk *clk;
struct clk_hw_omap *oclk; struct clk_hw_omap *oclk;
clk = ti_clk_register(dev, hw, con); clk = of_ti_clk_register(node, hw, con);
if (IS_ERR(clk)) if (IS_ERR(clk))
return clk; return clk;

4
drivers/clk/ti/clkctrl.c
View File

@ -317,7 +317,7 @@ _ti_clkctrl_clk_register(struct omap_clkctrl_provider *provider,
init.ops = ops; init.ops = ops;
init.flags = 0; init.flags = 0;
clk = ti_clk_register(NULL, clk_hw, init.name); clk = of_ti_clk_register(node, clk_hw, init.name);
if (IS_ERR_OR_NULL(clk)) { if (IS_ERR_OR_NULL(clk)) {
ret = -EINVAL; ret = -EINVAL;
goto cleanup; goto cleanup;
@ -701,7 +701,7 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node)
init.ops = &omap4_clkctrl_clk_ops; init.ops = &omap4_clkctrl_clk_ops;
hw->hw.init = &init; hw->hw.init = &init;
clk = ti_clk_register_omap_hw(NULL, &hw->hw, init.name); clk = of_ti_clk_register_omap_hw(node, &hw->hw, init.name);
if (IS_ERR_OR_NULL(clk)) if (IS_ERR_OR_NULL(clk))
goto cleanup; goto cleanup;

11
drivers/clk/ti/clock.h
View File

@ -210,11 +210,12 @@ extern const struct omap_clkctrl_data dm816_clkctrl_data[];
typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *); typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw, struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
const char *con); const char *con);
struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw, struct clk *of_ti_clk_register_omap_hw(struct device_node *node,
const char *con); struct clk_hw *hw, const char *con);
int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con); const char *ti_dt_clk_name(struct device_node *np);
int ti_clk_add_alias(struct clk *clk, const char *con);
void ti_clk_add_aliases(void); void ti_clk_add_aliases(void);
void ti_clk_latch(struct clk_omap_reg *reg, s8 shift); void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);

2
drivers/clk/ti/clockdomain.c
View File

@ -131,7 +131,7 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
{ {
struct clk *clk; struct clk *clk;
struct clk_hw *clk_hw; struct clk_hw *clk_hw;
const char *clkdm_name = node->name; const char *clkdm_name = ti_dt_clk_name(node);
int i; int i;
unsigned int num_clks; unsigned int num_clks;

6
drivers/clk/ti/composite.c
View File

@ -125,6 +125,7 @@ static void __init _register_composite(void *user,
struct component_clk *comp; struct component_clk *comp;
int num_parents = 0; int num_parents = 0;
const char **parent_names = NULL; const char **parent_names = NULL;
const char *name;
int i; int i;
int ret; int ret;
@ -172,7 +173,8 @@ static void __init _register_composite(void *user,
goto cleanup; goto cleanup;
} }
clk = clk_register_composite(NULL, node->name, name = ti_dt_clk_name(node);
clk = clk_register_composite(NULL, name,
parent_names, num_parents, parent_names, num_parents,
_get_hw(cclk, CLK_COMPONENT_TYPE_MUX), _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
&ti_clk_mux_ops, &ti_clk_mux_ops,
@ -182,7 +184,7 @@ static void __init _register_composite(void *user,
&ti_composite_gate_ops, 0); &ti_composite_gate_ops, 0);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
ret = ti_clk_add_alias(NULL, clk, node->name); ret = ti_clk_add_alias(clk, name);
if (ret) { if (ret) {
clk_unregister(clk); clk_unregister(clk);
goto cleanup; goto cleanup;

12
drivers/clk/ti/divider.c
View File

@ -317,13 +317,14 @@ static struct clk *_register_divider(struct device_node *node,
u32 flags, u32 flags,
struct clk_omap_divider *div) struct clk_omap_divider *div)
{ {
struct clk *clk;
struct clk_init_data init; struct clk_init_data init;
const char *parent_name; const char *parent_name;
const char *name;
parent_name = of_clk_get_parent_name(node, 0); parent_name = of_clk_get_parent_name(node, 0);
init.name = node->name; name = ti_dt_clk_name(node);
init.name = name;
init.ops = &ti_clk_divider_ops; init.ops = &ti_clk_divider_ops;
init.flags = flags; init.flags = flags;
init.parent_names = (parent_name ? &parent_name : NULL); init.parent_names = (parent_name ? &parent_name : NULL);
@ -332,12 +333,7 @@ static struct clk *_register_divider(struct device_node *node,
div->hw.init = &init; div->hw.init = &init;
/* register the clock */ /* register the clock */
clk = ti_clk_register(NULL, &div->hw, node->name); return of_ti_clk_register(node, &div->hw, name);
if (IS_ERR(clk))
kfree(div);
return clk;
} }
int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div, int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,

10
drivers/clk/ti/dpll.c
View File

@ -164,6 +164,7 @@ static void __init _register_dpll(void *user,
struct clk_hw *hw = user; struct clk_hw *hw = user;
struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw);
struct dpll_data *dd = clk_hw->dpll_data; struct dpll_data *dd = clk_hw->dpll_data;
const char *name;
struct clk *clk; struct clk *clk;
const struct clk_init_data *init = hw->init; const struct clk_init_data *init = hw->init;
@ -193,7 +194,8 @@ static void __init _register_dpll(void *user,
dd->clk_bypass = __clk_get_hw(clk); dd->clk_bypass = __clk_get_hw(clk);
/* register the clock */ /* register the clock */
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, node->name); name = ti_dt_clk_name(node);
clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);
@ -227,7 +229,7 @@ static void _register_dpll_x2(struct device_node *node,
struct clk *clk; struct clk *clk;
struct clk_init_data init = { NULL }; struct clk_init_data init = { NULL };
struct clk_hw_omap *clk_hw; struct clk_hw_omap *clk_hw;
const char *name = node->name; const char *name = ti_dt_clk_name(node);
const char *parent_name; const char *parent_name;
parent_name = of_clk_get_parent_name(node, 0); parent_name = of_clk_get_parent_name(node, 0);
@ -265,7 +267,7 @@ static void _register_dpll_x2(struct device_node *node,
#endif #endif
/* register the clock */ /* register the clock */
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk)) if (IS_ERR(clk))
kfree(clk_hw); kfree(clk_hw);
@ -302,7 +304,7 @@ static void __init of_ti_dpll_setup(struct device_node *node,
clk_hw->ops = &clkhwops_omap3_dpll; clk_hw->ops = &clkhwops_omap3_dpll;
clk_hw->hw.init = init; clk_hw->hw.init = init;
init->name = node->name; init->name = ti_dt_clk_name(node);
init->ops = ops; init->ops = ops;
init->num_parents = of_clk_get_parent_count(node); init->num_parents = of_clk_get_parent_count(node);

11
drivers/clk/ti/fapll.c
View File

@ -19,6 +19,8 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/clk/ti.h> #include <linux/clk/ti.h>
#include "clock.h"
/* FAPLL Control Register PLL_CTRL */ /* FAPLL Control Register PLL_CTRL */
#define FAPLL_MAIN_MULT_N_SHIFT 16 #define FAPLL_MAIN_MULT_N_SHIFT 16
#define FAPLL_MAIN_DIV_P_SHIFT 8 #define FAPLL_MAIN_DIV_P_SHIFT 8
@ -542,6 +544,7 @@ static void __init ti_fapll_setup(struct device_node *node)
struct clk_init_data *init = NULL; struct clk_init_data *init = NULL;
const char *parent_name[2]; const char *parent_name[2];
struct clk *pll_clk; struct clk *pll_clk;
const char *name;
int i; int i;
fd = kzalloc(sizeof(*fd), GFP_KERNEL); fd = kzalloc(sizeof(*fd), GFP_KERNEL);
@ -559,7 +562,8 @@ static void __init ti_fapll_setup(struct device_node *node)
goto free; goto free;
init->ops = &ti_fapll_ops; init->ops = &ti_fapll_ops;
init->name = node->name; name = ti_dt_clk_name(node);
init->name = name;
init->num_parents = of_clk_get_parent_count(node); init->num_parents = of_clk_get_parent_count(node);
if (init->num_parents != 2) { if (init->num_parents != 2) {
@ -591,7 +595,7 @@ static void __init ti_fapll_setup(struct device_node *node)
if (fapll_is_ddr_pll(fd->base)) if (fapll_is_ddr_pll(fd->base))
fd->bypass_bit_inverted = true; fd->bypass_bit_inverted = true;
fd->name = node->name; fd->name = name;
fd->hw.init = init; fd->hw.init = init;
/* Register the parent PLL */ /* Register the parent PLL */
@ -638,8 +642,7 @@ static void __init ti_fapll_setup(struct device_node *node)
freq = NULL; freq = NULL;
} }
synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance, synth_clk = ti_fapll_synth_setup(fd, freq, div, output_instance,
output_name, node->name, output_name, name, pll_clk);
pll_clk);
if (IS_ERR(synth_clk)) if (IS_ERR(synth_clk))
continue; continue;

4
drivers/clk/ti/fixed-factor.c
View File

@ -36,7 +36,7 @@
static void __init of_ti_fixed_factor_clk_setup(struct device_node *node) static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
{ {
struct clk *clk; struct clk *clk;
const char *clk_name = node->name; const char *clk_name = ti_dt_clk_name(node);
const char *parent_name; const char *parent_name;
u32 div, mult; u32 div, mult;
u32 flags = 0; u32 flags = 0;
@ -62,7 +62,7 @@ static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
if (!IS_ERR(clk)) { if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk); of_clk_add_provider(node, of_clk_src_simple_get, clk);
of_ti_clk_autoidle_setup(node); of_ti_clk_autoidle_setup(node);
ti_clk_add_alias(NULL, clk, clk_name); ti_clk_add_alias(clk, clk_name);
} }
} }
CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock", CLK_OF_DECLARE(ti_fixed_factor_clk, "ti,fixed-factor-clock",

8
drivers/clk/ti/gate.c
View File

@ -93,7 +93,7 @@ static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *hw)
return ret; return ret;
} }
static struct clk *_register_gate(struct device *dev, const char *name, static struct clk *_register_gate(struct device_node *node, const char *name,
const char *parent_name, unsigned long flags, const char *parent_name, unsigned long flags,
struct clk_omap_reg *reg, u8 bit_idx, struct clk_omap_reg *reg, u8 bit_idx,
u8 clk_gate_flags, const struct clk_ops *ops, u8 clk_gate_flags, const struct clk_ops *ops,
@ -123,7 +123,7 @@ static struct clk *_register_gate(struct device *dev, const char *name,
init.flags = flags; init.flags = flags;
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk)) if (IS_ERR(clk))
kfree(clk_hw); kfree(clk_hw);
@ -138,6 +138,7 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
struct clk *clk; struct clk *clk;
const char *parent_name; const char *parent_name;
struct clk_omap_reg reg; struct clk_omap_reg reg;
const char *name;
u8 enable_bit = 0; u8 enable_bit = 0;
u32 val; u32 val;
u32 flags = 0; u32 flags = 0;
@ -164,7 +165,8 @@ static void __init _of_ti_gate_clk_setup(struct device_node *node,
if (of_property_read_bool(node, "ti,set-bit-to-disable")) if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_gate_flags |= INVERT_ENABLE; clk_gate_flags |= INVERT_ENABLE;
clk = _register_gate(NULL, node->name, parent_name, flags, &reg, name = ti_dt_clk_name(node);
clk = _register_gate(node, name, parent_name, flags, &reg,
enable_bit, clk_gate_flags, ops, hw_ops); enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk)) if (!IS_ERR(clk))

9
drivers/clk/ti/interface.c
View File

@ -32,7 +32,8 @@ static const struct clk_ops ti_interface_clk_ops = {
.is_enabled = &omap2_dflt_clk_is_enabled, .is_enabled = &omap2_dflt_clk_is_enabled,
}; };
static struct clk *_register_interface(struct device *dev, const char *name, static struct clk *_register_interface(struct device_node *node,
const char *name,
const char *parent_name, const char *parent_name,
struct clk_omap_reg *reg, u8 bit_idx, struct clk_omap_reg *reg, u8 bit_idx,
const struct clk_hw_omap_ops *ops) const struct clk_hw_omap_ops *ops)
@ -57,7 +58,7 @@ static struct clk *_register_interface(struct device *dev, const char *name,
init.num_parents = 1; init.num_parents = 1;
init.parent_names = &parent_name; init.parent_names = &parent_name;
clk = ti_clk_register_omap_hw(NULL, &clk_hw->hw, name); clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
if (IS_ERR(clk)) if (IS_ERR(clk))
kfree(clk_hw); kfree(clk_hw);
@ -72,6 +73,7 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
const char *parent_name; const char *parent_name;
struct clk_omap_reg reg; struct clk_omap_reg reg;
u8 enable_bit = 0; u8 enable_bit = 0;
const char *name;
u32 val; u32 val;
if (ti_clk_get_reg_addr(node, 0, &reg)) if (ti_clk_get_reg_addr(node, 0, &reg))
@ -86,7 +88,8 @@ static void __init _of_ti_interface_clk_setup(struct device_node *node,
return; return;
} }
clk = _register_interface(NULL, node->name, parent_name, &reg, name = ti_dt_clk_name(node);
clk = _register_interface(node, name, parent_name, &reg,
enable_bit, ops); enable_bit, ops);
if (!IS_ERR(clk)) if (!IS_ERR(clk))

8
drivers/clk/ti/mux.c
View File

@ -126,7 +126,7 @@ const struct clk_ops ti_clk_mux_ops = {
.restore_context = clk_mux_restore_context, .restore_context = clk_mux_restore_context,
}; };
static struct clk *_register_mux(struct device *dev, const char *name, static struct clk *_register_mux(struct device_node *node, const char *name,
const char * const *parent_names, const char * const *parent_names,
u8 num_parents, unsigned long flags, u8 num_parents, unsigned long flags,
struct clk_omap_reg *reg, u8 shift, u32 mask, struct clk_omap_reg *reg, u8 shift, u32 mask,
@ -156,7 +156,7 @@ static struct clk *_register_mux(struct device *dev, const char *name,
mux->table = table; mux->table = table;
mux->hw.init = &init; mux->hw.init = &init;
clk = ti_clk_register(dev, &mux->hw, name); clk = of_ti_clk_register(node, &mux->hw, name);
if (IS_ERR(clk)) if (IS_ERR(clk))
kfree(mux); kfree(mux);
@ -176,6 +176,7 @@ static void of_mux_clk_setup(struct device_node *node)
struct clk_omap_reg reg; struct clk_omap_reg reg;
unsigned int num_parents; unsigned int num_parents;
const char **parent_names; const char **parent_names;
const char *name;
u8 clk_mux_flags = 0; u8 clk_mux_flags = 0;
u32 mask = 0; u32 mask = 0;
u32 shift = 0; u32 shift = 0;
@ -213,7 +214,8 @@ static void of_mux_clk_setup(struct device_node *node)
mask = (1 << fls(mask)) - 1; mask = (1 << fls(mask)) - 1;
clk = _register_mux(NULL, node->name, parent_names, num_parents, name = ti_dt_clk_name(node);
clk = _register_mux(node, name, parent_names, num_parents,
flags, &reg, shift, mask, latch, clk_mux_flags, flags, &reg, shift, mask, latch, clk_mux_flags,
NULL); NULL);

3
drivers/crypto/caam/caamalg.c
View File

@ -566,7 +566,8 @@ static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key,
if (keylen != CHACHA_KEY_SIZE + saltlen) if (keylen != CHACHA_KEY_SIZE + saltlen)
return -EINVAL; return -EINVAL;
ctx->cdata.key_virt = key; memcpy(ctx->key, key, keylen);
ctx->cdata.key_virt = ctx->key;
ctx->cdata.keylen = keylen - saltlen; ctx->cdata.keylen = keylen - saltlen;
return chachapoly_set_sh_desc(aead); return chachapoly_set_sh_desc(aead);

3
drivers/crypto/caam/caamalg_qi2.c
View File

@ -636,7 +636,8 @@ static int chachapoly_setkey(struct crypto_aead *aead, const u8 *key,
if (keylen != CHACHA_KEY_SIZE + saltlen) if (keylen != CHACHA_KEY_SIZE + saltlen)
return -EINVAL; return -EINVAL;
ctx->cdata.key_virt = key; memcpy(ctx->key, key, keylen);
ctx->cdata.key_virt = ctx->key;
ctx->cdata.keylen = keylen - saltlen; ctx->cdata.keylen = keylen - saltlen;
return chachapoly_set_sh_desc(aead); return chachapoly_set_sh_desc(aead);

2
drivers/crypto/hisilicon/hpre/hpre_main.c
View File

@ -637,7 +637,7 @@ static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { for (i = 0; i < HPRE_CLUSTERS_NUM; i++) {
ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
if (ret < 0) if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
return -EINVAL; return -EINVAL;
tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);

34
drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.c
View File

@ -17,15 +17,33 @@ static struct adf_hw_device_class c3xxx_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET & u32 straps = self->straps;
ADF_C3XXX_ACCELERATORS_MASK; u32 fuses = self->fuses;
u32 accel;
accel = ~(fuses | straps) >> ADF_C3XXX_ACCELERATORS_REG_OFFSET;
accel &= ADF_C3XXX_ACCELERATORS_MASK;
return accel;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) & ADF_C3XXX_ACCELENGINES_MASK; u32 straps = self->straps;
u32 fuses = self->fuses;
unsigned long disabled;
u32 ae_disable;
int accel;
/* If an accel is disabled, then disable the corresponding two AEs */
disabled = ~get_accel_mask(self) & ADF_C3XXX_ACCELERATORS_MASK;
ae_disable = BIT(1) | BIT(0);
for_each_set_bit(accel, &disabled, ADF_C3XXX_MAX_ACCELERATORS)
straps |= ae_disable << (accel << 1);
return ~(fuses | straps) & ADF_C3XXX_ACCELENGINES_MASK;
} }
static u32 get_num_accels(struct adf_hw_device_data *self) static u32 get_num_accels(struct adf_hw_device_data *self)
@ -109,11 +127,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
{ {
struct adf_hw_device_data *hw_device = accel_dev->hw_device; struct adf_hw_device_data *hw_device = accel_dev->hw_device;
struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR]; struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C3XXX_PMISC_BAR];
unsigned long accel_mask = hw_device->accel_mask;
unsigned long ae_mask = hw_device->ae_mask;
void __iomem *csr = misc_bar->virt_addr; void __iomem *csr = misc_bar->virt_addr;
unsigned int val, i; unsigned int val, i;
/* Enable Accel Engine error detection & correction */ /* Enable Accel Engine error detection & correction */
for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i)); val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
val |= ADF_C3XXX_ENABLE_AE_ECC_ERR; val |= ADF_C3XXX_ENABLE_AE_ECC_ERR;
ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val); ADF_CSR_WR(csr, ADF_C3XXX_AE_CTX_ENABLES(i), val);
@ -123,7 +143,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
} }
/* Enable shared memory error detection & correction */ /* Enable shared memory error detection & correction */
for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { for_each_set_bit(i, &accel_mask, ADF_C3XXX_MAX_ACCELERATORS) {
val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i)); val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
val |= ADF_C3XXX_ERRSSMSH_EN; val |= ADF_C3XXX_ERRSSMSH_EN;
ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val); ADF_CSR_WR(csr, ADF_C3XXX_UERRSSMSH(i), val);

1
drivers/crypto/qat/qat_c3xxx/adf_c3xxx_hw_data.h
View File

@ -18,6 +18,7 @@
#define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) #define ADF_C3XXX_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
#define ADF_C3XXX_SMIA0_MASK 0xFFFF #define ADF_C3XXX_SMIA0_MASK 0xFFFF
#define ADF_C3XXX_SMIA1_MASK 0x1 #define ADF_C3XXX_SMIA1_MASK 0x1
#define ADF_C3XXX_SOFTSTRAP_CSR_OFFSET 0x2EC
/* Error detection and correction */ /* Error detection and correction */
#define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) #define ADF_C3XXX_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
#define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) #define ADF_C3XXX_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)

6
drivers/crypto/qat/qat_c3xxx/adf_drv.c
View File

@ -126,10 +126,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid); pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET, pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET,
&hw_data->fuses); &hw_data->fuses);
pci_read_config_dword(pdev, ADF_C3XXX_SOFTSTRAP_CSR_OFFSET,
&hw_data->straps);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* If the device has no acceleration engines then ignore it. */ /* If the device has no acceleration engines then ignore it. */
if (!hw_data->accel_mask || !hw_data->ae_mask || if (!hw_data->accel_mask || !hw_data->ae_mask ||

4
drivers/crypto/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
View File

@ -11,12 +11,12 @@ static struct adf_hw_device_class c3xxxiov_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return ADF_C3XXXIOV_ACCELERATORS_MASK; return ADF_C3XXXIOV_ACCELERATORS_MASK;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return ADF_C3XXXIOV_ACCELENGINES_MASK; return ADF_C3XXXIOV_ACCELENGINES_MASK;
} }

4
drivers/crypto/qat/qat_c3xxxvf/adf_drv.c
View File

@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
adf_init_hw_data_c3xxxiov(accel_dev->hw_device); adf_init_hw_data_c3xxxiov(accel_dev->hw_device);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* Create dev top level debugfs entry */ /* Create dev top level debugfs entry */

34
drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.c
View File

@ -22,15 +22,33 @@ static struct adf_hw_device_class c62x_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) >> ADF_C62X_ACCELERATORS_REG_OFFSET & u32 straps = self->straps;
ADF_C62X_ACCELERATORS_MASK; u32 fuses = self->fuses;
u32 accel;
accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
accel &= ADF_C62X_ACCELERATORS_MASK;
return accel;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) & ADF_C62X_ACCELENGINES_MASK; u32 straps = self->straps;
u32 fuses = self->fuses;
unsigned long disabled;
u32 ae_disable;
int accel;
/* If an accel is disabled, then disable the corresponding two AEs */
disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK;
ae_disable = BIT(1) | BIT(0);
for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS)
straps |= ae_disable << (accel << 1);
return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
} }
static u32 get_num_accels(struct adf_hw_device_data *self) static u32 get_num_accels(struct adf_hw_device_data *self)
@ -119,11 +137,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
{ {
struct adf_hw_device_data *hw_device = accel_dev->hw_device; struct adf_hw_device_data *hw_device = accel_dev->hw_device;
struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR]; struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_C62X_PMISC_BAR];
unsigned long accel_mask = hw_device->accel_mask;
unsigned long ae_mask = hw_device->ae_mask;
void __iomem *csr = misc_bar->virt_addr; void __iomem *csr = misc_bar->virt_addr;
unsigned int val, i; unsigned int val, i;
/* Enable Accel Engine error detection & correction */ /* Enable Accel Engine error detection & correction */
for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i)); val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
val |= ADF_C62X_ENABLE_AE_ECC_ERR; val |= ADF_C62X_ENABLE_AE_ECC_ERR;
ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val); ADF_CSR_WR(csr, ADF_C62X_AE_CTX_ENABLES(i), val);
@ -133,7 +153,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
} }
/* Enable shared memory error detection & correction */ /* Enable shared memory error detection & correction */
for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { for_each_set_bit(i, &accel_mask, ADF_C62X_MAX_ACCELERATORS) {
val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i)); val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
val |= ADF_C62X_ERRSSMSH_EN; val |= ADF_C62X_ERRSSMSH_EN;
ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val); ADF_CSR_WR(csr, ADF_C62X_UERRSSMSH(i), val);

1
drivers/crypto/qat/qat_c62x/adf_c62x_hw_data.h
View File

@ -19,6 +19,7 @@
#define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30) #define ADF_C62X_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
#define ADF_C62X_SMIA0_MASK 0xFFFF #define ADF_C62X_SMIA0_MASK 0xFFFF
#define ADF_C62X_SMIA1_MASK 0x1 #define ADF_C62X_SMIA1_MASK 0x1
#define ADF_C62X_SOFTSTRAP_CSR_OFFSET 0x2EC
/* Error detection and correction */ /* Error detection and correction */
#define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818) #define ADF_C62X_AE_CTX_ENABLES(i) (i * 0x1000 + 0x20818)
#define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960) #define ADF_C62X_AE_MISC_CONTROL(i) (i * 0x1000 + 0x20960)

6
drivers/crypto/qat/qat_c62x/adf_drv.c
View File

@ -126,10 +126,12 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid); pci_read_config_byte(pdev, PCI_REVISION_ID, &accel_pci_dev->revid);
pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET, pci_read_config_dword(pdev, ADF_DEVICE_FUSECTL_OFFSET,
&hw_data->fuses); &hw_data->fuses);
pci_read_config_dword(pdev, ADF_C62X_SOFTSTRAP_CSR_OFFSET,
&hw_data->straps);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* If the device has no acceleration engines then ignore it. */ /* If the device has no acceleration engines then ignore it. */
if (!hw_data->accel_mask || !hw_data->ae_mask || if (!hw_data->accel_mask || !hw_data->ae_mask ||

4
drivers/crypto/qat/qat_c62xvf/adf_c62xvf_hw_data.c
View File

@ -11,12 +11,12 @@ static struct adf_hw_device_class c62xiov_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return ADF_C62XIOV_ACCELERATORS_MASK; return ADF_C62XIOV_ACCELERATORS_MASK;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return ADF_C62XIOV_ACCELENGINES_MASK; return ADF_C62XIOV_ACCELENGINES_MASK;
} }

4
drivers/crypto/qat/qat_c62xvf/adf_drv.c
View File

@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
adf_init_hw_data_c62xiov(accel_dev->hw_device); adf_init_hw_data_c62xiov(accel_dev->hw_device);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* Create dev top level debugfs entry */ /* Create dev top level debugfs entry */

7
drivers/crypto/qat/qat_common/adf_accel_devices.h
View File

@ -23,7 +23,7 @@
#define ADF_PCI_MAX_BARS 3 #define ADF_PCI_MAX_BARS 3
#define ADF_DEVICE_NAME_LENGTH 32 #define ADF_DEVICE_NAME_LENGTH 32
#define ADF_ETR_MAX_RINGS_PER_BANK 16 #define ADF_ETR_MAX_RINGS_PER_BANK 16
#define ADF_MAX_MSIX_VECTOR_NAME 16 #define ADF_MAX_MSIX_VECTOR_NAME 48
#define ADF_DEVICE_NAME_PREFIX "qat_" #define ADF_DEVICE_NAME_PREFIX "qat_"
enum adf_accel_capabilities { enum adf_accel_capabilities {
@ -104,8 +104,8 @@ struct adf_etr_ring_data;
struct adf_hw_device_data { struct adf_hw_device_data {
struct adf_hw_device_class *dev_class; struct adf_hw_device_class *dev_class;
u32 (*get_accel_mask)(u32 fuse); u32 (*get_accel_mask)(struct adf_hw_device_data *self);
u32 (*get_ae_mask)(u32 fuse); u32 (*get_ae_mask)(struct adf_hw_device_data *self);
u32 (*get_sram_bar_id)(struct adf_hw_device_data *self); u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
u32 (*get_misc_bar_id)(struct adf_hw_device_data *self); u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
u32 (*get_etr_bar_id)(struct adf_hw_device_data *self); u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
@ -131,6 +131,7 @@ struct adf_hw_device_data {
const char *fw_name; const char *fw_name;
const char *fw_mmp_name; const char *fw_mmp_name;
u32 fuses; u32 fuses;
u32 straps;
u32 accel_capabilities_mask; u32 accel_capabilities_mask;
u32 instance_id; u32 instance_id;
u16 accel_mask; u16 accel_mask;

4
drivers/crypto/qat/qat_common/adf_transport_debug.c
View File

@ -89,7 +89,7 @@ DEFINE_SEQ_ATTRIBUTE(adf_ring_debug);
int adf_ring_debugfs_add(struct adf_etr_ring_data *ring, const char *name) int adf_ring_debugfs_add(struct adf_etr_ring_data *ring, const char *name)
{ {
struct adf_etr_ring_debug_entry *ring_debug; struct adf_etr_ring_debug_entry *ring_debug;
char entry_name[8]; char entry_name[16];
ring_debug = kzalloc(sizeof(*ring_debug), GFP_KERNEL); ring_debug = kzalloc(sizeof(*ring_debug), GFP_KERNEL);
if (!ring_debug) if (!ring_debug)
@ -184,7 +184,7 @@ int adf_bank_debugfs_add(struct adf_etr_bank_data *bank)
{ {
struct adf_accel_dev *accel_dev = bank->accel_dev; struct adf_accel_dev *accel_dev = bank->accel_dev;
struct dentry *parent = accel_dev->transport->debug; struct dentry *parent = accel_dev->transport->debug;
char name[8]; char name[16];
snprintf(name, sizeof(name), "bank_%02d", bank->bank_number); snprintf(name, sizeof(name), "bank_%02d", bank->bank_number);
bank->bank_debug_dir = debugfs_create_dir(name, parent); bank->bank_debug_dir = debugfs_create_dir(name, parent);

27
drivers/crypto/qat/qat_common/qat_hal.c
View File

@ -346,11 +346,12 @@ static void qat_hal_put_wakeup_event(struct icp_qat_fw_loader_handle *handle,
static int qat_hal_check_ae_alive(struct icp_qat_fw_loader_handle *handle) static int qat_hal_check_ae_alive(struct icp_qat_fw_loader_handle *handle)
{ {
unsigned long ae_mask = handle->hal_handle->ae_mask;
unsigned int base_cnt, cur_cnt; unsigned int base_cnt, cur_cnt;
unsigned char ae; unsigned char ae;
int times = MAX_RETRY_TIMES; int times = MAX_RETRY_TIMES;
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT); base_cnt = qat_hal_rd_ae_csr(handle, ae, PROFILE_COUNT);
base_cnt &= 0xffff; base_cnt &= 0xffff;
@ -384,6 +385,7 @@ int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle) static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
{ {
unsigned long ae_mask = handle->hal_handle->ae_mask;
unsigned int misc_ctl; unsigned int misc_ctl;
unsigned char ae; unsigned char ae;
@ -393,7 +395,7 @@ static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl & SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl &
(~MC_TIMESTAMP_ENABLE)); (~MC_TIMESTAMP_ENABLE));
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0); qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_LOW, 0);
qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0); qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);
} }
@ -438,6 +440,7 @@ static int qat_hal_init_esram(struct icp_qat_fw_loader_handle *handle)
#define SHRAM_INIT_CYCLES 2060 #define SHRAM_INIT_CYCLES 2060
int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle) int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
{ {
unsigned long ae_mask = handle->hal_handle->ae_mask;
unsigned int ae_reset_csr; unsigned int ae_reset_csr;
unsigned char ae; unsigned char ae;
unsigned int clk_csr; unsigned int clk_csr;
@ -464,7 +467,7 @@ int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
goto out_err; goto out_err;
/* Set undefined power-up/reset states to reasonable default values */ /* Set undefined power-up/reset states to reasonable default values */
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES, qat_hal_wr_ae_csr(handle, ae, CTX_ENABLES,
INIT_CTX_ENABLE_VALUE); INIT_CTX_ENABLE_VALUE);
qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX, qat_hal_wr_indr_csr(handle, ae, ICP_QAT_UCLO_AE_ALL_CTX,
@ -570,10 +573,11 @@ static void qat_hal_enable_ctx(struct icp_qat_fw_loader_handle *handle,
static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle) static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle)
{ {
unsigned long ae_mask = handle->hal_handle->ae_mask;
unsigned char ae; unsigned char ae;
unsigned short reg; unsigned short reg;
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) { for (reg = 0; reg < ICP_QAT_UCLO_MAX_GPR_REG; reg++) {
qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS, qat_hal_init_rd_xfer(handle, ae, 0, ICP_SR_RD_ABS,
reg, 0); reg, 0);
@ -585,6 +589,7 @@ static void qat_hal_clear_xfer(struct icp_qat_fw_loader_handle *handle)
static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle) static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
{ {
unsigned long ae_mask = handle->hal_handle->ae_mask;
unsigned char ae; unsigned char ae;
unsigned int ctx_mask = ICP_QAT_UCLO_AE_ALL_CTX; unsigned int ctx_mask = ICP_QAT_UCLO_AE_ALL_CTX;
int times = MAX_RETRY_TIMES; int times = MAX_RETRY_TIMES;
@ -592,7 +597,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
unsigned int savctx = 0; unsigned int savctx = 0;
int ret = 0; int ret = 0;
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL); csr_val = qat_hal_rd_ae_csr(handle, ae, AE_MISC_CONTROL);
csr_val &= ~(1 << MMC_SHARE_CS_BITPOS); csr_val &= ~(1 << MMC_SHARE_CS_BITPOS);
qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val); qat_hal_wr_ae_csr(handle, ae, AE_MISC_CONTROL, csr_val);
@ -613,7 +618,7 @@ static int qat_hal_clear_gpr(struct icp_qat_fw_loader_handle *handle)
qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0); qat_hal_wr_ae_csr(handle, ae, CTX_SIG_EVENTS_ACTIVE, 0);
qat_hal_enable_ctx(handle, ae, ctx_mask); qat_hal_enable_ctx(handle, ae, ctx_mask);
} }
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
/* wait for AE to finish */ /* wait for AE to finish */
do { do {
ret = qat_hal_wait_cycles(handle, ae, 20, 1); ret = qat_hal_wait_cycles(handle, ae, 20, 1);
@ -654,6 +659,8 @@ int qat_hal_init(struct adf_accel_dev *accel_dev)
struct adf_hw_device_data *hw_data = accel_dev->hw_device; struct adf_hw_device_data *hw_data = accel_dev->hw_device;
struct adf_bar *misc_bar = struct adf_bar *misc_bar =
&pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)]; &pci_info->pci_bars[hw_data->get_misc_bar_id(hw_data)];
unsigned long ae_mask = hw_data->ae_mask;
unsigned int csr_val = 0;
struct adf_bar *sram_bar; struct adf_bar *sram_bar;
handle = kzalloc(sizeof(*handle), GFP_KERNEL); handle = kzalloc(sizeof(*handle), GFP_KERNEL);
@ -689,9 +696,7 @@ int qat_hal_init(struct adf_accel_dev *accel_dev)
/* create AE objects */ /* create AE objects */
handle->hal_handle->upc_mask = 0x1ffff; handle->hal_handle->upc_mask = 0x1ffff;
handle->hal_handle->max_ustore = 0x4000; handle->hal_handle->max_ustore = 0x4000;
for (ae = 0; ae < ICP_QAT_UCLO_MAX_AE; ae++) { for_each_set_bit(ae, &ae_mask, ICP_QAT_UCLO_MAX_AE) {
if (!(hw_data->ae_mask & (1 << ae)))
continue;
handle->hal_handle->aes[ae].free_addr = 0; handle->hal_handle->aes[ae].free_addr = 0;
handle->hal_handle->aes[ae].free_size = handle->hal_handle->aes[ae].free_size =
handle->hal_handle->max_ustore; handle->hal_handle->max_ustore;
@ -714,9 +719,7 @@ int qat_hal_init(struct adf_accel_dev *accel_dev)
} }
/* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */ /* Set SIGNATURE_ENABLE[0] to 0x1 in order to enable ALU_OUT csr */
for (ae = 0; ae < handle->hal_handle->ae_max_num; ae++) { for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
unsigned int csr_val = 0;
csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE); csr_val = qat_hal_rd_ae_csr(handle, ae, SIGNATURE_ENABLE);
csr_val |= 0x1; csr_val |= 0x1;
qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val); qat_hal_wr_ae_csr(handle, ae, SIGNATURE_ENABLE, csr_val);

20
drivers/crypto/qat/qat_dh895xcc/adf_dh895xcc_hw_data.c
View File

@ -24,15 +24,19 @@ static struct adf_hw_device_class dh895xcc_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET & u32 fuses = self->fuses;
ADF_DH895XCC_ACCELERATORS_MASK;
return ~fuses >> ADF_DH895XCC_ACCELERATORS_REG_OFFSET &
ADF_DH895XCC_ACCELERATORS_MASK;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return (~fuse) & ADF_DH895XCC_ACCELENGINES_MASK; u32 fuses = self->fuses;
return ~fuses & ADF_DH895XCC_ACCELENGINES_MASK;
} }
static u32 get_num_accels(struct adf_hw_device_data *self) static u32 get_num_accels(struct adf_hw_device_data *self)
@ -131,11 +135,13 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
{ {
struct adf_hw_device_data *hw_device = accel_dev->hw_device; struct adf_hw_device_data *hw_device = accel_dev->hw_device;
struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR]; struct adf_bar *misc_bar = &GET_BARS(accel_dev)[ADF_DH895XCC_PMISC_BAR];
unsigned long accel_mask = hw_device->accel_mask;
unsigned long ae_mask = hw_device->ae_mask;
void __iomem *csr = misc_bar->virt_addr; void __iomem *csr = misc_bar->virt_addr;
unsigned int val, i; unsigned int val, i;
/* Enable Accel Engine error detection & correction */ /* Enable Accel Engine error detection & correction */
for (i = 0; i < hw_device->get_num_aes(hw_device); i++) { for_each_set_bit(i, &ae_mask, GET_MAX_ACCELENGINES(accel_dev)) {
val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i)); val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR; val |= ADF_DH895XCC_ENABLE_AE_ECC_ERR;
ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val);
@ -145,7 +151,7 @@ static void adf_enable_error_correction(struct adf_accel_dev *accel_dev)
} }
/* Enable shared memory error detection & correction */ /* Enable shared memory error detection & correction */
for (i = 0; i < hw_device->get_num_accels(hw_device); i++) { for_each_set_bit(i, &accel_mask, ADF_DH895XCC_MAX_ACCELERATORS) {
val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i)); val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
val |= ADF_DH895XCC_ERRSSMSH_EN; val |= ADF_DH895XCC_ERRSSMSH_EN;
ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val);

4
drivers/crypto/qat/qat_dh895xcc/adf_drv.c
View File

@ -128,8 +128,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
&hw_data->fuses); &hw_data->fuses);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* If the device has no acceleration engines then ignore it. */ /* If the device has no acceleration engines then ignore it. */
if (!hw_data->accel_mask || !hw_data->ae_mask || if (!hw_data->accel_mask || !hw_data->ae_mask ||

4
drivers/crypto/qat/qat_dh895xccvf/adf_dh895xccvf_hw_data.c
View File

@ -11,12 +11,12 @@ static struct adf_hw_device_class dh895xcciov_class = {
.instances = 0 .instances = 0
}; };
static u32 get_accel_mask(u32 fuse) static u32 get_accel_mask(struct adf_hw_device_data *self)
{ {
return ADF_DH895XCCIOV_ACCELERATORS_MASK; return ADF_DH895XCCIOV_ACCELERATORS_MASK;
} }
static u32 get_ae_mask(u32 fuse) static u32 get_ae_mask(struct adf_hw_device_data *self)
{ {
return ADF_DH895XCCIOV_ACCELENGINES_MASK; return ADF_DH895XCCIOV_ACCELENGINES_MASK;
} }

4
drivers/crypto/qat/qat_dh895xccvf/adf_drv.c
View File

@ -119,8 +119,8 @@ static int adf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
adf_init_hw_data_dh895xcciov(accel_dev->hw_device); adf_init_hw_data_dh895xcciov(accel_dev->hw_device);
/* Get Accelerators and Accelerators Engines masks */ /* Get Accelerators and Accelerators Engines masks */
hw_data->accel_mask = hw_data->get_accel_mask(hw_data->fuses); hw_data->accel_mask = hw_data->get_accel_mask(hw_data);
hw_data->ae_mask = hw_data->get_ae_mask(hw_data->fuses); hw_data->ae_mask = hw_data->get_ae_mask(hw_data);
accel_pci_dev->sku = hw_data->get_sku(hw_data); accel_pci_dev->sku = hw_data->get_sku(hw_data);
/* Create dev top level debugfs entry */ /* Create dev top level debugfs entry */

15
drivers/devfreq/event/rockchip-dfi.c
View File

@ -194,14 +194,15 @@ static int rockchip_dfi_probe(struct platform_device *pdev)
return PTR_ERR(data->clk); return PTR_ERR(data->clk);
} }
/* try to find the optional reference to the pmu syscon */
node = of_parse_phandle(np, "rockchip,pmu", 0); node = of_parse_phandle(np, "rockchip,pmu", 0);
if (node) { if (!node)
data->regmap_pmu = syscon_node_to_regmap(node); return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
of_node_put(node);
if (IS_ERR(data->regmap_pmu)) data->regmap_pmu = syscon_node_to_regmap(node);
return PTR_ERR(data->regmap_pmu); of_node_put(node);
} if (IS_ERR(data->regmap_pmu))
return PTR_ERR(data->regmap_pmu);
data->dev = dev; data->dev = dev;
desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);

1
drivers/dma/pxa_dma.c
View File

@ -723,7 +723,6 @@ static void pxad_free_desc(struct virt_dma_desc *vd)
dma_addr_t dma; dma_addr_t dma;
struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd); struct pxad_desc_sw *sw_desc = to_pxad_sw_desc(vd);
BUG_ON(sw_desc->nb_desc == 0);
for (i = sw_desc->nb_desc - 1; i >= 0; i--) { for (i = sw_desc->nb_desc - 1; i >= 0; i--) {
if (i > 0) if (i > 0)
dma = sw_desc->hw_desc[i - 1]->ddadr; dma = sw_desc->hw_desc[i - 1]->ddadr;

4
drivers/dma/ti/edma.c
View File

@ -2459,7 +2459,7 @@ static int edma_probe(struct platform_device *pdev)
if (irq < 0 && node) if (irq < 0 && node)
irq = irq_of_parse_and_map(node, 0); irq = irq_of_parse_and_map(node, 0);
if (irq >= 0) { if (irq > 0) {
irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint", irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
dev_name(dev)); dev_name(dev));
ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name, ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
@ -2475,7 +2475,7 @@ static int edma_probe(struct platform_device *pdev)
if (irq < 0 && node) if (irq < 0 && node)
irq = irq_of_parse_and_map(node, 2); irq = irq_of_parse_and_map(node, 2);
if (irq >= 0) { if (irq > 0) {
irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint", irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
dev_name(dev)); dev_name(dev));
ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name, ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,

46
drivers/firmware/ti_sci.c
View File

@ -190,19 +190,6 @@ static int ti_sci_debugfs_create(struct platform_device *pdev,
return 0; return 0;
} }
/**
* ti_sci_debugfs_destroy() - clean up log debug file
* @pdev: platform device pointer
* @info: Pointer to SCI entity information
*/
static void ti_sci_debugfs_destroy(struct platform_device *pdev,
struct ti_sci_info *info)
{
if (IS_ERR(info->debug_region))
return;
debugfs_remove(info->d);
}
#else /* CONFIG_DEBUG_FS */ #else /* CONFIG_DEBUG_FS */
static inline int ti_sci_debugfs_create(struct platform_device *dev, static inline int ti_sci_debugfs_create(struct platform_device *dev,
struct ti_sci_info *info) struct ti_sci_info *info)
@ -3510,43 +3497,12 @@ static int ti_sci_probe(struct platform_device *pdev)
return ret; return ret;
} }
static int ti_sci_remove(struct platform_device *pdev)
{
struct ti_sci_info *info;
struct device *dev = &pdev->dev;
int ret = 0;
of_platform_depopulate(dev);
info = platform_get_drvdata(pdev);
if (info->nb.notifier_call)
unregister_restart_handler(&info->nb);
mutex_lock(&ti_sci_list_mutex);
if (info->users)
ret = -EBUSY;
else
list_del(&info->node);
mutex_unlock(&ti_sci_list_mutex);
if (!ret) {
ti_sci_debugfs_destroy(pdev, info);
/* Safe to free channels since no more users */
mbox_free_channel(info->chan_tx);
mbox_free_channel(info->chan_rx);
}
return ret;
}
static struct platform_driver ti_sci_driver = { static struct platform_driver ti_sci_driver = {
.probe = ti_sci_probe, .probe = ti_sci_probe,
.remove = ti_sci_remove,
.driver = { .driver = {
.name = "ti-sci", .name = "ti-sci",
.of_match_table = of_match_ptr(ti_sci_of_match), .of_match_table = of_match_ptr(ti_sci_of_match),
.suppress_bind_attrs = true,
}, },
}; };
module_platform_driver(ti_sci_driver); module_platform_driver(ti_sci_driver);

25
drivers/gpu/drm/bridge/tc358768.c
View File

@ -217,6 +217,10 @@ static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
u32 tmp, orig; u32 tmp, orig;
tc358768_read(priv, reg, &orig); tc358768_read(priv, reg, &orig);
if (priv->error)
return;
tmp = orig & ~mask; tmp = orig & ~mask;
tmp |= val & mask; tmp |= val & mask;
if (tmp != orig) if (tmp != orig)
@ -633,6 +637,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
{ {
struct tc358768_priv *priv = bridge_to_tc358768(bridge); struct tc358768_priv *priv = bridge_to_tc358768(bridge);
struct mipi_dsi_device *dsi_dev = priv->output.dev; struct mipi_dsi_device *dsi_dev = priv->output.dev;
unsigned long mode_flags = dsi_dev->mode_flags;
u32 val, val2, lptxcnt, hact, data_type; u32 val, val2, lptxcnt, hact, data_type;
s32 raw_val; s32 raw_val;
const struct drm_display_mode *mode; const struct drm_display_mode *mode;
@ -640,6 +645,11 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
u32 dsiclk, dsibclk; u32 dsiclk, dsibclk;
int ret, i; int ret, i;
if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");
mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
}
tc358768_hw_enable(priv); tc358768_hw_enable(priv);
ret = tc358768_sw_reset(priv); ret = tc358768_sw_reset(priv);
@ -775,8 +785,8 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
val |= BIT(i + 1); val |= BIT(i + 1);
tc358768_write(priv, TC358768_HSTXVREGEN, val); tc358768_write(priv, TC358768_HSTXVREGEN, val);
if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) tc358768_write(priv, TC358768_TXOPTIONCNTRL,
tc358768_write(priv, TC358768_TXOPTIONCNTRL, 0x1); (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
/* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4); val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
@ -812,11 +822,12 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
tc358768_write(priv, TC358768_DSI_HACT, hact); tc358768_write(priv, TC358768_DSI_HACT, hact);
/* VSYNC polarity */ /* VSYNC polarity */
if (!(mode->flags & DRM_MODE_FLAG_NVSYNC)) tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), BIT(5)); (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
/* HSYNC polarity */ /* HSYNC polarity */
if (mode->flags & DRM_MODE_FLAG_PHSYNC) tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), BIT(0)); (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
/* Start DSI Tx */ /* Start DSI Tx */
tc358768_write(priv, TC358768_DSI_START, 0x1); tc358768_write(priv, TC358768_DSI_START, 0x1);
@ -832,7 +843,7 @@ static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
val |= TC358768_DSI_CONTROL_TXMD; val |= TC358768_DSI_CONTROL_TXMD;
if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
val |= TC358768_DSI_CONTROL_HSCKMD; val |= TC358768_DSI_CONTROL_HSCKMD;
if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET) if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET)

3
drivers/gpu/drm/drm_syncobj.c
View File

@ -983,7 +983,8 @@ static signed long drm_syncobj_array_wait_timeout(struct drm_syncobj **syncobjs,
fence = drm_syncobj_fence_get(syncobjs[i]); fence = drm_syncobj_fence_get(syncobjs[i]);
if (!fence || dma_fence_chain_find_seqno(&fence, points[i])) { if (!fence || dma_fence_chain_find_seqno(&fence, points[i])) {
dma_fence_put(fence); dma_fence_put(fence);
if (flags & DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT) { if (flags & (DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT |
DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE)) {
continue; continue;
} else { } else {
timeout = -EINVAL; timeout = -EINVAL;

3
drivers/gpu/drm/mediatek/mtk_drm_crtc.c
View File

@ -320,6 +320,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
unsigned int local_layer; unsigned int local_layer;
plane_state = to_mtk_plane_state(plane->state); plane_state = to_mtk_plane_state(plane->state);
/* should not enable layer before crtc enabled */
plane_state->pending.enable = false;
comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer); comp = mtk_drm_ddp_comp_for_plane(crtc, plane, &local_layer);
if (comp) if (comp)
mtk_ddp_comp_layer_config(comp, local_layer, mtk_ddp_comp_layer_config(comp, local_layer,

7
drivers/gpu/drm/radeon/evergreen.c
View File

@ -4819,14 +4819,15 @@ int evergreen_irq_process(struct radeon_device *rdev)
break; break;
case 44: /* hdmi */ case 44: /* hdmi */
afmt_idx = src_data; afmt_idx = src_data;
if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG))
DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
if (afmt_idx > 5) { if (afmt_idx > 5) {
DRM_ERROR("Unhandled interrupt: %d %d\n", DRM_ERROR("Unhandled interrupt: %d %d\n",
src_id, src_data); src_id, src_data);
break; break;
} }
if (!(afmt_status[afmt_idx] & AFMT_AZ_FORMAT_WTRIG))
DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG; afmt_status[afmt_idx] &= ~AFMT_AZ_FORMAT_WTRIG;
queue_hdmi = true; queue_hdmi = true;
DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1); DRM_DEBUG("IH: HDMI%d\n", afmt_idx + 1);

15
drivers/gpu/drm/rockchip/cdn-dp-core.c
View File

@ -1145,6 +1145,7 @@ static int cdn_dp_probe(struct platform_device *pdev)
struct cdn_dp_device *dp; struct cdn_dp_device *dp;
struct extcon_dev *extcon; struct extcon_dev *extcon;
struct phy *phy; struct phy *phy;
int ret;
int i; int i;
dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL); dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
@ -1185,9 +1186,19 @@ static int cdn_dp_probe(struct platform_device *pdev)
mutex_init(&dp->lock); mutex_init(&dp->lock);
dev_set_drvdata(dev, dp); dev_set_drvdata(dev, dp);
cdn_dp_audio_codec_init(dp, dev); ret = cdn_dp_audio_codec_init(dp, dev);
if (ret)
return ret;
return component_add(dev, &cdn_dp_component_ops); ret = component_add(dev, &cdn_dp_component_ops);
if (ret)
goto err_audio_deinit;
return 0;
err_audio_deinit:
platform_device_unregister(dp->audio_pdev);
return ret;
} }
static int cdn_dp_remove(struct platform_device *pdev) static int cdn_dp_remove(struct platform_device *pdev)

2
drivers/gpu/drm/rockchip/rockchip_drm_gem.c
View File

@ -38,7 +38,7 @@ static int rockchip_gem_iommu_map(struct rockchip_gem_object *rk_obj)
ret = iommu_map_sgtable(private->domain, rk_obj->dma_addr, rk_obj->sgt, ret = iommu_map_sgtable(private->domain, rk_obj->dma_addr, rk_obj->sgt,
prot); prot);
if (ret < rk_obj->base.size) { if (ret < (ssize_t)rk_obj->base.size) {
DRM_ERROR("failed to map buffer: size=%zd request_size=%zd\n", DRM_ERROR("failed to map buffer: size=%zd request_size=%zd\n",
ret, rk_obj->base.size); ret, rk_obj->base.size);
ret = -ENOMEM; ret = -ENOMEM;

8
drivers/gpu/drm/rockchip/rockchip_drm_vop.c
View File

@ -1533,7 +1533,8 @@ static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
if (WARN_ON(!crtc->state)) if (WARN_ON(!crtc->state))
return NULL; return NULL;
rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL); rockchip_state = kmemdup(to_rockchip_crtc_state(crtc->state),
sizeof(*rockchip_state), GFP_KERNEL);
if (!rockchip_state) if (!rockchip_state)
return NULL; return NULL;
@ -1558,7 +1559,10 @@ static void vop_crtc_reset(struct drm_crtc *crtc)
if (crtc->state) if (crtc->state)
vop_crtc_destroy_state(crtc, crtc->state); vop_crtc_destroy_state(crtc, crtc->state);
__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base); if (crtc_state)
__drm_atomic_helper_crtc_reset(crtc, &crtc_state->base);
else
__drm_atomic_helper_crtc_reset(crtc, NULL);
} }
#ifdef CONFIG_DRM_ANALOGIX_DP #ifdef CONFIG_DRM_ANALOGIX_DP

9
drivers/hid/hid-cp2112.c
View File

@ -1157,8 +1157,6 @@ static unsigned int cp2112_gpio_irq_startup(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cp2112_device *dev = gpiochip_get_data(gc); struct cp2112_device *dev = gpiochip_get_data(gc);
INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback);
if (!dev->gpio_poll) { if (!dev->gpio_poll) {
dev->gpio_poll = true; dev->gpio_poll = true;
schedule_delayed_work(&dev->gpio_poll_worker, 0); schedule_delayed_work(&dev->gpio_poll_worker, 0);
@ -1173,7 +1171,10 @@ static void cp2112_gpio_irq_shutdown(struct irq_data *d)
struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct cp2112_device *dev = gpiochip_get_data(gc); struct cp2112_device *dev = gpiochip_get_data(gc);
cancel_delayed_work_sync(&dev->gpio_poll_worker); if (!dev->irq_mask) {
dev->gpio_poll = false;
cancel_delayed_work_sync(&dev->gpio_poll_worker);
}
} }
static int cp2112_gpio_irq_type(struct irq_data *d, unsigned int type) static int cp2112_gpio_irq_type(struct irq_data *d, unsigned int type)
@ -1354,6 +1355,8 @@ static int cp2112_probe(struct hid_device *hdev, const struct hid_device_id *id)
girq->handler = handle_simple_irq; girq->handler = handle_simple_irq;
girq->threaded = true; girq->threaded = true;
INIT_DELAYED_WORK(&dev->gpio_poll_worker, cp2112_gpio_poll_callback);
ret = gpiochip_add_data(&dev->gc, dev); ret = gpiochip_add_data(&dev->gc, dev);
if (ret < 0) { if (ret < 0) {
hid_err(hdev, "error registering gpio chip\n"); hid_err(hdev, "error registering gpio chip\n");

76
drivers/hid/hid-logitech-hidpp.c
View File

@ -31,11 +31,6 @@ MODULE_LICENSE("GPL");
MODULE_AUTHOR("Benjamin Tissoires <benjamin.tissoires@gmail.com>"); MODULE_AUTHOR("Benjamin Tissoires <benjamin.tissoires@gmail.com>");
MODULE_AUTHOR("Nestor Lopez Casado <nlopezcasad@logitech.com>"); MODULE_AUTHOR("Nestor Lopez Casado <nlopezcasad@logitech.com>");
static bool disable_raw_mode;
module_param(disable_raw_mode, bool, 0644);
MODULE_PARM_DESC(disable_raw_mode,
"Disable Raw mode reporting for touchpads and keep firmware gestures.");
static bool disable_tap_to_click; static bool disable_tap_to_click;
module_param(disable_tap_to_click, bool, 0644); module_param(disable_tap_to_click, bool, 0644);
MODULE_PARM_DESC(disable_tap_to_click, MODULE_PARM_DESC(disable_tap_to_click,
@ -66,7 +61,7 @@ MODULE_PARM_DESC(disable_tap_to_click,
/* bits 2..20 are reserved for classes */ /* bits 2..20 are reserved for classes */
/* #define HIDPP_QUIRK_CONNECT_EVENTS BIT(21) disabled */ /* #define HIDPP_QUIRK_CONNECT_EVENTS BIT(21) disabled */
#define HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS BIT(22) #define HIDPP_QUIRK_WTP_PHYSICAL_BUTTONS BIT(22)
#define HIDPP_QUIRK_NO_HIDINPUT BIT(23) #define HIDPP_QUIRK_DELAYED_INIT BIT(23)
#define HIDPP_QUIRK_FORCE_OUTPUT_REPORTS BIT(24) #define HIDPP_QUIRK_FORCE_OUTPUT_REPORTS BIT(24)
#define HIDPP_QUIRK_UNIFYING BIT(25) #define HIDPP_QUIRK_UNIFYING BIT(25)
#define HIDPP_QUIRK_HI_RES_SCROLL_1P0 BIT(26) #define HIDPP_QUIRK_HI_RES_SCROLL_1P0 BIT(26)
@ -85,8 +80,6 @@ MODULE_PARM_DESC(disable_tap_to_click,
HIDPP_QUIRK_HI_RES_SCROLL_X2120 | \ HIDPP_QUIRK_HI_RES_SCROLL_X2120 | \
HIDPP_QUIRK_HI_RES_SCROLL_X2121) HIDPP_QUIRK_HI_RES_SCROLL_X2121)
#define HIDPP_QUIRK_DELAYED_INIT HIDPP_QUIRK_NO_HIDINPUT
#define HIDPP_CAPABILITY_HIDPP10_BATTERY BIT(0) #define HIDPP_CAPABILITY_HIDPP10_BATTERY BIT(0)
#define HIDPP_CAPABILITY_HIDPP20_BATTERY BIT(1) #define HIDPP_CAPABILITY_HIDPP20_BATTERY BIT(1)
#define HIDPP_CAPABILITY_BATTERY_MILEAGE BIT(2) #define HIDPP_CAPABILITY_BATTERY_MILEAGE BIT(2)
@ -1495,15 +1488,14 @@ static int hidpp_battery_get_property(struct power_supply *psy,
/* -------------------------------------------------------------------------- */ /* -------------------------------------------------------------------------- */
#define HIDPP_PAGE_WIRELESS_DEVICE_STATUS 0x1d4b #define HIDPP_PAGE_WIRELESS_DEVICE_STATUS 0x1d4b
static int hidpp_set_wireless_feature_index(struct hidpp_device *hidpp) static int hidpp_get_wireless_feature_index(struct hidpp_device *hidpp, u8 *feature_index)
{ {
u8 feature_type; u8 feature_type;
int ret; int ret;
ret = hidpp_root_get_feature(hidpp, ret = hidpp_root_get_feature(hidpp,
HIDPP_PAGE_WIRELESS_DEVICE_STATUS, HIDPP_PAGE_WIRELESS_DEVICE_STATUS,
&hidpp->wireless_feature_index, feature_index, &feature_type);
&feature_type);
return ret; return ret;
} }
@ -3673,6 +3665,13 @@ static void hidpp_connect_event(struct hidpp_device *hidpp)
} }
} }
if (hidpp->protocol_major >= 2) {
u8 feature_index;
if (!hidpp_get_wireless_feature_index(hidpp, &feature_index))
hidpp->wireless_feature_index = feature_index;
}
if (hidpp->name == hdev->name && hidpp->protocol_major >= 2) { if (hidpp->name == hdev->name && hidpp->protocol_major >= 2) {
name = hidpp_get_device_name(hidpp); name = hidpp_get_device_name(hidpp);
if (name) { if (name) {
@ -3707,7 +3706,7 @@ static void hidpp_connect_event(struct hidpp_device *hidpp)
if (hidpp->quirks & HIDPP_QUIRK_HI_RES_SCROLL) if (hidpp->quirks & HIDPP_QUIRK_HI_RES_SCROLL)
hi_res_scroll_enable(hidpp); hi_res_scroll_enable(hidpp);
if (!(hidpp->quirks & HIDPP_QUIRK_NO_HIDINPUT) || hidpp->delayed_input) if (!(hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT) || hidpp->delayed_input)
/* if the input nodes are already created, we can stop now */ /* if the input nodes are already created, we can stop now */
return; return;
@ -3810,7 +3809,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
bool connected; bool connected;
unsigned int connect_mask = HID_CONNECT_DEFAULT; unsigned int connect_mask = HID_CONNECT_DEFAULT;
struct hidpp_ff_private_data data; struct hidpp_ff_private_data data;
bool will_restart = false;
/* report_fixup needs drvdata to be set before we call hid_parse */ /* report_fixup needs drvdata to be set before we call hid_parse */
hidpp = devm_kzalloc(&hdev->dev, sizeof(*hidpp), GFP_KERNEL); hidpp = devm_kzalloc(&hdev->dev, sizeof(*hidpp), GFP_KERNEL);
@ -3851,11 +3849,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
hidpp_application_equals(hdev, HID_GD_KEYBOARD)) hidpp_application_equals(hdev, HID_GD_KEYBOARD))
hidpp->quirks |= HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS; hidpp->quirks |= HIDPP_QUIRK_HIDPP_CONSUMER_VENDOR_KEYS;
if (disable_raw_mode) {
hidpp->quirks &= ~HIDPP_QUIRK_CLASS_WTP;
hidpp->quirks &= ~HIDPP_QUIRK_NO_HIDINPUT;
}
if (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP) { if (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP) {
ret = wtp_allocate(hdev, id); ret = wtp_allocate(hdev, id);
if (ret) if (ret)
@ -3866,10 +3859,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
return ret; return ret;
} }
if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT ||
hidpp->quirks & HIDPP_QUIRK_UNIFYING)
will_restart = true;
INIT_WORK(&hidpp->work, delayed_work_cb); INIT_WORK(&hidpp->work, delayed_work_cb);
mutex_init(&hidpp->send_mutex); mutex_init(&hidpp->send_mutex);
init_waitqueue_head(&hidpp->wait); init_waitqueue_head(&hidpp->wait);
@ -3881,10 +3870,12 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
hdev->name); hdev->name);
/* /*
* Plain USB connections need to actually call start and open * First call hid_hw_start(hdev, 0) to allow IO without connecting any
* on the transport driver to allow incoming data. * hid subdrivers (hid-input, hidraw). This allows retrieving the dev's
* name and serial number and store these in hdev->name and hdev->uniq,
* before the hid-input and hidraw drivers expose these to userspace.
*/ */
ret = hid_hw_start(hdev, will_restart ? 0 : connect_mask); ret = hid_hw_start(hdev, 0);
if (ret) { if (ret) {
hid_err(hdev, "hw start failed\n"); hid_err(hdev, "hw start failed\n");
goto hid_hw_start_fail; goto hid_hw_start_fail;
@ -3917,15 +3908,6 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
hidpp_overwrite_name(hdev); hidpp_overwrite_name(hdev);
} }
if (connected && hidpp->protocol_major >= 2) {
ret = hidpp_set_wireless_feature_index(hidpp);
if (ret == -ENOENT)
hidpp->wireless_feature_index = 0;
else if (ret)
goto hid_hw_init_fail;
ret = 0;
}
if (connected && (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP)) { if (connected && (hidpp->quirks & HIDPP_QUIRK_CLASS_WTP)) {
ret = wtp_get_config(hidpp); ret = wtp_get_config(hidpp);
if (ret) if (ret)
@ -3939,21 +3921,14 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
schedule_work(&hidpp->work); schedule_work(&hidpp->work);
flush_work(&hidpp->work); flush_work(&hidpp->work);
if (will_restart) { if (hidpp->quirks & HIDPP_QUIRK_DELAYED_INIT)
/* Reset the HID node state */ connect_mask &= ~HID_CONNECT_HIDINPUT;
hid_device_io_stop(hdev);
hid_hw_close(hdev);
hid_hw_stop(hdev);
if (hidpp->quirks & HIDPP_QUIRK_NO_HIDINPUT) /* Now export the actual inputs and hidraw nodes to the world */
connect_mask &= ~HID_CONNECT_HIDINPUT; ret = hid_connect(hdev, connect_mask);
if (ret) {
/* Now export the actual inputs and hidraw nodes to the world */ hid_err(hdev, "%s:hid_connect returned error %d\n", __func__, ret);
ret = hid_hw_start(hdev, connect_mask); goto hid_hw_init_fail;
if (ret) {
hid_err(hdev, "%s:hid_hw_start returned error\n", __func__);
goto hid_hw_start_fail;
}
} }
if (hidpp->quirks & HIDPP_QUIRK_CLASS_G920) { if (hidpp->quirks & HIDPP_QUIRK_CLASS_G920) {
@ -3964,6 +3939,11 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
ret); ret);
} }
/*
* This relies on logi_dj_ll_close() being a no-op so that DJ connection
* events will still be received.
*/
hid_hw_close(hdev);
return ret; return ret;
hid_hw_init_fail: hid_hw_init_fail:

101
drivers/hwmon/axi-fan-control.c
View File

@ -8,6 +8,7 @@
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/fpga/adi-axi-common.h> #include <linux/fpga/adi-axi-common.h>
#include <linux/hwmon.h> #include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/kernel.h> #include <linux/kernel.h>
@ -23,6 +24,14 @@
#define ADI_REG_PWM_PERIOD 0x00c0 #define ADI_REG_PWM_PERIOD 0x00c0
#define ADI_REG_TACH_MEASUR 0x00c4 #define ADI_REG_TACH_MEASUR 0x00c4
#define ADI_REG_TEMPERATURE 0x00c8 #define ADI_REG_TEMPERATURE 0x00c8
#define ADI_REG_TEMP_00_H 0x0100
#define ADI_REG_TEMP_25_L 0x0104
#define ADI_REG_TEMP_25_H 0x0108
#define ADI_REG_TEMP_50_L 0x010c
#define ADI_REG_TEMP_50_H 0x0110
#define ADI_REG_TEMP_75_L 0x0114
#define ADI_REG_TEMP_75_H 0x0118
#define ADI_REG_TEMP_100_L 0x011c
#define ADI_REG_IRQ_MASK 0x0040 #define ADI_REG_IRQ_MASK 0x0040
#define ADI_REG_IRQ_PENDING 0x0044 #define ADI_REG_IRQ_PENDING 0x0044
@ -62,6 +71,39 @@ static inline u32 axi_ioread(const u32 reg,
return ioread32(ctl->base + reg); return ioread32(ctl->base + reg);
} }
/*
* The core calculates the temperature as:
* T = /raw * 509.3140064 / 65535) - 280.2308787
*/
static ssize_t axi_fan_control_show(struct device *dev, struct device_attribute *da, char *buf)
{
struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
u32 temp = axi_ioread(attr->index, ctl);
temp = DIV_ROUND_CLOSEST_ULL(temp * 509314ULL, 65535) - 280230;
return sprintf(buf, "%u\n", temp);
}
static ssize_t axi_fan_control_store(struct device *dev, struct device_attribute *da,
const char *buf, size_t count)
{
struct axi_fan_control_data *ctl = dev_get_drvdata(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(da);
u32 temp;
int ret;
ret = kstrtou32(buf, 10, &temp);
if (ret)
return ret;
temp = DIV_ROUND_CLOSEST_ULL((temp + 280230) * 65535ULL, 509314);
axi_iowrite(temp, attr->index, ctl);
return count;
}
static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl) static long axi_fan_control_get_pwm_duty(const struct axi_fan_control_data *ctl)
{ {
u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl); u32 pwm_width = axi_ioread(ADI_REG_PWM_WIDTH, ctl);
@ -370,6 +412,36 @@ static const struct hwmon_chip_info axi_chip_info = {
.info = axi_fan_control_info, .info = axi_fan_control_info,
}; };
/* temperature threshold below which PWM should be 0% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp_hyst, axi_fan_control, ADI_REG_TEMP_00_H);
/* temperature threshold above which PWM should be 25% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point1_temp, axi_fan_control, ADI_REG_TEMP_25_L);
/* temperature threshold below which PWM should be 25% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp_hyst, axi_fan_control, ADI_REG_TEMP_25_H);
/* temperature threshold above which PWM should be 50% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point2_temp, axi_fan_control, ADI_REG_TEMP_50_L);
/* temperature threshold below which PWM should be 50% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp_hyst, axi_fan_control, ADI_REG_TEMP_50_H);
/* temperature threshold above which PWM should be 75% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point3_temp, axi_fan_control, ADI_REG_TEMP_75_L);
/* temperature threshold below which PWM should be 75% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp_hyst, axi_fan_control, ADI_REG_TEMP_75_H);
/* temperature threshold above which PWM should be 100% */
static SENSOR_DEVICE_ATTR_RW(pwm1_auto_point4_temp, axi_fan_control, ADI_REG_TEMP_100_L);
static struct attribute *axi_fan_control_attrs[] = {
&sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point2_temp_hyst.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point3_temp_hyst.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point4_temp_hyst.dev_attr.attr,
&sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
NULL,
};
ATTRIBUTE_GROUPS(axi_fan_control);
static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a'); static const u32 version_1_0_0 = ADI_AXI_PCORE_VER(1, 0, 'a');
static const struct of_device_id axi_fan_control_of_match[] = { static const struct of_device_id axi_fan_control_of_match[] = {
@ -423,6 +495,21 @@ static int axi_fan_control_probe(struct platform_device *pdev)
return -ENODEV; return -ENODEV;
} }
ret = axi_fan_control_init(ctl, pdev->dev.of_node);
if (ret) {
dev_err(&pdev->dev, "Failed to initialize device\n");
return ret;
}
ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
name,
ctl,
&axi_chip_info,
axi_fan_control_groups);
if (IS_ERR(ctl->hdev))
return PTR_ERR(ctl->hdev);
ctl->irq = platform_get_irq(pdev, 0); ctl->irq = platform_get_irq(pdev, 0);
if (ctl->irq < 0) if (ctl->irq < 0)
return ctl->irq; return ctl->irq;
@ -436,19 +523,7 @@ static int axi_fan_control_probe(struct platform_device *pdev)
return ret; return ret;
} }
ret = axi_fan_control_init(ctl, pdev->dev.of_node); return 0;
if (ret) {
dev_err(&pdev->dev, "Failed to initialize device\n");
return ret;
}
ctl->hdev = devm_hwmon_device_register_with_info(&pdev->dev,
name,
ctl,
&axi_chip_info,
NULL);
return PTR_ERR_OR_ZERO(ctl->hdev);
} }
static struct platform_driver axi_fan_control_driver = { static struct platform_driver axi_fan_control_driver = {

2
drivers/hwmon/coretemp.c
View File

@ -41,7 +41,7 @@ MODULE_PARM_DESC(tjmax, "TjMax value in degrees Celsius");
#define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */ #define PKG_SYSFS_ATTR_NO 1 /* Sysfs attribute for package temp */
#define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */ #define BASE_SYSFS_ATTR_NO 2 /* Sysfs Base attr no for coretemp */
#define NUM_REAL_CORES 128 /* Number of Real cores per cpu */ #define NUM_REAL_CORES 128 /* Number of Real cores per cpu */
#define CORETEMP_NAME_LENGTH 19 /* String Length of attrs */ #define CORETEMP_NAME_LENGTH 28 /* String Length of attrs */
#define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */ #define MAX_CORE_ATTRS 4 /* Maximum no of basic attrs */
#define TOTAL_ATTRS (MAX_CORE_ATTRS + 1) #define TOTAL_ATTRS (MAX_CORE_ATTRS + 1)
#define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO) #define MAX_CORE_DATA (NUM_REAL_CORES + BASE_SYSFS_ATTR_NO)

4
drivers/i3c/master.c
View File

@ -1509,9 +1509,11 @@ i3c_master_register_new_i3c_devs(struct i3c_master_controller *master)
desc->dev->dev.of_node = desc->boardinfo->of_node; desc->dev->dev.of_node = desc->boardinfo->of_node;
ret = device_register(&desc->dev->dev); ret = device_register(&desc->dev->dev);
if (ret) if (ret) {
dev_err(&master->dev, dev_err(&master->dev,
"Failed to add I3C device (err = %d)\n", ret); "Failed to add I3C device (err = %d)\n", ret);
put_device(&desc->dev->dev);
}
} }
} }

2
drivers/infiniband/hw/hfi1/efivar.c
View File

@ -152,7 +152,7 @@ int read_hfi1_efi_var(struct hfi1_devdata *dd, const char *kind,
unsigned long *size, void **return_data) unsigned long *size, void **return_data)
{ {
char prefix_name[64]; char prefix_name[64];
char name[64]; char name[128];
int result; int result;
int i; int i;

2
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
View File

@ -247,7 +247,7 @@ static bool check_inl_data_len(struct hns_roce_qp *qp, unsigned int len)
struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device); struct hns_roce_dev *hr_dev = to_hr_dev(qp->ibqp.device);
int mtu = ib_mtu_enum_to_int(qp->path_mtu); int mtu = ib_mtu_enum_to_int(qp->path_mtu);
if (len > qp->max_inline_data || len > mtu) { if (mtu < 0 || len > qp->max_inline_data || len > mtu) {
ibdev_err(&hr_dev->ib_dev, ibdev_err(&hr_dev->ib_dev,
"invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n", "invalid length of data, data len = %u, max inline len = %u, path mtu = %d.\n",
len, qp->max_inline_data, mtu); len, qp->max_inline_data, mtu);

2
drivers/infiniband/hw/hns/hns_roce_qp.c
View File

@ -906,7 +906,7 @@ static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
{ {
struct hns_roce_ib_create_qp_resp resp = {}; struct hns_roce_ib_create_qp_resp resp = {};
struct ib_device *ibdev = &hr_dev->ib_dev; struct ib_device *ibdev = &hr_dev->ib_dev;
struct hns_roce_ib_create_qp ucmd; struct hns_roce_ib_create_qp ucmd = {};
int ret; int ret;
mutex_init(&hr_qp->mutex); mutex_init(&hr_qp->mutex);

27
drivers/infiniband/hw/mlx5/qp.c
View File

@ -3714,6 +3714,30 @@ static unsigned int get_tx_affinity(struct ib_qp *qp,
return tx_affinity; return tx_affinity;
} }
static int __mlx5_ib_qp_set_raw_qp_counter(struct mlx5_ib_qp *qp, u32 set_id,
struct mlx5_core_dev *mdev)
{
struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
u32 in[MLX5_ST_SZ_DW(modify_rq_in)] = {};
void *rqc;
if (!qp->rq.wqe_cnt)
return 0;
MLX5_SET(modify_rq_in, in, rq_state, rq->state);
MLX5_SET(modify_rq_in, in, uid, to_mpd(qp->ibqp.pd)->uid);
rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
MLX5_SET64(modify_rq_in, in, modify_bitmask,
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
MLX5_SET(rqc, rqc, counter_set_id, set_id);
return mlx5_core_modify_rq(mdev, rq->base.mqp.qpn, in);
}
static int __mlx5_ib_qp_set_counter(struct ib_qp *qp, static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
struct rdma_counter *counter) struct rdma_counter *counter)
{ {
@ -3729,6 +3753,9 @@ static int __mlx5_ib_qp_set_counter(struct ib_qp *qp,
else else
set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1); set_id = mlx5_ib_get_counters_id(dev, mqp->port - 1);
if (mqp->type == IB_QPT_RAW_PACKET)
return __mlx5_ib_qp_set_raw_qp_counter(mqp, set_id, dev->mdev);
base = &mqp->trans_qp.base; base = &mqp->trans_qp.base;
MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP); MLX5_SET(rts2rts_qp_in, in, opcode, MLX5_CMD_OP_RTS2RTS_QP);
MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn); MLX5_SET(rts2rts_qp_in, in, qpn, base->mqp.qpn);

2
drivers/input/rmi4/rmi_bus.c
View File

@ -276,11 +276,11 @@ void rmi_unregister_function(struct rmi_function *fn)
device_del(&fn->dev); device_del(&fn->dev);
of_node_put(fn->dev.of_node); of_node_put(fn->dev.of_node);
put_device(&fn->dev);
for (i = 0; i < fn->num_of_irqs; i++) for (i = 0; i < fn->num_of_irqs; i++)
irq_dispose_mapping(fn->irq[i]); irq_dispose_mapping(fn->irq[i]);
put_device(&fn->dev);
} }
/** /**

256
drivers/interconnect/qcom/sc7180.c
View File

@ -153,30 +153,238 @@ DEFINE_QNODE(srvc_snoc, SC7180_SLAVE_SERVICE_SNOC, 1, 4);
DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4); DEFINE_QNODE(xs_qdss_stm, SC7180_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8); DEFINE_QNODE(xs_sys_tcu_cfg, SC7180_SLAVE_TCU, 1, 8);
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi); static struct qcom_icc_bcm bcm_acv = {
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi); .name = "ACV",
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc); .enable_mask = BIT(3),
DEFINE_QBCM(bcm_mm0, "MM0", false, &qns_mem_noc_hf); .keepalive = false,
DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto); .num_nodes = 1,
DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_aop, &qhs_aoss, &qhs_boot_rom, &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg, &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl, &qhs_cpr_cx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_display_rt_throttle_cfg, &qhs_display_throttle_cfg, &qhs_glm, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_mnoc_cfg, &qhs_mss_cfg, &qhs_npu_cfg, &qhs_npu_dma_throttle_cfg, &qhs_npu_dsp_throttle_cfg, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qm_cfg, &qhs_qm_mpu_cfg, &qhs_qup0, &qhs_qup1, &qhs_security, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm_1, &qhs_tlmm_2, &qhs_tlmm_3, &qhs_ufs_mem_cfg, &qhs_usb3, &qhs_venus_cfg, &qhs_venus_throttle_cfg, &qhs_vsense_ctrl_cfg, &srvc_cnoc); .nodes = { &ebi },
DEFINE_QBCM(bcm_mm1, "MM1", false, &qxm_camnoc_hf0_uncomp, &qxm_camnoc_hf1_uncomp, &qxm_camnoc_sf_uncomp, &qhm_mnoc_cfg, &qxm_mdp0, &qxm_rot, &qxm_venus0, &qxm_venus_arm9); };
DEFINE_QBCM(bcm_sh2, "SH2", false, &acm_sys_tcu);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf); static struct qcom_icc_bcm bcm_mc0 = {
DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup_core_master_1, &qup_core_master_2); .name = "MC0",
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc); .keepalive = true,
DEFINE_QBCM(bcm_sh4, "SH4", false, &acm_apps0); .num_nodes = 1,
DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf); .nodes = { &ebi },
DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_gemnoc); };
DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
DEFINE_QBCM(bcm_cn1, "CN1", false, &qhm_qspi, &xm_sdc2, &xm_emmc, &qhs_ahb2phy2, &qhs_emmc_cfg, &qhs_pdm, &qhs_qspi, &qhs_sdc2); static struct qcom_icc_bcm bcm_sh0 = {
DEFINE_QBCM(bcm_sn2, "SN2", false, &qxm_pimem, &qns_gemnoc_gc); .name = "SH0",
DEFINE_QBCM(bcm_co2, "CO2", false, &qnm_npu); .keepalive = true,
DEFINE_QBCM(bcm_sn3, "SN3", false, &qxs_pimem); .num_nodes = 1,
DEFINE_QBCM(bcm_co3, "CO3", false, &qxm_npu_dsp); .nodes = { &qns_llcc },
DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_qdss_stm); };
DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_aggre2_noc); static struct qcom_icc_bcm bcm_mm0 = {
DEFINE_QBCM(bcm_sn12, "SN12", false, &qnm_gemnoc); .name = "MM0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
.num_nodes = 48,
.nodes = { &qnm_snoc,
&xm_qdss_dap,
&qhs_a1_noc_cfg,
&qhs_a2_noc_cfg,
&qhs_ahb2phy0,
&qhs_aop,
&qhs_aoss,
&qhs_boot_rom,
&qhs_camera_cfg,
&qhs_camera_nrt_throttle_cfg,
&qhs_camera_rt_throttle_cfg,
&qhs_clk_ctl,
&qhs_cpr_cx,
&qhs_cpr_mx,
&qhs_crypto0_cfg,
&qhs_dcc_cfg,
&qhs_ddrss_cfg,
&qhs_display_cfg,
&qhs_display_rt_throttle_cfg,
&qhs_display_throttle_cfg,
&qhs_glm,
&qhs_gpuss_cfg,
&qhs_imem_cfg,
&qhs_ipa,
&qhs_mnoc_cfg,
&qhs_mss_cfg,
&qhs_npu_cfg,
&qhs_npu_dma_throttle_cfg,
&qhs_npu_dsp_throttle_cfg,
&qhs_pimem_cfg,
&qhs_prng,
&qhs_qdss_cfg,
&qhs_qm_cfg,
&qhs_qm_mpu_cfg,
&qhs_qup0,
&qhs_qup1,
&qhs_security,
&qhs_snoc_cfg,
&qhs_tcsr,
&qhs_tlmm_1,
&qhs_tlmm_2,
&qhs_tlmm_3,
&qhs_ufs_mem_cfg,
&qhs_usb3,
&qhs_venus_cfg,
&qhs_venus_throttle_cfg,
&qhs_vsense_ctrl_cfg,
&srvc_cnoc
},
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.keepalive = false,
.num_nodes = 8,
.nodes = { &qxm_camnoc_hf0_uncomp,
&qxm_camnoc_hf1_uncomp,
&qxm_camnoc_sf_uncomp,
&qhm_mnoc_cfg,
&qxm_mdp0,
&qxm_rot,
&qxm_venus0,
&qxm_venus_arm9
},
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.keepalive = false,
.num_nodes = 1,
.nodes = { &acm_sys_tcu },
};
static struct qcom_icc_bcm bcm_mm2 = {
.name = "MM2",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qup_core_master_1, &qup_core_master_2 },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_cmpnoc },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.keepalive = false,
.num_nodes = 1,
.nodes = { &acm_apps0 },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qns_cdsp_gemnoc },
};
static struct qcom_icc_bcm bcm_sn1 = {
.name = "SN1",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxs_imem },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.keepalive = false,
.num_nodes = 8,
.nodes = { &qhm_qspi,
&xm_sdc2,
&xm_emmc,
&qhs_ahb2phy2,
&qhs_emmc_cfg,
&qhs_pdm,
&qhs_qspi,
&qhs_sdc2
},
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.keepalive = false,
.num_nodes = 2,
.nodes = { &qxm_pimem, &qns_gemnoc_gc },
};
static struct qcom_icc_bcm bcm_co2 = {
.name = "CO2",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_npu },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxs_pimem },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qxm_npu_dsp },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.keepalive = false,
.num_nodes = 1,
.nodes = { &xs_qdss_stm },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_bcm bcm_sn9 = {
.name = "SN9",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_bcm bcm_sn12 = {
.name = "SN12",
.keepalive = false,
.num_nodes = 1,
.nodes = { &qnm_gemnoc },
};
static struct qcom_icc_bcm *aggre1_noc_bcms[] = { static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
&bcm_cn1, &bcm_cn1,

2
drivers/leds/leds-pwm.c
View File

@ -51,7 +51,7 @@ static int led_pwm_set(struct led_classdev *led_cdev,
duty = led_dat->pwmstate.period - duty; duty = led_dat->pwmstate.period - duty;
led_dat->pwmstate.duty_cycle = duty; led_dat->pwmstate.duty_cycle = duty;
led_dat->pwmstate.enabled = duty > 0; led_dat->pwmstate.enabled = true;
return pwm_apply_state(led_dat->pwm, &led_dat->pwmstate); return pwm_apply_state(led_dat->pwm, &led_dat->pwmstate);
} }

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