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EDAC, amd64: Add Hygon Dhyana support

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Add support for Hygon Dhyana CPU to EDAC.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: mchehab@kernel.org
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: thomas.lendacky@amd.com
Cc: linux-edac@vger.kernel.org
Link: https://lkml.kernel.org/r/9d71061301177822bc55b3bfd44f91057458d886.1537533369.git.puwen@hygon.cn
This commit is contained in:
Pu Wen 2018-09-27 16:31:28 +02:00 committed by Borislav Petkov
parent d913e8966a
commit c4a3e94641
2 changed files with 12 additions and 2 deletions
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10
drivers/edac/amd64_edac.c
View File

@ -211,7 +211,7 @@ static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
scrubval = scrubrates[i].scrubval; scrubval = scrubrates[i].scrubval;
if (pvt->fam == 0x17) { if (pvt->fam == 0x17 || pvt->fam == 0x18) {
__f17h_set_scrubval(pvt, scrubval); __f17h_set_scrubval(pvt, scrubval);
} else if (pvt->fam == 0x15 && pvt->model == 0x60) { } else if (pvt->fam == 0x15 && pvt->model == 0x60) {
f15h_select_dct(pvt, 0); f15h_select_dct(pvt, 0);
@ -264,6 +264,7 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
break; break;
case 0x17: case 0x17:
case 0x18:
amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval); amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
if (scrubval & BIT(0)) { if (scrubval & BIT(0)) {
amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval); amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
@ -1044,6 +1045,7 @@ static void determine_memory_type(struct amd64_pvt *pvt)
goto ddr3; goto ddr3;
case 0x17: case 0x17:
case 0x18:
if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
pvt->dram_type = MEM_LRDDR4; pvt->dram_type = MEM_LRDDR4;
else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
@ -3202,8 +3204,13 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
pvt->ops = &family_types[F17_M10H_CPUS].ops; pvt->ops = &family_types[F17_M10H_CPUS].ops;
break; break;
} }
/* fall through */
case 0x18:
fam_type = &family_types[F17_CPUS]; fam_type = &family_types[F17_CPUS];
pvt->ops = &family_types[F17_CPUS].ops; pvt->ops = &family_types[F17_CPUS].ops;
if (pvt->fam == 0x18)
family_types[F17_CPUS].ctl_name = "F18h";
break; break;
default: default:
@ -3442,6 +3449,7 @@ static const struct x86_cpu_id amd64_cpuids[] = {
{ X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x15, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x16, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 }, { X86_VENDOR_AMD, 0x17, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ X86_VENDOR_HYGON, 0x18, X86_MODEL_ANY, X86_FEATURE_ANY, 0 },
{ } { }
}; };
MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids); MODULE_DEVICE_TABLE(x86cpu, amd64_cpuids);

4
drivers/edac/mce_amd.c
View File

@ -1059,7 +1059,8 @@ static int __init mce_amd_init(void)
{ {
struct cpuinfo_x86 *c = &boot_cpu_data; struct cpuinfo_x86 *c = &boot_cpu_data;
if (c->x86_vendor != X86_VENDOR_AMD) if (c->x86_vendor != X86_VENDOR_AMD &&
c->x86_vendor != X86_VENDOR_HYGON)
return -ENODEV; return -ENODEV;
fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL); fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
@ -1113,6 +1114,7 @@ static int __init mce_amd_init(void)
break; break;
case 0x17: case 0x17:
case 0x18:
xec_mask = 0x3f; xec_mask = 0x3f;
if (!boot_cpu_has(X86_FEATURE_SMCA)) { if (!boot_cpu_has(X86_FEATURE_SMCA)) {
printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n"); printk(KERN_WARNING "Decoding supported only on Scalable MCA processors.\n");