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net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii

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[ Upstream commit 621427fbdada788f18f77238e1c36f463c2cb9d1 ]

RGMII mode can be enable from dp83822 straps, and also writing bit 9
of register 0x17 - RMII and Status Register (RCSR).
When phy_interface_is_rgmii rgmii mode must be enabled, same for
contrary, this prevents malconfigurations of hw straps

References:
 - https://www.ti.com/lit/gpn/dp83822i p66

Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: c8a5c731fd12 ("net: phy: dp83822: Fix RGMII TX delay configuration")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Tommaso Merciai 2022-05-21 01:58:46 +02:00 committed by Sasha Levin
parent a352d039ff
commit c44a5aa4be
1 changed files with 8 additions and 1 deletions
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9
drivers/net/phy/dp83822.c
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@ -94,7 +94,8 @@
#define DP83822_WOL_INDICATION_SEL BIT(8)
#define DP83822_WOL_CLR_INDICATION BIT(11)
/* RSCR bits */
/* RCSR bits */
#define DP83822_RGMII_MODE_EN BIT(9)
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
@ -386,6 +387,12 @@ static int dp83822_config_init(struct phy_device *phydev)
if (err)
return err;
}
phy_set_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
} else {
phy_clear_bits_mmd(phydev, DP83822_DEVADDR,
MII_DP83822_RCSR, DP83822_RGMII_MODE_EN);
}
if (dp83822->fx_enabled) {