android/android_kernel_xiaomi_sm8450
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drm/radeon: add some additional 6xx/7xx/EG register init

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- SMX_SAR_CTL0 needs to be programmed correctly to prevent
problems with memory exports in certain cases.
- VC_ENHANCE needs to be initialized on 6xx/7xx.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher 2012-06-14 22:06:36 +02:00 committed by Dave Airlie
parent 6b53a0507b
commit b866d1334b
6 changed files with 13 additions and 1 deletions
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3
drivers/gpu/drm/radeon/evergreen.c
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@ -1932,6 +1932,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
WREG32(SMX_DC_CTL0, smx_dc_ctl0); WREG32(SMX_DC_CTL0, smx_dc_ctl0);
if (rdev->family <= CHIP_SUMO2)
WREG32(SMX_SAR_CTL0, 0x00010000);
WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));

1
drivers/gpu/drm/radeon/evergreend.h
View File

@ -503,6 +503,7 @@
#define SCRATCH_UMSK 0x8540 #define SCRATCH_UMSK 0x8540
#define SCRATCH_ADDR 0x8544 #define SCRATCH_ADDR 0x8544
#define SMX_SAR_CTL0 0xA008
#define SMX_DC_CTL0 0xA020 #define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0) #define USE_HASH_FUNCTION (1 << 0)
#define NUMBER_OF_SETS(x) ((x) << 1) #define NUMBER_OF_SETS(x) ((x) << 1)

1
drivers/gpu/drm/radeon/r600.c
View File

@ -1839,6 +1839,7 @@ void r600_gpu_init(struct radeon_device *rdev)
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
NUM_CLIP_SEQ(3))); NUM_CLIP_SEQ(3)));
WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
WREG32(VC_ENHANCE, 0);
} }

1
drivers/gpu/drm/radeon/r600d.h
View File

@ -485,6 +485,7 @@
#define TC_L2_SIZE(x) ((x)<<5) #define TC_L2_SIZE(x) ((x)<<5)
#define L2_DISABLE_LATE_HIT (1<<9) #define L2_DISABLE_LATE_HIT (1<<9)
#define VC_ENHANCE 0x9714
#define VGT_CACHE_INVALIDATION 0x88C4 #define VGT_CACHE_INVALIDATION 0x88C4
#define CACHE_INVALIDATION(x) ((x)<<0) #define CACHE_INVALIDATION(x) ((x)<<0)

5
drivers/gpu/drm/radeon/rv770.c
View File

@ -616,6 +616,9 @@ static void rv770_gpu_init(struct radeon_device *rdev)
ACK_FLUSH_CTL(3) | ACK_FLUSH_CTL(3) |
SYNC_FLUSH_CTL)); SYNC_FLUSH_CTL));
if (rdev->family != CHIP_RV770)
WREG32(SMX_SAR_CTL0, 0x00003f3f);
db_debug3 = RREG32(DB_DEBUG3); db_debug3 = RREG32(DB_DEBUG3);
db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f); db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
switch (rdev->family) { switch (rdev->family) {
@ -792,7 +795,7 @@ static void rv770_gpu_init(struct radeon_device *rdev)
WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
NUM_CLIP_SEQ(3))); NUM_CLIP_SEQ(3)));
WREG32(VC_ENHANCE, 0);
} }
void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)

3
drivers/gpu/drm/radeon/rv770d.h
View File

@ -211,6 +211,7 @@
#define SCRATCH_UMSK 0x8540 #define SCRATCH_UMSK 0x8540
#define SCRATCH_ADDR 0x8544 #define SCRATCH_ADDR 0x8544
#define SMX_SAR_CTL0 0xA008
#define SMX_DC_CTL0 0xA020 #define SMX_DC_CTL0 0xA020
#define USE_HASH_FUNCTION (1 << 0) #define USE_HASH_FUNCTION (1 << 0)
#define CACHE_DEPTH(x) ((x) << 1) #define CACHE_DEPTH(x) ((x) << 1)
@ -310,6 +311,8 @@
#define TCP_CNTL 0x9610 #define TCP_CNTL 0x9610
#define TCP_CHAN_STEER 0x9614 #define TCP_CHAN_STEER 0x9614
#define VC_ENHANCE 0x9714
#define VGT_CACHE_INVALIDATION 0x88C4 #define VGT_CACHE_INVALIDATION 0x88C4
#define CACHE_INVALIDATION(x) ((x)<<0) #define CACHE_INVALIDATION(x) ((x)<<0)
#define VC_ONLY 0 #define VC_ONLY 0