android/android_kernel_xiaomi_sm8450
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

parisc: document the shadow registers

Browse Source 
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: <stable@vger.kernel.org> # 3.10
This commit is contained in:
Helge Deller 2013-06-29 13:24:16 +02:00
parent 30a9f0b251
commit a83f58bcb2
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/parisc/registers
View File

@ -77,6 +77,14 @@ PSW default E value 0
Shadow Registers used by interruption handler code Shadow Registers used by interruption handler code
TOC enable bit 1 TOC enable bit 1
=========================================================================
The PA-RISC architecture defines 7 registers as "shadow registers".
Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce
the state save and restore time by eliminating the need for general register
(GR) saves and restores in interruption handlers.
Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25.
========================================================================= =========================================================================
Register usage notes, originally from John Marvin, with some additional Register usage notes, originally from John Marvin, with some additional
notes from Randolph Chung. notes from Randolph Chung.