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Merge "msm: ep_pcie: Allow L1 states while switching back to D0 from D3hot"

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qctecmdr 2021-11-23 21:47:46 -08:00 committed by Gerrit - the friendly Code Review server
commit 9ecf5a17c2
1 changed files with 8 additions and 0 deletions
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8
drivers/platform/msm/ep_pcie/ep_pcie_core.c
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@ -2287,6 +2287,14 @@ static irqreturn_t ep_pcie_handle_dstate_change_irq(int irq, void *data)
} else if (dstate == 0) {
dev->l23_ready = false;
dev->d0_counter++;
/*
* When device is trasistion back to D0 from D3hot
* (without D3cold), REQ_EXIT_L1 bit won't get cleared.
* And L1 would get blocked till next D3cold.
* So clear it explicitly during D0.
*/
ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(1), 0);
atomic_set(&dev->host_wake_pending, 0);
EP_PCIE_DBG(dev,
"PCIe V%d: No. %ld change to D0 state, clearing wake pending:%d\n",