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clk: Reset code to align with upstream

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Reset clock code to align with android12-5.10 commit b129c98dc6
("Merge 5.10.17 into android12-5.10").

Change-Id: I07a40310fe76b4b059e8a604e942363af923fb45
Signed-off-by: Mike Tipton <mdtipton@codeaurora.org>
This commit is contained in:
Mike Tipton 2021-02-19 11:36:07 -08:00 committed by Vivek Aknurwar
parent 4a5a92ec37
commit 84a9635b12
11 changed files with 4 additions and 126 deletions
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4
drivers/clk/clk-divider.c
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@ -295,9 +295,6 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struct clk_hw *parent,
unsigned long parent_rate, best = 0, now, maxdiv;
unsigned long parent_rate_saved = *best_parent_rate;
if (!hw || !parent)
return -EINVAL;
if (!rate)
rate = 1;
@ -511,7 +508,6 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
/* register the clock */
hw = &div->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(div);
hw = ERR_PTR(ret);

1
drivers/clk/clk-fixed-factor.c
View File

@ -98,7 +98,6 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
ret = clk_hw_register(dev, hw);
else
ret = of_clk_hw_register(np, hw);
hw->init = NULL;
if (ret) {
kfree(fix);
hw = ERR_PTR(ret);

1
drivers/clk/clk-fixed-rate.c
View File

@ -89,7 +89,6 @@ struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
ret = clk_hw_register(dev, hw);
else if (np)
ret = of_clk_hw_register(np, hw);
hw->init = NULL;
if (ret) {
kfree(fixed);
hw = ERR_PTR(ret);

1
drivers/clk/clk-fractional-divider.c
View File

@ -185,7 +185,6 @@ struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
hw = &fd->hw;
ret = clk_hw_register(dev, hw);
hw->init = NULL;
if (ret) {
kfree(fd);
hw = ERR_PTR(ret);

1
drivers/clk/clk-gate.c
View File

@ -171,7 +171,6 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
ret = clk_hw_register(dev, hw);
else if (np)
ret = of_clk_hw_register(np, hw);
hw->init = NULL;
if (ret) {
kfree(gate);
hw = ERR_PTR(ret);

1
drivers/clk/clk-gpio.c
View File

@ -166,7 +166,6 @@ static struct clk_hw *clk_register_gpio(struct device *dev, u8 num_parents,
err = devm_clk_hw_register(dev, hw);
if (err)
return ERR_PTR(err);
hw->init = NULL;
return hw;
}

1
drivers/clk/clk-mux.c
View File

@ -197,7 +197,6 @@ struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
ret = clk_hw_register(dev, hw);
else if (np)
ret = of_clk_hw_register(np, hw);
hw->init = NULL;
if (ret) {
kfree(mux);
hw = ERR_PTR(ret);

76
drivers/clk/clk.c
View File

@ -2574,7 +2574,7 @@ static int clk_core_set_parent_nolock(struct clk_core *core,
if (!core)
return 0;
if (core->parent == parent && !(core->flags & CLK_IS_MEASURE))
if (core->parent == parent)
return 0;
/* verify ops for multi-parent clks */
@ -3306,76 +3306,6 @@ static int clk_max_rate_show(struct seq_file *s, void *data)
}
DEFINE_SHOW_ATTRIBUTE(clk_max_rate);
static int clock_debug_rate_set(void *data, u64 val)
{
struct clk_core *core = data;
int ret;
ret = clk_set_rate(core->hw->clk, val);
if (ret)
pr_err("clk_set_rate(%lu) failed (%d)\n",
(unsigned long)val, ret);
return ret;
}
static int clock_debug_rate_get(void *data, u64 *val)
{
struct clk_core *core = data;
*val = clk_get_rate(core->hw->clk);
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(clock_rate_fops, clock_debug_rate_get,
clock_debug_rate_set, "%llu\n");
static ssize_t clock_parent_read(struct file *filp, char __user *ubuf,
size_t cnt, loff_t *ppos)
{
char name[256] = {0};
struct clk_core *core = filp->private_data;
struct clk_core *p = core->hw->core->parent;
snprintf(name, sizeof(name), "%s\n", p ? p->name : "None\n");
return simple_read_from_buffer(ubuf, cnt, ppos, name, strlen(name));
}
static const struct file_operations clock_parent_fops = {
.open = simple_open,
.read = clock_parent_read,
};
static int clock_debug_enable_set(void *data, u64 val)
{
struct clk_core *core = data;
int rc = 0;
if (val)
rc = clk_prepare_enable(core->hw->clk);
else
clk_disable_unprepare(core->hw->clk);
return rc;
}
static int clock_debug_enable_get(void *data, u64 *val)
{
struct clk_core *core = data;
int enabled = 0;
enabled = core->enable_count;
*val = enabled;
return 0;
}
DEFINE_DEBUGFS_ATTRIBUTE(clock_enable_fops, clock_debug_enable_get,
clock_debug_enable_set, "%lld\n");
static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
{
struct dentry *root;
@ -3394,8 +3324,7 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
debugfs_create_u32("clk_phase", 0444, root, &core->phase);
debugfs_create_file("clk_flags", 0444, root, core, &clk_flags_fops);
debugfs_create_u32("clk_prepare_count", 0444, root, &core->prepare_count);
debugfs_create_file("clk_enable_count", 0444, root, core,
&clock_enable_fops);
debugfs_create_u32("clk_enable_count", 0444, root, &core->enable_count);
debugfs_create_u32("clk_protect_count", 0444, root, &core->protect_count);
debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
debugfs_create_file("clk_duty_cycle", 0444, root, core,
@ -3706,6 +3635,7 @@ static int __clk_core_init(struct clk_core *core)
clk_core_hold_state(core);
clk_core_reparent_orphans_nolock();
kref_init(&core->ref);
out:
clk_pm_runtime_put(core);

1
drivers/clk/clk.h
View File

@ -25,7 +25,6 @@ struct clk_hw *clk_find_hw(const char *dev_id, const char *con_id);
struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
const char *dev_id, const char *con_id);
void __clk_put(struct clk *clk);
#else
/* All these casts to avoid ifdefs in clkdev... */
static inline struct clk *

5
include/linux/clk-provider.h
View File

@ -33,7 +33,6 @@
/* duty cycle call may be forwarded to the parent clock */
#define CLK_DUTY_CYCLE_PARENT BIT(13)
#define CLK_DONT_HOLD_STATE BIT(14) /* Don't hold state */
#define CLK_IS_MEASURE BIT(15) /* clock used for measurement only */
struct clk;
struct clk_hw;
@ -215,10 +214,6 @@ struct clk_duty {
* requirements that were needed while the clock and its tree
* was changing states. Returns 0 on success, -EERROR otherwise.
*
* @list_rate_vdd_level: Queries the required voltage level for the given rate.
* The return value may not represent an exact voltage and instead
* may be an abstract index or voltage "corner".
*
* The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
* implementations to split any work between atomic (enable) and sleepable
* (prepare) contexts. If enabling a clock requires code that might sleep,

38
include/trace/events/clk.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
*/
#undef TRACE_SYSTEM
#define TRACE_SYSTEM clk
@ -220,42 +220,6 @@ DEFINE_EVENT(clk_duty_cycle, clk_set_duty_cycle_complete,
TP_ARGS(core, duty)
);
DECLARE_EVENT_CLASS(clk_state_dump,
TP_PROTO(const char *name, unsigned int prepare_count,
unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
TP_ARGS(name, prepare_count, enable_count, rate, vdd_level),
TP_STRUCT__entry(
__string(name, name)
__field(unsigned int, prepare_count)
__field(unsigned int, enable_count)
__field(unsigned long, rate)
__field(unsigned int, vdd_level)
),
TP_fast_assign(
__assign_str(name, name);
__entry->prepare_count = prepare_count;
__entry->enable_count = enable_count;
__entry->rate = rate;
__entry->vdd_level = vdd_level;
),
TP_printk("%s\tprepare:enable cnt [%u:%u]\trate: vdd_level [%lu:%u]",
__get_str(name), __entry->prepare_count, __entry->enable_count,
__entry->rate, __entry->vdd_level)
);
DEFINE_EVENT(clk_state_dump, clk_state,
TP_PROTO(const char *name, unsigned int prepare_count,
unsigned int enable_count, unsigned long rate, unsigned int vdd_level),
TP_ARGS(name, prepare_count, enable_count, rate, vdd_level)
);
#endif /* _TRACE_CLK_H */
/* This part must be outside protection */