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ANDROID: iommu/dma: Add support for DMA_ATTR_SYS_CACHE_ONLY_NWA

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IOMMU_SYS_CACHE_ONLY_NWA allows buffers for non-coherent devices
to be mapped with the correct memory attributes so that the buffers
can be cached in the system cache, with a no write allocate cache policy.
However, this property is only usable by drivers that invoke the
IOMMU API directly; it is not usable by drivers that use the DMA API.

Thus, introduce DMA_ATTR_SYS_CACHE_ONLY_NWA, so that drivers for
non-coherent devices that use the DMA API can use it to specify if
they want a buffer to be cached in the system cache.

Bug: 176778547
Change-Id: Ic812a1fb144a58deb4279c2bf121fc6cc4c3b208
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
This commit is contained in:
Isaac J. Manjarres 2021-01-04 18:11:10 -08:00 committed by Suren Baghdasaryan
parent 0b653f27bb
commit 7cfc6861b8
3 changed files with 13 additions and 1 deletions
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2
drivers/iommu/dma-iommu.c
View File

@ -434,6 +434,8 @@ static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
prot |= IOMMU_PRIV;
if (attrs & DMA_ATTR_SYS_CACHE_ONLY)
prot |= IOMMU_SYS_CACHE_ONLY;
if (attrs & DMA_ATTR_SYS_CACHE_ONLY_NWA)
prot |= IOMMU_SYS_CACHE_ONLY_NWA;
switch (dir) {
case DMA_BIDIRECTIONAL:

9
include/linux/dma-mapping.h
View File

@ -69,6 +69,15 @@
*/
#define DMA_ATTR_SYS_CACHE_ONLY (1UL << 10)
/*
* DMA_ATTR_SYS_CACHE_ONLY_NWA: used to indicate that the buffer should be
* mapped with the correct memory attributes so that it can be cached in the
* system or last level cache, with a no write allocate cache policy. This is
* useful for buffers that are being mapped for devices that are non-coherent,
* but can use the system cache.
*/
#define DMA_ATTR_SYS_CACHE_ONLY_NWA (1UL << 11)
/*
* A dma_addr_t can hold any valid DMA or bus address for the platform. It can
* be given to a device to use as a DMA source or target. It is specific to a

3
kernel/dma/mapping.c
View File

@ -348,7 +348,8 @@ pgprot_t dma_pgprot(struct device *dev, pgprot_t prot, unsigned long attrs)
if (attrs & DMA_ATTR_WRITE_COMBINE)
return pgprot_writecombine(prot);
#endif
if (attrs & DMA_ATTR_SYS_CACHE_ONLY)
if (attrs & DMA_ATTR_SYS_CACHE_ONLY ||
attrs & DMA_ATTR_SYS_CACHE_ONLY_NWA)
return pgprot_syscached(prot);
return pgprot_dmacoherent(prot);
}