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ARM: dts: i.MX51: Separate TXD/RXD and RTS/CTS pinmux entries for UARTs

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RTS/CTS pins can be used for different purposes, so create separate
definitions for these pins.

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Alexander Shiyan 2013-08-21 11:28:23 +04:00 committed by Shawn Guo
parent 44a2687708
commit 727b8124f5
2 changed files with 12 additions and 2 deletions
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4
arch/arm/boot/dts/imx51-babbage.dts
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@ -95,7 +95,7 @@ &esdhc2 {
&uart3 { &uart3 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>; pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_rtscts_1>;
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };
@ -252,7 +252,7 @@ MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
&uart1 { &uart1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>; pinctrl-0 = <&pinctrl_uart1_1 &pinctrl_uart1_rtscts_1>;
fsl,uart-has-rtscts; fsl,uart-has-rtscts;
status = "okay"; status = "okay";
}; };

10
arch/arm/boot/dts/imx51.dtsi
View File

@ -747,6 +747,11 @@ pinctrl_uart1_1: uart1grp-1 {
fsl,pins = < fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
>;
};
pinctrl_uart1_rtscts_1: uart1rtscts-1 {
fsl,pins = <
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>; >;
@ -767,6 +772,11 @@ pinctrl_uart3_1: uart3grp-1 {
fsl,pins = < fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
>;
};
pinctrl_uart3_rtscts_1: uart3rtscts-1 {
fsl,pins = <
MX51_PAD_EIM_D27__UART3_RTS 0x1c5 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>; >;