drm/amd/display: dcn20_resource_construct reduce scope of FPU enabled
[ Upstream commit bc39a69a2ac484e6575a958567c162ef56c9f278 ] Limit when FPU is enabled to only functions that does FPU operations for dcn20_resource_construct, which gets called during driver initialization. Enabling FPU operation disables preemption. Sleeping functions(mutex (un)lock, memory allocation using GFP_KERNEL, etc.) should not be called when preemption is disabled. Fixes the following case caught by enabling CONFIG_DEBUG_ATOMIC_SLEEP in kernel config [ 1.338434] BUG: sleeping function called from invalid context at kernel/locking/mutex.c:281 [ 1.347395] in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 197, name: systemd-udevd [ 1.356356] CPU: 7 PID: 197 Comm: systemd-udevd Not tainted 5.13.0+ #3 [ 1.356358] Hardware name: System manufacturer System Product Name/PRIME X570-PRO, BIOS 3405 02/01/2021 [ 1.356360] Call Trace: [ 1.356361] dump_stack+0x6b/0x86 [ 1.356366] ___might_sleep.cold+0x87/0x98 [ 1.356370] __might_sleep+0x4b/0x80 [ 1.356372] mutex_lock+0x21/0x50 [ 1.356376] smu_get_uclk_dpm_states+0x3f/0x80 [amdgpu] [ 1.356538] pp_nv_get_uclk_dpm_states+0x35/0x50 [amdgpu] [ 1.356711] init_soc_bounding_box+0xf9/0x210 [amdgpu] [ 1.356892] ? create_object+0x20d/0x340 [ 1.356897] ? dcn20_resource_construct+0x46f/0xd30 [amdgpu] [ 1.357077] dcn20_resource_construct+0x4b1/0xd30 [amdgpu] ... Tested on: 5700XT (NAVI10 0x1002:0x731F 0x1DA2:0xE410 0xC1) Cc: Christian König <christian.koenig@amd.com> Cc: Hersen Wu <hersenxs.wu@amd.com> Cc: Anson Jacob <Anson.Jacob@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com> Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -3754,16 +3754,22 @@ static bool init_soc_bounding_box(struct dc *dc,
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clock_limits_available = (status == PP_SMU_RESULT_OK);
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}
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if (clock_limits_available && uclk_states_available && num_states)
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if (clock_limits_available && uclk_states_available && num_states) {
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DC_FP_START();
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dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
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else if (clock_limits_available)
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DC_FP_END();
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} else if (clock_limits_available) {
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DC_FP_START();
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dcn20_cap_soc_clocks(loaded_bb, max_clocks);
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DC_FP_END();
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}
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}
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loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
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loaded_ip->max_num_dpp = pool->base.pipe_count;
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DC_FP_START();
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dcn20_patch_bounding_box(dc, loaded_bb);
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DC_FP_END();
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return true;
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}
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@ -3783,8 +3789,6 @@ static bool dcn20_resource_construct(
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enum dml_project dml_project_version =
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get_dml_project_version(ctx->asic_id.hw_internal_rev);
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DC_FP_START();
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ctx->dc_bios->regs = &bios_regs;
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pool->base.funcs = &dcn20_res_pool_funcs;
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@ -4128,12 +4132,10 @@ static bool dcn20_resource_construct(
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pool->base.oem_device = NULL;
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}
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DC_FP_END();
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return true;
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create_fail:
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DC_FP_END();
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dcn20_resource_destruct(pool);
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return false;
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