lan743x: Add support for ethtool eeprom access
Implement ethtool eeprom access Also provides access to OTP (One Time Programming) Signed-off-by: Bryan Whitehead <Bryan.Whitehead@microchip.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bryan Whitehead
David S. Miller
parent
2958337d68
commit
695846047a
@ -7,6 +7,178 @@
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#include <linux/pci.h>
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#include <linux/phy.h>
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/* eeprom */
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#define LAN743X_EEPROM_MAGIC (0x74A5)
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#define LAN743X_OTP_MAGIC (0x74F3)
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#define EEPROM_INDICATOR_1 (0xA5)
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#define EEPROM_INDICATOR_2 (0xAA)
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#define EEPROM_MAC_OFFSET (0x01)
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#define MAX_EEPROM_SIZE 512
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#define OTP_INDICATOR_1 (0xF3)
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#define OTP_INDICATOR_2 (0xF7)
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static int lan743x_otp_write(struct lan743x_adapter *adapter, u32 offset,
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u32 length, u8 *data)
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{
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unsigned long timeout;
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u32 buf;
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int i;
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buf = lan743x_csr_read(adapter, OTP_PWR_DN);
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if (buf & OTP_PWR_DN_PWRDN_N_) {
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/* clear it and wait to be cleared */
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lan743x_csr_write(adapter, OTP_PWR_DN, 0);
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timeout = jiffies + HZ;
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do {
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udelay(1);
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buf = lan743x_csr_read(adapter, OTP_PWR_DN);
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if (time_after(jiffies, timeout)) {
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netif_warn(adapter, drv, adapter->netdev,
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"timeout on OTP_PWR_DN completion\n");
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return -EIO;
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}
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} while (buf & OTP_PWR_DN_PWRDN_N_);
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}
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/* set to BYTE program mode */
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lan743x_csr_write(adapter, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
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for (i = 0; i < length; i++) {
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lan743x_csr_write(adapter, OTP_ADDR1,
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((offset + i) >> 8) &
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OTP_ADDR1_15_11_MASK_);
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lan743x_csr_write(adapter, OTP_ADDR2,
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((offset + i) &
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OTP_ADDR2_10_3_MASK_));
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lan743x_csr_write(adapter, OTP_PRGM_DATA, data[i]);
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lan743x_csr_write(adapter, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
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lan743x_csr_write(adapter, OTP_CMD_GO, OTP_CMD_GO_GO_);
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timeout = jiffies + HZ;
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do {
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udelay(1);
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buf = lan743x_csr_read(adapter, OTP_STATUS);
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if (time_after(jiffies, timeout)) {
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netif_warn(adapter, drv, adapter->netdev,
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"Timeout on OTP_STATUS completion\n");
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return -EIO;
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}
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} while (buf & OTP_STATUS_BUSY_);
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}
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return 0;
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}
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static int lan743x_eeprom_wait(struct lan743x_adapter *adapter)
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{
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unsigned long start_time = jiffies;
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u32 val;
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do {
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val = lan743x_csr_read(adapter, E2P_CMD);
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if (!(val & E2P_CMD_EPC_BUSY_) ||
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(val & E2P_CMD_EPC_TIMEOUT_))
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break;
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usleep_range(40, 100);
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} while (!time_after(jiffies, start_time + HZ));
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if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
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netif_warn(adapter, drv, adapter->netdev,
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"EEPROM read operation timeout\n");
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return -EIO;
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}
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return 0;
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}
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static int lan743x_eeprom_confirm_not_busy(struct lan743x_adapter *adapter)
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{
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unsigned long start_time = jiffies;
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u32 val;
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do {
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val = lan743x_csr_read(adapter, E2P_CMD);
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if (!(val & E2P_CMD_EPC_BUSY_))
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return 0;
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usleep_range(40, 100);
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} while (!time_after(jiffies, start_time + HZ));
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netif_warn(adapter, drv, adapter->netdev, "EEPROM is busy\n");
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return -EIO;
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}
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static int lan743x_eeprom_read(struct lan743x_adapter *adapter,
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u32 offset, u32 length, u8 *data)
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{
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int retval;
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u32 val;
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int i;
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retval = lan743x_eeprom_confirm_not_busy(adapter);
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if (retval)
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return retval;
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for (i = 0; i < length; i++) {
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
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val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
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lan743x_csr_write(adapter, E2P_CMD, val);
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retval = lan743x_eeprom_wait(adapter);
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if (retval < 0)
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return retval;
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val = lan743x_csr_read(adapter, E2P_DATA);
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data[i] = val & 0xFF;
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offset++;
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}
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return 0;
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}
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static int lan743x_eeprom_write(struct lan743x_adapter *adapter,
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u32 offset, u32 length, u8 *data)
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{
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int retval;
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u32 val;
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int i;
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retval = lan743x_eeprom_confirm_not_busy(adapter);
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if (retval)
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return retval;
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/* Issue write/erase enable command */
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
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lan743x_csr_write(adapter, E2P_CMD, val);
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retval = lan743x_eeprom_wait(adapter);
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if (retval < 0)
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return retval;
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for (i = 0; i < length; i++) {
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/* Fill data register */
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val = data[i];
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lan743x_csr_write(adapter, E2P_DATA, val);
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/* Send "write" command */
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val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
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val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
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lan743x_csr_write(adapter, E2P_CMD, val);
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retval = lan743x_eeprom_wait(adapter);
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if (retval < 0)
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return retval;
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offset++;
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}
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return 0;
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}
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static void lan743x_ethtool_get_drvinfo(struct net_device *netdev,
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struct ethtool_drvinfo *info)
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{
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@ -32,6 +204,40 @@ static void lan743x_ethtool_set_msglevel(struct net_device *netdev,
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adapter->msg_enable = msglevel;
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}
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static int lan743x_ethtool_get_eeprom_len(struct net_device *netdev)
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{
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return MAX_EEPROM_SIZE;
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}
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static int lan743x_ethtool_get_eeprom(struct net_device *netdev,
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struct ethtool_eeprom *ee, u8 *data)
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{
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struct lan743x_adapter *adapter = netdev_priv(netdev);
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return lan743x_eeprom_read(adapter, ee->offset, ee->len, data);
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}
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static int lan743x_ethtool_set_eeprom(struct net_device *netdev,
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struct ethtool_eeprom *ee, u8 *data)
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{
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struct lan743x_adapter *adapter = netdev_priv(netdev);
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int ret = -EINVAL;
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if (ee->magic == LAN743X_EEPROM_MAGIC)
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ret = lan743x_eeprom_write(adapter, ee->offset, ee->len,
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data);
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/* Beware! OTP is One Time Programming ONLY!
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* So do some strict condition check before messing up
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*/
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else if ((ee->magic == LAN743X_OTP_MAGIC) &&
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(ee->offset == 0) &&
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(ee->len == MAX_EEPROM_SIZE) &&
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(data[0] == OTP_INDICATOR_1))
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ret = lan743x_otp_write(adapter, ee->offset, ee->len, data);
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return ret;
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}
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static const char lan743x_set0_hw_cnt_strings[][ETH_GSTRING_LEN] = {
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"RX FCS Errors",
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"RX Alignment Errors",
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@ -215,6 +421,9 @@ const struct ethtool_ops lan743x_ethtool_ops = {
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.set_msglevel = lan743x_ethtool_set_msglevel,
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.get_link = ethtool_op_get_link,
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.get_eeprom_len = lan743x_ethtool_get_eeprom_len,
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.get_eeprom = lan743x_ethtool_get_eeprom,
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.set_eeprom = lan743x_ethtool_set_eeprom,
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.get_strings = lan743x_ethtool_get_strings,
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.get_ethtool_stats = lan743x_ethtool_get_ethtool_stats,
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.get_sset_count = lan743x_ethtool_get_sset_count,
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@ -42,6 +42,16 @@
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#define DP_DATA_0 (0x030)
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#define E2P_CMD (0x040)
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#define E2P_CMD_EPC_BUSY_ BIT(31)
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#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000)
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#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000)
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#define E2P_CMD_EPC_CMD_READ_ (0x00000000)
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#define E2P_CMD_EPC_TIMEOUT_ BIT(10)
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#define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF)
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#define E2P_DATA (0x044)
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#define FCT_RX_CTL (0xAC)
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#define FCT_RX_CTL_EN_(channel) BIT(28 + (channel))
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#define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel))
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@ -288,6 +298,29 @@
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#define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3)
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#define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007)
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#define OTP_PWR_DN (0x1000)
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#define OTP_PWR_DN_PWRDN_N_ BIT(0)
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#define OTP_ADDR1 (0x1004)
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#define OTP_ADDR1_15_11_MASK_ (0x1F)
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#define OTP_ADDR2 (0x1008)
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#define OTP_ADDR2_10_3_MASK_ (0xFF)
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#define OTP_PRGM_DATA (0x1010)
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#define OTP_PRGM_MODE (0x1014)
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#define OTP_PRGM_MODE_BYTE_ BIT(0)
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#define OTP_TST_CMD (0x1024)
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#define OTP_TST_CMD_PRGVRFY_ BIT(3)
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#define OTP_CMD_GO (0x1028)
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#define OTP_CMD_GO_GO_ BIT(0)
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#define OTP_STATUS (0x1030)
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#define OTP_STATUS_BUSY_ BIT(0)
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/* MAC statistics registers */
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#define STAT_RX_FCS_ERRORS (0x1200)
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#define STAT_RX_ALIGNMENT_ERRORS (0x1204)
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