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MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instruction

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MIPS R6 introduced the following instruction:
SELEQZ.fmt: FPR[fd]  FPR[ft].bit0 ? 0 : FPR[fs]

Add support for emulating the single and double precision formats
of the said instruction.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/10954/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras 2015-08-13 09:56:29 +02:00 committed by Ralf Baechle
parent f8c3c6717a
commit 67613f0278
1 changed files with 23 additions and 0 deletions
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23
arch/mips/math-emu/cp1emu.c
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@ -1743,6 +1743,17 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
SPFROMREG(rv.s, MIPSInst_FS(ir)); SPFROMREG(rv.s, MIPSInst_FS(ir));
break; break;
case fseleqz_op:
if (!cpu_has_mips_r6)
return SIGILL;
SPFROMREG(rv.s, MIPSInst_FT(ir));
if (rv.w & 0x1)
rv.w = 0;
else
SPFROMREG(rv.s, MIPSInst_FS(ir));
break;
case fabs_op: case fabs_op:
handler.u = ieee754sp_abs; handler.u = ieee754sp_abs;
goto scopuop; goto scopuop;
@ -1940,6 +1951,18 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
return 0; return 0;
DPFROMREG(rv.d, MIPSInst_FS(ir)); DPFROMREG(rv.d, MIPSInst_FS(ir));
break; break;
case fseleqz_op:
if (!cpu_has_mips_r6)
return SIGILL;
DPFROMREG(rv.d, MIPSInst_FT(ir));
if (rv.l & 0x1)
rv.l = 0;
else
DPFROMREG(rv.d, MIPSInst_FS(ir));
break;
case fabs_op: case fabs_op:
handler.u = ieee754dp_abs; handler.u = ieee754dp_abs;
goto dcopuop; goto dcopuop;