PCI: Cache PCIe Device Capabilities register
[ Upstream commit 69139244806537f9d51364f37fe146bb2ee88a05 ] Add a new member called devcap in struct pci_dev for caching the PCIe Device Capabilities register to avoid reading PCI_EXP_DEVCAP multiple times. Refactor pcie_has_flr() to use cached device capabilities. Link: https://lore.kernel.org/r/20210817180500.1253-2-ameynarkhede03@gmail.com Signed-off-by: Amey Narkhede <ameynarkhede03@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Stable-dep-of: 627c6db20703 ("PCI/DPC: Quirk PIO log size for Intel Raptor Lake Root Ports") Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -31,6 +31,7 @@
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#include <linux/vmalloc.h>
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#include <asm/dma.h>
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#include <linux/aer.h>
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#include <linux/bitfield.h>
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#include "pci.h"
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DEFINE_MUTEX(pci_slot_mutex);
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@ -4572,13 +4573,10 @@ EXPORT_SYMBOL(pci_wait_for_pending_transaction);
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*/
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bool pcie_has_flr(struct pci_dev *dev)
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{
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u32 cap;
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if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
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return false;
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pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
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return cap & PCI_EXP_DEVCAP_FLR;
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return FIELD_GET(PCI_EXP_DEVCAP_FLR, dev->devcap) == 1;
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}
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EXPORT_SYMBOL_GPL(pcie_has_flr);
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@ -19,6 +19,7 @@
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#include <linux/hypervisor.h>
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#include <linux/irqdomain.h>
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#include <linux/pm_runtime.h>
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#include <linux/bitfield.h>
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#include "pci.h"
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#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
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@ -1496,8 +1497,8 @@ void set_pcie_port_type(struct pci_dev *pdev)
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pdev->pcie_cap = pos;
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pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
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pdev->pcie_flags_reg = reg16;
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pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
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pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
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pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
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pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
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parent = pci_upstream_bridge(pdev);
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if (!parent)
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@ -333,6 +333,7 @@ struct pci_dev {
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#ifdef CONFIG_PCIEPORTBUS
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struct rcec_ea *rcec_ea; /* RCEC cached endpoint association */
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#endif
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u32 devcap; /* PCIe Device Capabilities */
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u8 pcie_cap; /* PCIe capability offset */
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u8 msi_cap; /* MSI capability offset */
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u8 msix_cap; /* MSI-X capability offset */
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