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ANDROID: GKI: pcie: Fix the broken dw_pcie structure

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This patch fix the break to abi dw_pcie structure and keep other code AS
IS.

Bug: 239396464
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I138f28812eb4254671fa353a7541e65bddfc1bda
This commit is contained in:
Kever Yang 2022-07-22 10:40:07 +08:00 committed by Steve Muckle
parent 51b3e17071
commit 5fa1e1affc
3 changed files with 11 additions and 9 deletions
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6
drivers/pci/controller/dwc/pcie-designware-host.c
View File

@ -479,7 +479,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
ret = pci_generic_config_read(bus, devfn, where, size, val);
if (!ret && pci->io_cfg_atu_shared)
if (!ret && (pci->iatu_unroll_enabled & DWC_IATU_IOCFG_SHARED))
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@ -495,7 +495,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
ret = pci_generic_config_write(bus, devfn, where, size, val);
if (!ret && pci->io_cfg_atu_shared)
if (!ret && (pci->iatu_unroll_enabled & DWC_IATU_IOCFG_SHARED))
dw_pcie_prog_outbound_atu(pci, 0, PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
@ -606,7 +606,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
else
pci->io_cfg_atu_shared = true;
pci->iatu_unroll_enabled |= DWC_IATU_IOCFG_SHARED;
}
if (pci->num_viewport <= atu_idx)

9
drivers/pci/controller/dwc/pcie-designware.c
View File

@ -274,7 +274,7 @@ static void __dw_pcie_prog_outbound_atu(struct dw_pcie *pci, u8 func_no,
if (pci->ops->cpu_addr_fixup)
cpu_addr = pci->ops->cpu_addr_fixup(pci, cpu_addr);
if (pci->iatu_unroll_enabled) {
if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN) {
dw_pcie_prog_outbound_atu_unroll(pci, func_no, index, type,
cpu_addr, pci_addr, size);
return;
@ -394,7 +394,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
int type;
u32 retries, val;
if (pci->iatu_unroll_enabled)
if (pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN)
return dw_pcie_prog_inbound_atu_unroll(pci, func_no, index, bar,
cpu_addr, as_type);
@ -554,14 +554,15 @@ void dw_pcie_setup(struct dw_pcie *pci)
if (pci->version >= 0x480A || (!pci->version &&
dw_pcie_iatu_unroll_enabled(pci))) {
pci->iatu_unroll_enabled = true;
pci->iatu_unroll_enabled |= DWC_IATU_UNROLL_EN;
if (!pci->atu_base)
pci->atu_base =
devm_platform_ioremap_resource_byname(pdev, "atu");
if (IS_ERR(pci->atu_base))
pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
}
dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ?
dev_dbg(pci->dev, "iATU unroll: %s\n",
pci->iatu_unroll_enabled & DWC_IATU_UNROLL_EN ?
"enabled" : "disabled");
if (pci->link_gen > 0)

5
drivers/pci/controller/dwc/pcie-designware.h
View File

@ -256,6 +256,8 @@ struct dw_pcie_ops {
void (*stop_link)(struct dw_pcie *pcie);
};
#define DWC_IATU_UNROLL_EN BIT(0)
#define DWC_IATU_IOCFG_SHARED BIT(1)
struct dw_pcie {
struct device *dev;
void __iomem *dbi_base;
@ -263,6 +265,7 @@ struct dw_pcie {
/* Used when iatu_unroll_enabled is true */
void __iomem *atu_base;
u32 num_viewport;
u8 iatu_unroll_enabled;
struct pcie_port pp;
struct dw_pcie_ep ep;
const struct dw_pcie_ops *ops;
@ -270,8 +273,6 @@ struct dw_pcie {
int num_lanes;
int link_gen;
u8 n_fts[2];
bool iatu_unroll_enabled: 1;
bool io_cfg_atu_shared: 1;
};
#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)