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driver: pinctrl: Add reserved GPIOs for Shima

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Certain GPIOs are reserved for secure world and cannot be accessed by HLOS.
Supply "reserved_gpios" to msm_pinctrl to mark these pins as invalid.

Change-Id: Ic8f45181b2210a6295bba1bdec45d24e607bede9
Signed-off-by: Mukesh Ojha <mojha@codeaurora.org>
This commit is contained in:
Mukesh Ojha 2020-05-27 15:47:16 +05:30 committed by Gerrit - the friendly Code Review server
parent 98446bc531
commit 5a08ead3da
1 changed files with 6 additions and 0 deletions
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6
drivers/pinctrl/qcom/pinctrl-shima.c
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@ -1861,6 +1861,11 @@ static const struct msm_pingroup shima_groups[] = {
[210] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x1d1000, 11, 3),
[211] = SDC_QDSD_PINGROUP(sdc2_data, 0x1d1000, 9, 0),
};
static const int shima_reserved_gpios[] = {
24, 25, 26, 27, 40, 41, 42, 43, -1
};
static struct pinctrl_qup shima_qup_regs[] = {
QUP_I3C(0, QUP_I3C_0_MODE_OFFSET),
QUP_I3C(1, QUP_I3C_1_MODE_OFFSET),
@ -1892,6 +1897,7 @@ static const struct msm_pinctrl_soc_data shima_pinctrl = {
.nfunctions = ARRAY_SIZE(shima_functions),
.groups = shima_groups,
.ngroups = ARRAY_SIZE(shima_groups),
.reserved_gpios = shima_reserved_gpios,
.ngpios = 205,
.qup_regs = shima_qup_regs,
.nqup_regs = ARRAY_SIZE(shima_qup_regs),