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msm: kgsl: Store Gen7 snapshot blocks in a structure

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Store snapshot blocks in a new structure to make it easier to
add blocks for different targets.

Change-Id: Ie0bee4424d553d31de2ee8342c8396eafe24c3e0
Signed-off-by: Urvashi Agrawal <quic_urvaagra@quicinc.com>
Signed-off-by: Lynus Vaz <quic_lvaz@quicinc.com>
Signed-off-by: Rohan Sethi <quic_rohsethi@quicinc.com>
This commit is contained in:
Rohan Sethi 2022-05-27 13:07:16 +05:30
parent 6282d072f5
commit 59b799af9e
5 changed files with 543 additions and 803 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/msm/adreno-gpulist.h
View File

@ -1779,6 +1779,9 @@ static const struct adreno_a6xx_core adreno_gpu_core_a662 = {
.ctxt_record_size = 2496 * 1024,
};
extern const struct gen7_snapshot_block_list gen7_0_0_snapshot_block_list;
extern const struct gen7_snapshot_block_list gen7_3_0_snapshot_block_list;
static const struct kgsl_regmap_list gen7_0_0_gbif_regs[] = {
{ GEN7_GBIF_QSB_SIDE0, 0x00071620 },
{ GEN7_GBIF_QSB_SIDE1, 0x00071620 },
@ -1981,6 +1984,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_0_0 = {
.hang_detect_cycles = 0xcfffff,
.protected_regs = gen7_0_0_protected_regs,
.highest_bank_bit = 16,
.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
};
static const struct adreno_gen7_core adreno_gpu_core_gen7_0_1 = {
@ -2011,6 +2015,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_0_1 = {
.hang_detect_cycles = 0xcfffff,
.protected_regs = gen7_0_0_protected_regs,
.highest_bank_bit = 16,
.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
};
static const struct adreno_gen7_core adreno_gpu_core_gen7_4_0 = {
@ -2040,6 +2045,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_4_0 = {
.hang_detect_cycles = 0xcfffff,
.protected_regs = gen7_0_0_protected_regs,
.highest_bank_bit = 16,
.gen7_snapshot_block_list = &gen7_0_0_snapshot_block_list,
};
static const struct adreno_gen7_core adreno_gpu_core_gen7_3_0 = {
@ -2067,6 +2073,7 @@ static const struct adreno_gen7_core adreno_gpu_core_gen7_3_0 = {
.hang_detect_cycles = 0xcfffff,
.protected_regs = gen7_0_0_protected_regs,
.highest_bank_bit = 15,
.gen7_snapshot_block_list = &gen7_3_0_snapshot_block_list,
};
static const struct adreno_gpu_core *adreno_gpulist[] = {

5
drivers/gpu/msm/adreno_gen7.h
View File

@ -17,6 +17,9 @@
#define PIPE_BV 2
#define PIPE_LPAC 3
/* Forward struct declaration */
struct gen7_snapshot_block_list;
extern const struct adreno_power_ops gen7_gmu_power_ops;
extern const struct adreno_power_ops gen7_hwsched_power_ops;
extern const struct adreno_perfcounters adreno_gen7_perfcounters;
@ -93,6 +96,8 @@ struct adreno_gen7_core {
u32 highest_bank_bit;
/** @gmu_hub_clk_freq: Gmu hub interface clock frequency */
u64 gmu_hub_clk_freq;
/** @gen7_snapshot_block_list: Device-specific blocks dumped in the snapshot */
const struct gen7_snapshot_block_list *gen7_snapshot_block_list;
};
/**

123
drivers/gpu/msm/adreno_gen7_gmu_snapshot.c
View File

@ -8,110 +8,10 @@
#include "adreno.h"
#include "adreno_gen7.h"
#include "adreno_gen7_gmu.h"
#include "adreno_gen7_snapshot.h"
#include "adreno_snapshot.h"
#include "kgsl_device.h"
static const u32 gen7_gmu_registers[] = {
0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2,
0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f914, 0x1f920, 0x1f921,
0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f958, 0x1f95a,
0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f96b, 0x1f970, 0x1f979,
0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e,
0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa,
0x1fa00, 0x1fa03, 0x20000, 0x20005, 0x20008, 0x2000c, 0x20010, 0x20012,
0x20018, 0x20018, 0x20020, 0x20023, 0x20030, 0x20031, 0x23801, 0x23801,
0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809,
0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811,
0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819,
0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822,
0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a,
0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832,
0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a,
0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01,
0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16,
0x23b20, 0x23b20, 0x23b28, 0x23b28, 0x23b30, 0x23b30,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_gmu_registers), 8));
static const u32 gen7_3_0_gmu_registers[] = {
0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
0x1f400, 0x1f40b, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2,
0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f911, 0x1f920, 0x1f921,
0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f980, 0x1f981, 0x1f984, 0x1f986,
0x1f992, 0x1f993, 0x1f996, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4,
0x1f9f1, 0x1f9f1, 0x1f9f8, 0x1f9fa, 0x1fa00, 0x1fa03, 0x20000, 0x20005,
0x20008, 0x20009, 0x20010, 0x20012, 0x20018, 0x20018, 0x20020, 0x20023,
0x20030, 0x20031, 0x23801, 0x23801, 0x23803, 0x23803, 0x23805, 0x23805,
0x23807, 0x23807, 0x23809, 0x23809, 0x2380b, 0x2380b, 0x2380d, 0x2380d,
0x2380f, 0x2380f, 0x23811, 0x23811, 0x23813, 0x23813, 0x23815, 0x23815,
0x23817, 0x23817, 0x23819, 0x23819, 0x2381b, 0x2381b, 0x2381d, 0x2381d,
0x2381f, 0x23820, 0x23822, 0x23822, 0x23824, 0x23824, 0x23826, 0x23826,
0x23828, 0x23828, 0x2382a, 0x2382a, 0x2382c, 0x2382c, 0x2382e, 0x2382e,
0x23830, 0x23830, 0x23832, 0x23832, 0x23834, 0x23834, 0x23836, 0x23836,
0x23838, 0x23838, 0x2383a, 0x2383a, 0x2383c, 0x2383c, 0x2383e, 0x2383e,
0x23840, 0x23847, 0x23b00, 0x23b01, 0x23b03, 0x23b03, 0x23b05, 0x23b0e,
0x23b10, 0x23b13, 0x23b15, 0x23b16, 0x23b20, 0x23b20, 0x23b28, 0x23b28,
0x23b30, 0x23b30,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_3_0_gmu_registers), 8));
static const u32 gen7_gmu_gx_registers[] = {
0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df,
0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df,
0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789, 0x1a78b, 0x1a78d,
0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799, 0x1a79b, 0x1a79b,
0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd,
0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd,
0x1a800, 0x1a802, 0x1a804, 0x1a804, 0x1a816, 0x1a816, 0x1a81e, 0x1a81e,
0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836, 0x1a83e, 0x1a83e,
0x1a846, 0x1a846, 0x1a860, 0x1a862, 0x1a864, 0x1a867, 0x1a870, 0x1a870,
0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2, 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3,
0x1a900, 0x1a92b, 0x1a940, 0x1a940,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_gmu_gx_registers), 8));
static const u32 gen7_3_0_gmu_gx_registers[] = {
0x1a802, 0x1a802, 0x1a883, 0x1a884, 0x1a900, 0x1a92b, 0x1a940, 0x1a940,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_3_0_gmu_gx_registers), 8));
static const u32 gen7_rscc_registers[] = {
0x14000, 0x14036, 0x14040, 0x14042, 0x14080, 0x14084, 0x14089, 0x1408c,
0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac,
0x14100, 0x14102, 0x14114, 0x14119, 0x14124, 0x1412e, 0x14140, 0x14143,
0x14180, 0x14197, 0x14340, 0x14342, 0x14344, 0x14347, 0x1434c, 0x14373,
0x143ec, 0x143ef, 0x143f4, 0x1441b, 0x14494, 0x14497, 0x1449c, 0x144c3,
0x1453c, 0x1453f, 0x14544, 0x1456b, 0x145e4, 0x145e7, 0x145ec, 0x14613,
0x1468c, 0x1468f, 0x14694, 0x146bb, 0x14734, 0x14737, 0x1473c, 0x14763,
0x147dc, 0x147df, 0x147e4, 0x1480b, 0x14884, 0x14887, 0x1488c, 0x148b3,
0x1492c, 0x1492f, 0x14934, 0x1495b, 0x14f51, 0x14f54,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_rscc_registers), 8));
struct gmu_mem_type_desc {
struct kgsl_memdesc *memdesc;
u32 type;
@ -330,6 +230,9 @@ void gen7_gmu_device_snapshot(struct kgsl_device *device,
{
struct adreno_device *adreno_dev = ADRENO_DEVICE(device);
struct gen7_gmu_device *gmu = to_gen7_gmu(adreno_dev);
const struct adreno_gen7_core *gpucore = to_gen7_core(ADRENO_DEVICE(device));
const struct gen7_snapshot_block_list *gen7_snapshot_block_list =
gpucore->gen7_snapshot_block_list;
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_GMU_MEMORY,
snapshot, gen7_gmu_snapshot_itcm, gmu);
@ -338,15 +241,11 @@ void gen7_gmu_device_snapshot(struct kgsl_device *device,
gen7_gmu_snapshot_memories(device, gmu, snapshot);
if (adreno_is_gen7_3_0(adreno_dev))
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_3_0_gmu_registers);
else
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_gmu_registers);
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_snapshot_block_list->gmu_regs);
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
gen7_snapshot_rscc_registers, (void *) gen7_rscc_registers);
gen7_snapshot_rscc_registers, (void *) gen7_snapshot_block_list->rscc_regs);
if (!gen7_gmu_gx_is_on(adreno_dev))
goto dtcm;
@ -356,12 +255,8 @@ void gen7_gmu_device_snapshot(struct kgsl_device *device,
/* Make sure the previous write posted before reading */
wmb();
if (adreno_is_gen7_3_0(adreno_dev))
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_3_0_gmu_gx_registers);
else
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_gmu_gx_registers);
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2, snapshot,
adreno_snapshot_registers_v2, (void *) gen7_snapshot_block_list->gmu_gx_regs);
/* A stalled SMMU can lead to NoC timeouts when host accesses DTCM */
if (gen7_is_smmu_stalled(device)) {

402
drivers/gpu/msm/adreno_gen7_snapshot.c
View File

@ -4,13 +4,64 @@
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "adreno_gen7_snapshot.h"
#include "adreno.h"
#include "adreno_gen7_snapshot.h"
#include "adreno_snapshot.h"
static struct kgsl_memdesc *gen7_capturescript;
static struct kgsl_memdesc *gen7_crashdump_registers;
static u32 *gen7_cd_reg_end;
static const struct gen7_snapshot_block_list *gen7_snapshot_block_list;
const struct gen7_snapshot_block_list gen7_0_0_snapshot_block_list = {
.pre_crashdumper_regs = gen7_0_0_pre_crashdumper_registers,
.cp_indexed_reg_list = gen7_0_0_cp_indexed_reg_list,
.cp_indexed_reg_list_len = ARRAY_SIZE(gen7_0_0_cp_indexed_reg_list),
.debugbus_blocks = gen7_0_0_debugbus_blocks,
.debugbus_blocks_len = ARRAY_SIZE(gen7_0_0_debugbus_blocks),
.gbif_debugbus_blocks = gen7_gbif_debugbus_blocks,
.gbif_debugbus_blocks_len = ARRAY_SIZE(gen7_gbif_debugbus_blocks),
.cx_debugbus_blocks = gen7_cx_dbgc_debugbus_blocks,
.cx_debugbus_blocks_len = ARRAY_SIZE(gen7_cx_dbgc_debugbus_blocks),
.external_core_regs = gen7_0_0_external_core_regs,
.num_external_core_regs = ARRAY_SIZE(gen7_0_0_external_core_regs),
.gmu_regs = gen7_0_0_gmu_registers,
.gmu_gx_regs = gen7_0_0_gmu_gx_registers,
.rscc_regs = gen7_0_0_rscc_registers,
.reg_list = gen7_0_0_reg_list,
.shader_blocks = gen7_0_0_shader_blocks,
.num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks),
.clusters = gen7_0_0_clusters,
.num_clusters = ARRAY_SIZE(gen7_0_0_clusters),
.sptp_clusters = gen7_0_0_sptp_clusters,
.num_sptp_clusters = ARRAY_SIZE(gen7_0_0_sptp_clusters),
.post_crashdumper_regs = gen7_0_0_post_crashdumper_registers,
};
const struct gen7_snapshot_block_list gen7_3_0_snapshot_block_list = {
.pre_crashdumper_regs = gen7_0_0_pre_crashdumper_registers,
.cp_indexed_reg_list = gen7_3_0_cp_indexed_reg_list,
.cp_indexed_reg_list_len = ARRAY_SIZE(gen7_3_0_cp_indexed_reg_list),
.debugbus_blocks = gen7_3_0_debugbus_blocks,
.debugbus_blocks_len = ARRAY_SIZE(gen7_3_0_debugbus_blocks),
.gbif_debugbus_blocks = gen7_gbif_debugbus_blocks,
.gbif_debugbus_blocks_len = ARRAY_SIZE(gen7_gbif_debugbus_blocks),
.cx_debugbus_blocks = gen7_cx_dbgc_debugbus_blocks,
.cx_debugbus_blocks_len = ARRAY_SIZE(gen7_cx_dbgc_debugbus_blocks),
.external_core_regs = gen7_3_0_external_core_regs,
.num_external_core_regs = ARRAY_SIZE(gen7_3_0_external_core_regs),
.gmu_regs = gen7_3_0_gmu_registers,
.gmu_gx_regs = gen7_3_0_gmu_gx_registers,
.rscc_regs = gen7_0_0_rscc_registers,
.reg_list = gen7_0_0_reg_list,
.shader_blocks = gen7_3_0_shader_blocks,
.num_shader_blocks = ARRAY_SIZE(gen7_3_0_shader_blocks),
.clusters = gen7_0_0_clusters,
.num_clusters = ARRAY_SIZE(gen7_0_0_clusters),
.sptp_clusters = gen7_0_0_sptp_clusters,
.num_sptp_clusters = ARRAY_SIZE(gen7_0_0_sptp_clusters),
.post_crashdumper_regs = gen7_0_0_post_crashdumper_registers,
};
#define GEN7_DEBUGBUS_BLOCK_SIZE 0x100
@ -170,14 +221,14 @@ static size_t gen7_legacy_snapshot_shader(struct kgsl_device *device,
}
header->type = block->statetype;
header->index = block->sp_id;
header->index = info->sp_id;
header->size = block->size;
header->usptp = block->usptp;
header->usptp = info->usptp;
header->location = block->location;
header->pipe_id = block->pipeid;
read_sel = GEN7_SP_READ_SEL_VAL(block->location, block->pipeid,
block->statetype, block->usptp, block->sp_id);
block->statetype, info->usptp, info->sp_id);
kgsl_regwrite(device, GEN7_SP_READ_SEL, read_sel);
@ -208,9 +259,9 @@ static size_t gen7_snapshot_shader_memory(struct kgsl_device *device,
}
header->type = block->statetype;
header->index = block->sp_id;
header->index = info->sp_id;
header->size = block->size;
header->usptp = block->usptp;
header->usptp = info->usptp;
header->location = block->location;
header->pipe_id = block->pipeid;
@ -227,120 +278,77 @@ static void gen7_snapshot_shader(struct kgsl_device *device,
struct gen7_shader_block_info info;
u64 *ptr;
u32 offset = 0;
struct gen7_shader_block *shader_blocks = gen7_snapshot_block_list->shader_blocks;
size_t num_shader_blocks = gen7_snapshot_block_list->num_shader_blocks;
unsigned int sp;
unsigned int usptp;
size_t (*func)(struct kgsl_device *device, u8 *buf, size_t remain,
void *priv) = gen7_legacy_snapshot_shader;
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < ARRAY_SIZE(gen7_shader_blocks); i++) {
info.block = &gen7_shader_blocks[i];
info.offset = offset;
offset += gen7_shader_blocks[i].size << 2;
for (i = 0; i < num_shader_blocks; i++) {
struct gen7_shader_block *block = &shader_blocks[i];
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
for (sp = 0; sp < block->num_sps; sp++) {
for (usptp = 0; usptp < block->num_usptps; usptp++) {
info.block = block;
info.sp_id = sp;
info.usptp = usptp;
info.offset = offset;
offset += block->size << 2;
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
}
}
}
return;
}
/* Build the crash script */
ptr = gen7_capturescript->hostptr;
offset = 0;
for (i = 0; i < num_shader_blocks; i++) {
struct gen7_shader_block *block = &shader_blocks[i];
for (i = 0; i < ARRAY_SIZE(gen7_shader_blocks); i++) {
struct gen7_shader_block *block = &gen7_shader_blocks[i];
/* Build the crash script */
ptr = gen7_capturescript->hostptr;
offset = 0;
/* Program the aperture */
ptr += CD_WRITE(ptr, GEN7_SP_READ_SEL,
GEN7_SP_READ_SEL_VAL(block->location, block->pipeid,
block->statetype, block->usptp, block->sp_id));
for (sp = 0; sp < block->num_sps; sp++) {
for (usptp = 0; usptp < block->num_usptps; usptp++) {
/* Program the aperture */
ptr += CD_WRITE(ptr, GEN7_SP_READ_SEL,
GEN7_SP_READ_SEL_VAL(block->location, block->pipeid,
block->statetype, usptp, sp));
/* Read all the data in one chunk */
ptr += CD_READ(ptr, GEN7_SP_AHB_READ_APERTURE, block->size,
gen7_crashdump_registers->gpuaddr + offset);
offset += block->size << 2;
}
/* Marker for end of script */
CD_FINISH(ptr, offset);
/* Try to run the crash dumper */
if (_gen7_do_crashdump(device))
func = gen7_snapshot_shader_memory;
offset = 0;
for (i = 0; i < ARRAY_SIZE(gen7_shader_blocks); i++) {
info.block = &gen7_shader_blocks[i];
info.offset = offset;
offset += gen7_shader_blocks[i].size << 2;
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
}
}
static void gen7_3_0_snapshot_shader(struct kgsl_device *device,
struct kgsl_snapshot *snapshot)
{
unsigned int i;
struct gen7_shader_block_info info;
u64 *ptr;
u32 offset = 0;
size_t (*func)(struct kgsl_device *device, u8 *buf, size_t remain,
void *priv) = gen7_legacy_snapshot_shader;
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < ARRAY_SIZE(gen7_3_0_shader_blocks); i++) {
info.block = &gen7_3_0_shader_blocks[i];
info.offset = offset;
offset += gen7_3_0_shader_blocks[i].size << 2;
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
/* Read all the data in one chunk */
ptr += CD_READ(ptr, GEN7_SP_AHB_READ_APERTURE, block->size,
gen7_crashdump_registers->gpuaddr + offset);
offset += block->size << 2;
}
}
return;
}
/* Marker for end of script */
CD_FINISH(ptr, offset);
/* Build the crash script */
ptr = gen7_capturescript->hostptr;
offset = 0;
/* Try to run the crash dumper */
func = gen7_legacy_snapshot_shader;
if (_gen7_do_crashdump(device))
func = gen7_snapshot_shader_memory;
for (i = 0; i < ARRAY_SIZE(gen7_3_0_shader_blocks); i++) {
struct gen7_shader_block *block = &gen7_3_0_shader_blocks[i];
offset = 0;
for (sp = 0; sp < block->num_sps; sp++) {
for (usptp = 0; usptp < block->num_usptps; usptp++) {
info.block = block;
info.sp_id = sp;
info.usptp = usptp;
info.offset = offset;
offset += block->size << 2;
/* Program the aperture */
ptr += CD_WRITE(ptr, GEN7_SP_READ_SEL,
GEN7_SP_READ_SEL_VAL(block->location, block->pipeid,
block->statetype, block->usptp, block->sp_id));
/* Read all the data in one chunk */
ptr += CD_READ(ptr, GEN7_SP_AHB_READ_APERTURE, block->size,
gen7_crashdump_registers->gpuaddr + offset);
offset += block->size << 2;
}
/* Marker for end of script */
CD_FINISH(ptr, offset);
/* Try to run the crash dumper */
if (_gen7_do_crashdump(device))
func = gen7_snapshot_shader_memory;
offset = 0;
for (i = 0; i < ARRAY_SIZE(gen7_3_0_shader_blocks); i++) {
info.block = &gen7_3_0_shader_blocks[i];
info.offset = offset;
offset += gen7_3_0_shader_blocks[i].size << 2;
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
/* Shader working/shadow memory */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_SHADER_V2,
snapshot, func, &info);
}
}
}
}
@ -465,22 +473,24 @@ static void gen7_snapshot_dbgahb_regs(struct kgsl_device *device,
int i;
u64 *ptr, offset = 0;
unsigned int count;
struct gen7_sptp_cluster_registers *sptp_clusters = gen7_snapshot_block_list->sptp_clusters;
size_t num_sptp_clusters = gen7_snapshot_block_list->num_sptp_clusters;
size_t (*func)(struct kgsl_device *device, u8 *buf, size_t remain,
void *priv) = gen7_legacy_snapshot_cluster_dbgahb;
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < ARRAY_SIZE(gen7_sptp_clusters); i++)
for (i = 0; i < num_sptp_clusters; i++)
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func,
&gen7_sptp_clusters[i]);
&sptp_clusters[i]);
return;
}
/* Build the crash script */
ptr = gen7_capturescript->hostptr;
for (i = 0; i < ARRAY_SIZE(gen7_sptp_clusters); i++) {
struct gen7_sptp_cluster_registers *cluster = &gen7_sptp_clusters[i];
for (i = 0; i < num_sptp_clusters; i++) {
struct gen7_sptp_cluster_registers *cluster = &sptp_clusters[i];
const u32 *regs = cluster->regs;
cluster->offset = offset;
@ -506,9 +516,9 @@ static void gen7_snapshot_dbgahb_regs(struct kgsl_device *device,
func = gen7_snapshot_cluster_dbgahb;
/* Capture the registers in snapshot */
for (i = 0; i < ARRAY_SIZE(gen7_sptp_clusters); i++)
for (i = 0; i < num_sptp_clusters; i++)
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &gen7_sptp_clusters[i]);
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &sptp_clusters[i]);
}
static size_t gen7_legacy_snapshot_mvc(struct kgsl_device *device, u8 *buf,
@ -610,21 +620,23 @@ static void gen7_snapshot_mvc_regs(struct kgsl_device *device,
int i;
u64 *ptr, offset = 0;
unsigned int count;
struct gen7_cluster_registers *clusters = gen7_snapshot_block_list->clusters;
size_t num_clusters = gen7_snapshot_block_list->num_clusters;
size_t (*func)(struct kgsl_device *device, u8 *buf,
size_t remain, void *priv) = gen7_legacy_snapshot_mvc;
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < ARRAY_SIZE(gen7_clusters); i++)
for (i = 0; i < num_clusters; i++)
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &gen7_clusters[i]);
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &clusters[i]);
return;
}
/* Build the crash script */
ptr = gen7_capturescript->hostptr;
for (i = 0; i < ARRAY_SIZE(gen7_clusters); i++) {
struct gen7_cluster_registers *cluster = &gen7_clusters[i];
for (i = 0; i < num_clusters; i++) {
struct gen7_cluster_registers *cluster = &clusters[i];
const u32 *regs = cluster->regs;
cluster->offset = offset;
@ -651,9 +663,9 @@ static void gen7_snapshot_mvc_regs(struct kgsl_device *device,
if (_gen7_do_crashdump(device))
func = gen7_snapshot_mvc;
for (i = 0; i < ARRAY_SIZE(gen7_clusters); i++)
for (i = 0; i < num_clusters; i++)
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &gen7_clusters[i]);
KGSL_SNAPSHOT_SECTION_MVC_V2, snapshot, func, &clusters[i]);
}
/* gen7_dbgc_debug_bus_read() - Read data from trace bus */
@ -933,84 +945,43 @@ static void gen7_snapshot_debugbus(struct adreno_device *adreno_dev,
adreno_cx_dbgc_regwrite(device, GEN7_CX_DBGC_CFG_DBGBUS_MASKL_2, 0);
adreno_cx_dbgc_regwrite(device, GEN7_CX_DBGC_CFG_DBGBUS_MASKL_3, 0);
if (adreno_is_gen7_3_0(adreno_dev))
for (i = 0; i < ARRAY_SIZE(gen7_3_0_debugbus_blocks); i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_debugbus_block,
(void *) &gen7_3_0_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_side_debugbus_block,
(void *) &gen7_3_0_debugbus_blocks[i]);
}
else
for (i = 0; i < ARRAY_SIZE(gen7_debugbus_blocks); i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_debugbus_block,
(void *) &gen7_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_side_debugbus_block,
(void *) &gen7_debugbus_blocks[i]);
}
/*
* GBIF has same debugbus as of other GPU blocks hence fall back to
* default path if GPU uses GBIF.
* GBIF uses exactly same ID as of VBIF so use it as it is.
*/
kgsl_snapshot_add_section(device,
for (i = 0; i < gen7_snapshot_block_list->debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[0]);
(void *) &gen7_snapshot_block_list->debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_side_debugbus_block,
(void *) &gen7_snapshot_block_list->debugbus_blocks[i]);
}
kgsl_snapshot_add_section(device,
for (i = 0; i < gen7_snapshot_block_list->gbif_debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[1]);
kgsl_snapshot_add_section(device,
(void *) &gen7_snapshot_block_list->gbif_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_side_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[0]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_dbgc_side_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[1]);
(void *) &gen7_snapshot_block_list->gbif_debugbus_blocks[i]);
}
/* Dump the CX debugbus data if the block exists */
if (adreno_is_cx_dbgc_register(device, GEN7_CX_DBGC_CFG_DBGBUS_SEL_A)) {
for (i = 0; i < ARRAY_SIZE(gen7_cx_dbgc_debugbus_blocks); i++) {
for (i = 0; i < gen7_snapshot_block_list->cx_debugbus_blocks_len; i++) {
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS,
snapshot, gen7_snapshot_cx_dbgc_debugbus_block,
(void *) &gen7_cx_dbgc_debugbus_blocks[i]);
(void *) &gen7_snapshot_block_list->cx_debugbus_blocks[i]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS,
snapshot, gen7_snapshot_cx_side_dbgc_debugbus_block,
(void *) &gen7_cx_dbgc_debugbus_blocks[i]);
(void *) &gen7_snapshot_block_list->cx_debugbus_blocks[i]);
}
/*
* Get debugbus for GBIF CX part if GPU has GBIF block
* GBIF uses exactly same ID as of VBIF so use
* it as it is.
*/
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_DEBUGBUS, snapshot,
gen7_snapshot_cx_dbgc_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[0]);
kgsl_snapshot_add_section(device,
KGSL_SNAPSHOT_SECTION_SIDE_DEBUGBUS, snapshot,
gen7_snapshot_cx_side_dbgc_debugbus_block,
(void *) &gen7_gbif_debugbus_blocks[0]);
}
}
/* gen7_snapshot_sqe() - Dump SQE data in snapshot */
static size_t gen7_snapshot_sqe(struct kgsl_device *device, u8 *buf,
size_t remain, void *priv)
@ -1071,21 +1042,22 @@ static void gen7_reglist_snapshot(struct kgsl_device *device,
u64 *ptr, offset = 0;
int i;
u32 r;
struct reg_list *reg_list = gen7_snapshot_block_list->reg_list;
size_t (*func)(struct kgsl_device *device, u8 *buf, size_t remain,
void *priv) = gen7_legacy_snapshot_registers;
if (CD_SCRIPT_CHECK(device)) {
for (i = 0; i < ARRAY_SIZE(gen7_reg_list); i++)
for (i = 0; reg_list[i].regs; i++)
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, func, &gen7_reg_list[i]);
snapshot, func, &reg_list[i]);
return;
}
/* Build the crash script */
ptr = (u64 *)gen7_capturescript->hostptr;
for (i = 0; i < ARRAY_SIZE(gen7_reg_list); i++) {
struct reg_list *regs = &gen7_reg_list[i];
for (i = 0; reg_list[i].regs; i++) {
struct reg_list *regs = &reg_list[i];
const u32 *regs_ptr = regs->regs;
regs->offset = offset;
@ -1109,10 +1081,9 @@ static void gen7_reglist_snapshot(struct kgsl_device *device,
if (_gen7_do_crashdump(device))
func = gen7_snapshot_registers;
for (i = 0; i < ARRAY_SIZE(gen7_reg_list); i++)
for (i = 0; reg_list[i].regs; i++)
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, func, &gen7_reg_list[i]);
snapshot, func, &reg_list[i]);
}
static void gen7_snapshot_br_roq(struct kgsl_device *device,
@ -1172,6 +1143,22 @@ static void gen7_snapshot_lpac_roq(struct kgsl_device *device,
GEN7_CP_LPAC_ROQ_DBG_ADDR, GEN7_CP_LPAC_ROQ_DBG_DATA, 0, (roq_size << 2));
}
static void gen7_snapshot_external_core_regs(struct kgsl_device *device,
struct kgsl_snapshot *snapshot)
{
size_t i;
const u32 **external_core_regs = gen7_snapshot_block_list->external_core_regs;
unsigned int num_external_core_regs = gen7_snapshot_block_list->num_external_core_regs;
for (i = 0; i < num_external_core_regs; i++) {
const u32 *regs = external_core_regs[i];
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *) regs);
}
}
/*
* gen7_snapshot() - GEN7 GPU snapshot function
* @adreno_dev: Device being snapshotted
@ -1183,11 +1170,18 @@ static void gen7_snapshot_lpac_roq(struct kgsl_device *device,
void gen7_snapshot(struct adreno_device *adreno_dev,
struct kgsl_snapshot *snapshot)
{
const struct adreno_gen7_core *gpucore = to_gen7_core(adreno_dev);
struct kgsl_device *device = KGSL_DEVICE(adreno_dev);
struct cp_indexed_reg_list *cp_indexed_reglist;
struct adreno_ringbuffer *rb;
size_t cp_indexed_reglist_len;
unsigned int i;
u32 hi, lo, cgc = 0, cgc1 = 0, cgc2 = 0;
gen7_snapshot_block_list = gpucore->gen7_snapshot_block_list;
cp_indexed_reglist = gen7_snapshot_block_list->cp_indexed_reg_list;
cp_indexed_reglist_len = gen7_snapshot_block_list->cp_indexed_reg_list_len;
/*
* Dump debugbus data here to capture it for both
* GMU and GPU snapshot. Debugbus data can be accessed
@ -1214,23 +1208,10 @@ void gen7_snapshot(struct adreno_device *adreno_dev,
kgsl_regwrite(device, GEN7_RBBM_CLOCK_CNTL3_TP0, cgc2);
}
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_gpucc_registers);
if (adreno_is_gen7_3_0(adreno_dev))
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_3_0_cpr_registers);
else
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_cpr_registers);
if (!adreno_gx_is_on(adreno_dev)) {
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_cx_misc_registers);
(void *)gen7_0_0_cx_misc_registers);
return;
}
@ -1253,7 +1234,9 @@ void gen7_snapshot(struct adreno_device *adreno_dev,
/* Dump the registers which get affected by crash dumper trigger */
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_pre_crashdumper_registers);
(void *) gen7_snapshot_block_list->pre_crashdumper_regs);
gen7_snapshot_external_core_regs(device, snapshot);
gen7_reglist_snapshot(device, snapshot);
@ -1270,23 +1253,15 @@ void gen7_snapshot(struct adreno_device *adreno_dev,
if (device->ftbl->is_hwcg_on(device))
kgsl_regwrite(device, GEN7_RBBM_CLOCK_MODE_CP, cgc);
if (adreno_is_gen7_3_0(adreno_dev)) {
for (i = 0; i < ARRAY_SIZE(gen7_3_0_cp_indexed_reg_list); i++)
kgsl_snapshot_indexed_registers(device, snapshot,
gen7_3_0_cp_indexed_reg_list[i].addr,
gen7_3_0_cp_indexed_reg_list[i].data, 0,
gen7_3_0_cp_indexed_reg_list[i].size);
} else {
for (i = 0; i < cp_indexed_reglist_len; i++)
kgsl_snapshot_indexed_registers(device, snapshot,
cp_indexed_reglist[i].addr, cp_indexed_reglist[i].data, 0,
cp_indexed_reglist[i].size);
if (!adreno_is_gen7_3_0(adreno_dev)) {
kgsl_snapshot_indexed_registers(device, snapshot,
GEN7_CP_RESOURCE_TBL_DBG_ADDR, GEN7_CP_RESOURCE_TBL_DBG_DATA,
0, 0x4100);
for (i = 0; i < ARRAY_SIZE(gen7_cp_indexed_reg_list); i++)
kgsl_snapshot_indexed_registers(device, snapshot,
gen7_cp_indexed_reg_list[i].addr,
gen7_cp_indexed_reg_list[i].data, 0,
gen7_cp_indexed_reg_list[i].size);
gen7_snapshot_bv_roq(device, snapshot);
gen7_snapshot_lpac_roq(device, snapshot);
}
@ -1301,10 +1276,7 @@ void gen7_snapshot(struct adreno_device *adreno_dev,
gen7_snapshot_mempool(device, snapshot);
/* Shader memory */
if (adreno_is_gen7_3_0(adreno_dev))
gen7_3_0_snapshot_shader(device, snapshot);
else
gen7_snapshot_shader(device, snapshot);
gen7_snapshot_shader(device, snapshot);
/* MVC register section */
gen7_snapshot_mvc_regs(device, snapshot);
@ -1314,7 +1286,7 @@ void gen7_snapshot(struct adreno_device *adreno_dev,
kgsl_snapshot_add_section(device, KGSL_SNAPSHOT_SECTION_REGS_V2,
snapshot, adreno_snapshot_registers_v2,
(void *)gen7_post_crashdumper_registers);
(void *) gen7_snapshot_block_list->post_crashdumper_regs);
kgsl_regwrite(device, GEN7_RBBM_SNAPSHOT_STATUS, 0x0);

809
drivers/gpu/msm/adreno_gen7_snapshot.h
View File

@ -36,6 +36,7 @@ enum gen7_debugbus_ids {
DEBUGBUS_GBIF_CX = 6,
DEBUGBUS_HLSQ = 7,
DEBUGBUS_UCHE_0 = 9,
DEBUGBUS_UCHE_1 = 10,
DEBUGBUS_TESS_BR = 13,
DEBUGBUS_TESS_BV = 14,
DEBUGBUS_PC_BR = 17,
@ -66,11 +67,15 @@ enum gen7_debugbus_ids {
DEBUGBUS_RB_1 = 71,
DEBUGBUS_RB_2 = 72,
DEBUGBUS_RB_3 = 73,
DEBUGBUS_RB_4 = 74,
DEBUGBUS_RB_5 = 75,
DEBUGBUS_UCHE_WRAPPER = 102,
DEBUGBUS_CCU_0 = 106,
DEBUGBUS_CCU_1 = 107,
DEBUGBUS_CCU_2 = 108,
DEBUGBUS_CCU_3 = 109,
DEBUGBUS_CCU_4 = 110,
DEBUGBUS_CCU_5 = 111,
DEBUGBUS_VFD_BR_0 = 138,
DEBUGBUS_VFD_BR_1 = 139,
DEBUGBUS_VFD_BR_2 = 140,
@ -87,6 +92,8 @@ enum gen7_debugbus_ids {
DEBUGBUS_USP_1 = 235,
DEBUGBUS_USP_2 = 236,
DEBUGBUS_USP_3 = 237,
DEBUGBUS_USP_4 = 238,
DEBUGBUS_USP_5 = 239,
DEBUGBUS_TP_0 = 266,
DEBUGBUS_TP_1 = 267,
DEBUGBUS_TP_2 = 268,
@ -95,6 +102,10 @@ enum gen7_debugbus_ids {
DEBUGBUS_TP_5 = 271,
DEBUGBUS_TP_6 = 272,
DEBUGBUS_TP_7 = 273,
DEBUGBUS_TP_8 = 274,
DEBUGBUS_TP_9 = 275,
DEBUGBUS_TP_10 = 276,
DEBUGBUS_TP_11 = 277,
DEBUGBUS_USPTP_0 = 330,
DEBUGBUS_USPTP_1 = 331,
DEBUGBUS_USPTP_2 = 332,
@ -103,9 +114,16 @@ enum gen7_debugbus_ids {
DEBUGBUS_USPTP_5 = 335,
DEBUGBUS_USPTP_6 = 336,
DEBUGBUS_USPTP_7 = 337,
DEBUGBUS_USPTP_8 = 338,
DEBUGBUS_USPTP_9 = 339,
DEBUGBUS_USPTP_10 = 340,
DEBUGBUS_USPTP_11 = 341,
DEBUGBUS_CCHE_0 = 396,
DEBUGBUS_CCHE_1 = 397,
DEBUGBUS_CCHE_2 = 398,
};
static const u32 gen7_debugbus_blocks[] = {
static const u32 gen7_0_0_debugbus_blocks[] = {
DEBUGBUS_CP_0_0,
DEBUGBUS_CP_0_1,
DEBUGBUS_RBBM,
@ -241,6 +259,8 @@ enum gen7_statetype_ids {
SP_LB_6_DATA = 47,
SP_LB_7_DATA = 48,
SP_CB_RAM = 49,
SP_LB_13_DATA = 50,
SP_LB_14_DATA = 51,
SP_INST_TAG = 52,
SP_INST_DATA_2 = 53,
SP_TMO_TAG = 54,
@ -298,20 +318,20 @@ gen7_0_0_rb_rbp_sel = {
.val = 0x9,
};
static const u32 gen7_pre_crashdumper_registers[] = {
static const u32 gen7_0_0_pre_crashdumper_registers[] = {
0x00210, 0x00210, 0x00212, 0x00213, 0x03c00, 0x03c0b, 0x03c40, 0x03c42,
0x03c45, 0x03c47, 0x03c49, 0x03c4a, 0x03cc0, 0x03cd1,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_pre_crashdumper_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_pre_crashdumper_registers), 8));
static const u32 gen7_post_crashdumper_registers[] = {
static const u32 gen7_0_0_post_crashdumper_registers[] = {
0x00535, 0x00535,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_post_crashdumper_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_post_crashdumper_registers), 8));
static const u32 gen7_gpu_registers[] = {
static const u32 gen7_0_0_gpu_registers[] = {
0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b,
0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044,
0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050,
@ -340,15 +360,116 @@ static const u32 gen7_gpu_registers[] = {
0x00e1b, 0x00e2b, 0x00e30, 0x00e32, 0x00e38, 0x00e3c,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_gpu_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpu_registers), 8));
static const u32 gen7_cx_misc_registers[] = {
static const u32 gen7_0_0_cx_misc_registers[] = {
0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27832, 0x27857,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_cx_misc_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_cx_misc_registers), 8));
static const u32 gen7_cpr_registers[] = {
static const u32 gen7_0_0_gmu_registers[] = {
0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2,
0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f914, 0x1f920, 0x1f921,
0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f958, 0x1f95a,
0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f96b, 0x1f970, 0x1f979,
0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e,
0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa,
0x1fa00, 0x1fa03, 0x20000, 0x20005, 0x20008, 0x2000c, 0x20010, 0x20012,
0x20018, 0x20018, 0x20020, 0x20023, 0x20030, 0x20031, 0x23801, 0x23801,
0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809,
0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811,
0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819,
0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822,
0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a,
0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832,
0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a,
0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01,
0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16,
0x23b20, 0x23b20, 0x23b28, 0x23b28, 0x23b30, 0x23b30,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmu_registers), 8));
static const u32 gen7_3_0_gmu_registers[] = {
0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403,
0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03,
0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403,
0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03,
0x1f400, 0x1f40b, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507,
0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c,
0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c,
0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860,
0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2,
0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0,
0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f911, 0x1f920, 0x1f921,
0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940,
0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f980, 0x1f981, 0x1f984, 0x1f986,
0x1f992, 0x1f993, 0x1f996, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4,
0x1f9f1, 0x1f9f1, 0x1f9f8, 0x1f9fa, 0x1fa00, 0x1fa03, 0x20000, 0x20005,
0x20008, 0x20009, 0x20010, 0x20012, 0x20018, 0x20018, 0x20020, 0x20023,
0x20030, 0x20031, 0x23801, 0x23801, 0x23803, 0x23803, 0x23805, 0x23805,
0x23807, 0x23807, 0x23809, 0x23809, 0x2380b, 0x2380b, 0x2380d, 0x2380d,
0x2380f, 0x2380f, 0x23811, 0x23811, 0x23813, 0x23813, 0x23815, 0x23815,
0x23817, 0x23817, 0x23819, 0x23819, 0x2381b, 0x2381b, 0x2381d, 0x2381d,
0x2381f, 0x23820, 0x23822, 0x23822, 0x23824, 0x23824, 0x23826, 0x23826,
0x23828, 0x23828, 0x2382a, 0x2382a, 0x2382c, 0x2382c, 0x2382e, 0x2382e,
0x23830, 0x23830, 0x23832, 0x23832, 0x23834, 0x23834, 0x23836, 0x23836,
0x23838, 0x23838, 0x2383a, 0x2383a, 0x2383c, 0x2383c, 0x2383e, 0x2383e,
0x23840, 0x23847, 0x23b00, 0x23b01, 0x23b03, 0x23b03, 0x23b05, 0x23b0e,
0x23b10, 0x23b13, 0x23b15, 0x23b16, 0x23b20, 0x23b20, 0x23b28, 0x23b28,
0x23b30, 0x23b30,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_3_0_gmu_registers), 8));
static const u32 gen7_0_0_gmu_gx_registers[] = {
0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df,
0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df,
0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789, 0x1a78b, 0x1a78d,
0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799, 0x1a79b, 0x1a79b,
0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd,
0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd,
0x1a800, 0x1a802, 0x1a804, 0x1a804, 0x1a816, 0x1a816, 0x1a81e, 0x1a81e,
0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836, 0x1a83e, 0x1a83e,
0x1a846, 0x1a846, 0x1a860, 0x1a862, 0x1a864, 0x1a867, 0x1a870, 0x1a870,
0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2, 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3,
0x1a900, 0x1a92b, 0x1a940, 0x1a940,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmu_gx_registers), 8));
static const u32 gen7_3_0_gmu_gx_registers[] = {
0x1a802, 0x1a802, 0x1a883, 0x1a884, 0x1a900, 0x1a92b, 0x1a940, 0x1a940,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_3_0_gmu_gx_registers), 8));
static const u32 gen7_0_0_rscc_registers[] = {
0x14000, 0x14036, 0x14040, 0x14042, 0x14080, 0x14084, 0x14089, 0x1408c,
0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac,
0x14100, 0x14102, 0x14114, 0x14119, 0x14124, 0x1412e, 0x14140, 0x14143,
0x14180, 0x14197, 0x14340, 0x14342, 0x14344, 0x14347, 0x1434c, 0x14373,
0x143ec, 0x143ef, 0x143f4, 0x1441b, 0x14494, 0x14497, 0x1449c, 0x144c3,
0x1453c, 0x1453f, 0x14544, 0x1456b, 0x145e4, 0x145e7, 0x145ec, 0x14613,
0x1468c, 0x1468f, 0x14694, 0x146bb, 0x14734, 0x14737, 0x1473c, 0x14763,
0x147dc, 0x147df, 0x147e4, 0x1480b, 0x14884, 0x14887, 0x1488c, 0x148b3,
0x1492c, 0x1492f, 0x14934, 0x1495b, 0x14f51, 0x14f54,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_0_0_rscc_registers), 8));
static const u32 gen7_0_0_cpr_registers[] = {
0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c,
0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850,
0x26880, 0x26898, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee,
@ -356,7 +477,7 @@ static const u32 gen7_cpr_registers[] = {
0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274ac,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_cpr_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_cpr_registers), 8));
static const u32 gen7_3_0_cpr_registers[] = {
0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c,
@ -368,14 +489,14 @@ static const u32 gen7_3_0_cpr_registers[] = {
};
static_assert(IS_ALIGNED(sizeof(gen7_3_0_cpr_registers), 8));
static const u32 gen7_dpm_registers[] = {
static const u32 gen7_0_0_dpm_registers[] = {
0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12,
0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_dpm_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8));
static const u32 gen7_gpucc_registers[] = {
static const u32 gen7_0_0_gpucc_registers[] = {
0x24000, 0x2400e, 0x24400, 0x2440e, 0x24800, 0x24805, 0x24c00, 0x24cff,
0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, 0x26400, 0x26405,
0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26432, 0x26441, 0x26455,
@ -385,7 +506,7 @@ static const u32 gen7_gpucc_registers[] = {
0x26540, 0x26570, 0x26600, 0x26616, 0x26620, 0x2662d,
UINT_MAX, UINT_MAX,
};
static_assert(IS_ALIGNED(sizeof(gen7_gpucc_registers), 8));
static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpucc_registers), 8));
static const u32 gen7_0_0_noncontext_pipe_br_registers[] = {
0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b,
@ -829,7 +950,7 @@ struct gen7_cluster_registers {
unsigned int offset;
};
static struct gen7_cluster_registers gen7_clusters[] = {
static struct gen7_cluster_registers gen7_0_0_clusters[] = {
{ CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT,
gen7_0_0_noncontext_pipe_br_registers, },
{ CLUSTER_NONE, PIPE_BV, STATE_NON_CONTEXT,
@ -917,7 +1038,7 @@ struct gen7_sptp_cluster_registers {
unsigned int offset;
};
static struct gen7_sptp_cluster_registers gen7_sptp_clusters[] = {
static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = {
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, HLSQ_State,
gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 },
{ CLUSTER_NONE, SP_NCTX_REG, PIPE_BR, 0, SP_TOP,
@ -1023,10 +1144,10 @@ struct gen7_shader_block {
u32 statetype;
/* size: Size of the block (in dwords) */
u32 size
/* sp_id: The SP id to dump */;
u32 sp_id;
/* usptp: The usptp id to dump */;
u32 usptp;
/* num_sps: The number of SPs to dump */;
u32 num_sps;
/* num_usptps: The number of USPTPs to dump */;
u32 num_usptps;
/* pipe_id: Pipe identifier for the block data */
u32 pipeid;
/* location: Location identifer for the block data */
@ -1035,457 +1156,135 @@ struct gen7_shader_block {
u64 offset;
};
static struct gen7_shader_block gen7_shader_blocks[] = {
{TP0_TMO_DATA, 0x200, 0, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 0, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 0, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 0, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 0, 0, PIPE_BR, USPTP},
{SP_INST_DATA_2, 0x200, 0, 0, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 0, 0, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 0, 0, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 0, 0, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 0, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 0, 0, PIPE_BR, USPTP},
{SP_LB_8_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 0, 0, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_CPS_MISC_RAM_1, 0x200, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_INST_RAM_1, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_STPROC_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_DATAPATH_META, 0x20, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 0, 0, PIPE_LPAC, HLSQ_State},
{HLSQ_INDIRECT_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 0, 0, PIPE_BV, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 0, 0, PIPE_LPAC, HLSQ_State},
/* SP 0 USPTP 1 */
{TP0_TMO_DATA, 0x200, 0, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 0, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 0, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 0, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 0, 1, PIPE_BR, USPTP},
{SP_INST_DATA_2, 0x200, 0, 1, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 0, 1, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 0, 1, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 0, 1, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 0, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 0, 1, PIPE_BR, USPTP},
{SP_LB_8_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 0, 1, PIPE_BR, USPTP},
/* SP 1 USPTP 0 */
{TP0_TMO_DATA, 0x200, 1, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 1, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 1, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 1, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 1, 0, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 1, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 1, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 1, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 1, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 1, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 1, 0, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 1, 0, PIPE_BR, USPTP},
/* SP 1 USPTP 1 */
{TP0_TMO_DATA, 0x200, 1, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 1, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 1, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 1, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 1, 1, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 1, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 1, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 1, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 1, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 1, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 1, 1, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 1, 1, PIPE_BR, USPTP},
/* SP 2 USPTP 0 */
{TP0_TMO_DATA, 0x200, 2, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 2, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 2, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 2, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 2, 0, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 2, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 2, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 2, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 2, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 2, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 2, 0, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 2, 0, PIPE_BR, USPTP},
/* SP 2 USPTP 1 */
{TP0_TMO_DATA, 0x200, 2, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 2, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 2, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 2, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 2, 1, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 2, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 2, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 2, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 2, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 2, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 2, 1, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 2, 1, PIPE_BR, USPTP},
/* SP 3 USPTP 0 */
{TP0_TMO_DATA, 0x200, 3, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 3, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 3, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 3, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 3, 0, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 3, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 3, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 3, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 3, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 3, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 3, 0, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 3, 0, PIPE_BR, USPTP},
/* SP 3 USPTP 1 */
{TP0_TMO_DATA, 0x200, 3, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 3, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 3, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 3, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 3, 1, PIPE_BR, USPTP,},
{SP_INST_DATA_2, 0x200, 3, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 3, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 3, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 3, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 3, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 3, 1, PIPE_BR, USPTP,},
{SP_LB_8_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 3, 1, PIPE_BR, USPTP},
static struct gen7_shader_block gen7_0_0_shader_blocks[] = {
{TP0_TMO_DATA, 0x200, 4, 2, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 4, 2, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_6_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_7_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 4, 2, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 4, 2, PIPE_BR, USPTP},
{SP_INST_DATA_2, 0x200, 4, 2, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 4, 2, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 4, 2, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 4, 2, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 4, 2, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 4, 2, PIPE_BR, USPTP},
{SP_LB_8_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_9_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_10_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_11_DATA, 0x800, 4, 2, PIPE_BR, USPTP},
{SP_LB_12_DATA, 0x200, 4, 2, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_LPAC, HLSQ_State},
{HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BV, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_LPAC, HLSQ_State},
};
static struct gen7_shader_block gen7_3_0_shader_blocks[] = {
{TP0_TMO_DATA, 0x200, 0, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 0, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 0, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 0, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 0, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 0, 0, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 0, 0, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 0, 0, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 0, 0, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 0, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 0, 0, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_1, 0x200, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_1, 0x800, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_STPROC_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_DATAPATH_META, 0x20, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_INDIRECT_META, 0x10, 0, 0, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 0, 0, PIPE_BR, HLSQ_State},
/* SP 0 USPTP 1 */
{TP0_TMO_DATA, 0x200, 0, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 0, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 0, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 0, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 0, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 0, 1, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 0, 1, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 0, 1, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 0, 1, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 0, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 0, 1, PIPE_BR, USPTP},
/* SP 1 USPTP 0 */
{TP0_TMO_DATA, 0x200, 1, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 1, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 1, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 1, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 1, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 1, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 1, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 1, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 1, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 1, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 1, 0, PIPE_BR, USPTP,},
/* SP 1 USPTP 1 */
{TP0_TMO_DATA, 0x200, 1, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 1, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 1, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 1, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 1, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 1, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 1, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 1, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 1, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 1, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 1, 1, PIPE_BR, USPTP,},
/* SP 2 USPTP 0 */
{TP0_TMO_DATA, 0x200, 2, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 2, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 2, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 2, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 2, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 2, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 2, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 2, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 2, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 2, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 2, 0, PIPE_BR, USPTP,},
/* SP 2 USPTP 1 */
{TP0_TMO_DATA, 0x200, 2, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 2, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 2, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 2, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 2, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 2, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 2, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 2, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 2, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 2, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 2, 1, PIPE_BR, USPTP,},
/* SP 3 USPTP 0 */
{TP0_TMO_DATA, 0x200, 3, 0, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 3, 0, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 3, 0, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 3, 0, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 3, 0, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 3, 0, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 3, 0, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 3, 0, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 3, 0, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 3, 0, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 3, 0, PIPE_BR, USPTP,},
/* SP 3 USPTP 1 */
{TP0_TMO_DATA, 0x200, 3, 1, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 3, 1, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 3, 1, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 3, 1, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 3, 1, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 3, 1, PIPE_BR, USPTP,},
{SP_TMO_TAG, 0x80, 3, 1, PIPE_BR, USPTP,},
{SP_SMO_TAG, 0x80, 3, 1, PIPE_BR, USPTP,},
{SP_STATE_DATA, 0x40, 3, 1, PIPE_BR, USPTP,},
{SP_HWAVE_RAM, 0x100, 3, 1, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 3, 1, PIPE_BR, USPTP,},
{TP0_TMO_DATA, 0x200, 1, 2, PIPE_BR, USPTP},
{TP0_SMO_DATA, 0x80, 1, 2, PIPE_BR, USPTP},
{TP0_MIPMAP_BASE_DATA, 0x3c0, 1, 2, PIPE_BR, USPTP},
{SP_INST_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_INST_DATA_1, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_0_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_1_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_2_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_3_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_4_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_LB_5_DATA, 0x800, 1, 2, PIPE_BR, USPTP},
{SP_CB_RAM, 0x390, 1, 2, PIPE_BR, USPTP,},
{SP_INST_TAG, 0x90, 1, 2, PIPE_BR, USPTP},
{SP_TMO_TAG, 0x80, 1, 2, PIPE_BR, USPTP},
{SP_SMO_TAG, 0x80, 1, 2, PIPE_BR, USPTP},
{SP_STATE_DATA, 0x40, 1, 2, PIPE_BR, USPTP},
{SP_HWAVE_RAM, 0x100, 1, 2, PIPE_BR, USPTP},
{SP_L0_INST_BUF, 0x50, 1, 2, PIPE_BR, USPTP},
{HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM, 0x280, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_TAG, 0x80, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INST_RAM_1, 0x800, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_STPROC_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BV_BE_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_DATAPATH_META, 0x20, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_FRONTEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_INDIRECT_META, 0x10, 1, 1, PIPE_BR, HLSQ_State},
{HLSQ_BACKEND_META, 0x40, 1, 1, PIPE_BR, HLSQ_State},
};
static const u32 gen7_gbif_debugbus_blocks[] = {
@ -1496,10 +1295,13 @@ static const u32 gen7_gbif_debugbus_blocks[] = {
static const u32 gen7_cx_dbgc_debugbus_blocks[] = {
DEBUGBUS_GMU_CX,
DEBUGBUS_CX,
DEBUGBUS_GBIF_CX,
};
struct gen7_shader_block_info {
struct gen7_shader_block *block;
unsigned int sp_id;
unsigned int usptp;
u32 bank;
u64 offset;
};
@ -1508,10 +1310,11 @@ static struct reg_list {
const u32 *regs;
const struct sel_reg *sel;
u64 offset;
} gen7_reg_list[] = {
{ gen7_gpu_registers, NULL },
{ gen7_cx_misc_registers, NULL },
{ gen7_dpm_registers, NULL },
} gen7_0_0_reg_list[] = {
{ gen7_0_0_gpu_registers, NULL },
{ gen7_0_0_cx_misc_registers, NULL },
{ gen7_0_0_dpm_registers, NULL },
{ NULL, NULL },
};
struct cp_indexed_reg_list {
@ -1520,7 +1323,7 @@ struct cp_indexed_reg_list {
u32 size;
};
static struct cp_indexed_reg_list gen7_cp_indexed_reg_list[] = {
static struct cp_indexed_reg_list gen7_0_0_cp_indexed_reg_list[] = {
{ GEN7_CP_SQE_STAT_ADDR, GEN7_CP_SQE_STAT_DATA, 0x33},
{ GEN7_CP_DRAW_STATE_ADDR, GEN7_CP_DRAW_STATE_DATA, 0x100},
{ GEN7_CP_SQE_UCODE_DBG_ADDR, GEN7_CP_SQE_UCODE_DBG_DATA, 0x8000},
@ -1538,4 +1341,62 @@ static struct cp_indexed_reg_list gen7_3_0_cp_indexed_reg_list[] = {
{ GEN7_CP_DRAW_STATE_ADDR, GEN7_CP_DRAW_STATE_DATA, 0x100},
{ GEN7_CP_SQE_UCODE_DBG_ADDR, GEN7_CP_SQE_UCODE_DBG_DATA, 0x8000},
};
static const u32 *gen7_0_0_external_core_regs[] = {
gen7_0_0_gpucc_registers,
gen7_0_0_cpr_registers,
};
static const u32 *gen7_3_0_external_core_regs[] = {
gen7_0_0_gpucc_registers,
gen7_3_0_cpr_registers,
};
struct gen7_snapshot_block_list {
/* pre_crashdumper_regs : Registers which need to be dumped before CD runs */
const u32 *pre_crashdumper_regs;
/* cp_indexed_reg_list : List of cp_indexed registers */
struct cp_indexed_reg_list *cp_indexed_reg_list;
/* cp_indexed_reg_list_len : Length of the cp_indexed register list */
size_t cp_indexed_reg_list_len;
/* debugbus_blocks : List of debugbus blocks */
const u32 *debugbus_blocks;
/* debugbus_blocks_len : Length of the debugbus list */
size_t debugbus_blocks_len;
/* gbif_debugbus_blocks : List of GBIF debugbus blocks */
const u32 *gbif_debugbus_blocks;
/* gbif_debugbus_blocks_len : Length of GBIF debugbus list */
size_t gbif_debugbus_blocks_len;
/* cx_debugbus_blocks : List of CX debugbus blocks */
const u32 *cx_debugbus_blocks;
/* cx_debugbus_blocks_len : Length of the CX debugbus list */
size_t cx_debugbus_blocks_len;
/* external_core_regs : List of external core registers */
const u32 **external_core_regs;
/* num_external_core_regs : length of external core registers list */
size_t num_external_core_regs;
/* gmu_regs : List of GMU registers */
const u32 *gmu_regs;
/* gmu_gx_regs : List of GMU GX registers */
const u32 *gmu_gx_regs;
/* rscc_regs : List of RSCC registers */
const u32 *rscc_regs;
/* reg_list : List of GPU internal registers */
struct reg_list *reg_list;
/* shader_blocks : List of GPU shader memory */
struct gen7_shader_block *shader_blocks;
/* num_shader_blocks : Length of the shader memory list */
size_t num_shader_blocks;
/* cluster_registers : List of GPU cluster registers */
struct gen7_cluster_registers *clusters;
/* num_clusters : Length of GPU cluster registers list */
size_t num_clusters;
/* spstp_cluster_registers : List of GPU SPTP cluster registers */
struct gen7_sptp_cluster_registers *sptp_clusters;
/* num_sptp_clusters : Length of GPU SPTP cluster registers list */
size_t num_sptp_clusters;
/* post_crashdumper_regs : Registers which need to be dumped after CD runs */
const u32 *post_crashdumper_regs;
};
#endif /*_ADRENO_GEN7_SNAPSHOT_H */