arm-smmu-qcom: Export QCOM io-pagetables for adreno smmu

Do the groundwork for kgsl to be able to use QCOM io-pagetables
to make maps/unmaps faster.

Change-Id: Ib1b484e1e0ba21aaf8e9c0cac1c100cc981a6825
Signed-off-by: Harshdeep Dhatt <quic_hdhatt@quicinc.com>

drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/adreno-smmu-priv.h>
@@ -168,6 +169,8 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 		struct io_pgtable_cfg *pgtbl_cfg, struct device *dev)
 {
 	struct adreno_smmu_priv *priv;
+	struct qcom_io_pgtable_info *input_info =
+		container_of(pgtbl_cfg, struct qcom_io_pgtable_info, cfg);
 
 	/* Only enable split pagetables for the GPU device (SID 0) */
 	if (!qcom_adreno_smmu_is_gpu_device(dev))
@@ -190,6 +193,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain,
 	priv->cookie = smmu_domain;
 	priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg;
 	priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg;
+	priv->pgtbl_info = *input_info;
 
 	return 0;
 }

drivers/iommu/arm/arm-smmu/arm-smmu.c

@@ -51,8 +51,8 @@
 #include "arm-smmu.h"
 #include "../../iommu-logger.h"
 #include "../../qcom-dma-iommu-generic.h"
-#include "../../qcom-io-pgtable.h"
 #include <linux/qcom-iommu-util.h>
+#include <linux/qcom-io-pgtable.h>
 
 #define CREATE_TRACE_POINTS
 #include "arm-smmu-trace.h"

drivers/iommu/arm/arm-smmu/arm-smmu.h

@@ -23,8 +23,7 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 #include <linux/qcom-iommu-util.h>
-
-#include "../../qcom-io-pgtable.h"
+#include <linux/qcom-io-pgtable.h>
 
 /* Configuration registers */
 #define ARM_SMMU_GR0_sCR0		0x0

drivers/iommu/io-pgtable-fast.c

@@ -14,10 +14,10 @@
 #include <linux/io-pgtable.h>
 #include <linux/io-pgtable-fast.h>
 #include <linux/mm.h>
+#include <linux/qcom-io-pgtable.h>
 #include <asm/cacheflush.h>
 #include <linux/vmalloc.h>
 #include <linux/dma-mapping.h>
-#include "qcom-io-pgtable.h"
 
 #define AV8L_FAST_MAX_ADDR_BITS		48
 

drivers/iommu/iommu-logger.c

@@ -6,8 +6,8 @@
 #include <linux/bitfield.h>
 #include <linux/module.h>
 #include <linux/iommu.h>
+#include <linux/qcom-io-pgtable.h>
 #include <linux/slab.h>
-#include "qcom-io-pgtable.h"
 
 #include "iommu-logger.h"
 

drivers/iommu/qcom-io-pgtable-arm.c

@@ -17,9 +17,9 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/dma-mapping.h>
+#include <linux/qcom-io-pgtable.h>
 
 #include <asm/barrier.h>
-#include "qcom-io-pgtable.h"
 
 #include "io-pgtable-arm.h"
 

drivers/iommu/qcom-iommu-util.c

@@ -6,10 +6,9 @@
 #include <linux/module.h>
 #include <linux/slab.h>
 #include <linux/qcom-iommu-util.h>
+#include <linux/qcom-io-pgtable.h>
 #include <linux/dma-mapping-fast.h>
 #include "qcom-dma-iommu-generic.h"
-#include "qcom-io-pgtable.h"
-
 
 struct qcom_iommu_range_prop_cb_data {
 	int (*range_prop_entry_cb_fn)(const __be32 *p, int naddr, int nsize, void *arg);

include/linux/adreno-smmu-priv.h

@@ -7,6 +7,7 @@
 #define __ADRENO_SMMU_PRIV_H
 
 #include <linux/io-pgtable.h>
+#include <linux/qcom-io-pgtable.h>
 
 /**
  * struct adreno_smmu_priv - private interface between adreno-smmu and GPU
@@ -17,6 +18,7 @@
  * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank.  A
  *                 NULL config disables TTBR0 translation, otherwise
  *                 TTBR0 translation is enabled with the specified cfg
+ * @pgtbl_info:    io-pagetables info for the GPUs context-bank
  *
  * The GPU driver (drm/msm) and adreno-smmu work together for controlling
  * the GPU's SMMU instance.  This is by necessity, as the GPU is directly
@@ -28,9 +30,10 @@
  * it's domain.
  */
 struct adreno_smmu_priv {
-    const void *cookie;
-    const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
-    int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
+	const void *cookie;
+	const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie);
+	int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg);
+	struct qcom_io_pgtable_info pgtbl_info;
 };
 
-#endif /* __ADRENO_SMMU_PRIV_H */
+#endif /* __ADRENO_SMMU_PRIV_H */