Merge branch 'clk-mediatek' into clk-next
* clk-mediatek: clk: mediatek: add clock support for MT7622 SoC clk: mediatek: add clocks dt-bindings required header for MT7622 SoC clk: mediatek: add the option for determining PLL source clock dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC clk: mediatek: mark mtk_infrasys_init_early __init clk: mediatek: Add MT2712 clock support clk: mediatek: Add dt-bindings for MT2712 clocks dt-bindings: ARM: Mediatek: Document bindings for MT2712
This commit is contained in:
Stephen Boyd
commit
4c4fe16971
@ -7,7 +7,9 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-apmixedsys"
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- "mediatek,mt2712-apmixedsys", "syscon"
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- "mediatek,mt6797-apmixedsys"
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- "mediatek,mt7622-apmixedsys"
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- "mediatek,mt8135-apmixedsys"
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- "mediatek,mt8173-apmixedsys"
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- #clock-cells: Must be 1
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@ -0,0 +1,22 @@
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MediaTek AUDSYS controller
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============================
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The MediaTek AUDSYS controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt7622-audsys", "syscon"
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- #clock-cells: Must be 1
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The AUDSYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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audsys: audsys@11220000 {
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compatible = "mediatek,mt7622-audsys", "syscon";
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reg = <0 0x11220000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-bdpsys", "syscon"
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- "mediatek,mt2712-bdpsys", "syscon"
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- #clock-cells: Must be 1
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The bdpsys controller uses the common clk binding from
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-ethsys", "syscon"
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- "mediatek,mt7622-ethsys", "syscon"
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- #clock-cells: Must be 1
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The ethsys controller uses the common clk binding from
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@ -8,6 +8,7 @@ Required Properties:
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- compatible: Should be:
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- "mediatek,mt2701-hifsys", "syscon"
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- "mediatek,mt7622-hifsys", "syscon"
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- #clock-cells: Must be 1
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The hifsys controller uses the common clk binding from
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-imgsys", "syscon"
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- "mediatek,mt2712-imgsys", "syscon"
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- "mediatek,mt6797-imgsys", "syscon"
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- "mediatek,mt8173-imgsys", "syscon"
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- #clock-cells: Must be 1
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@ -8,7 +8,9 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-infracfg", "syscon"
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- "mediatek,mt2712-infracfg", "syscon"
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- "mediatek,mt6797-infracfg", "syscon"
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- "mediatek,mt7622-infracfg", "syscon"
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- "mediatek,mt8135-infracfg", "syscon"
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- "mediatek,mt8173-infracfg", "syscon"
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- #clock-cells: Must be 1
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@ -0,0 +1,22 @@
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Mediatek jpgdecsys controller
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============================
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The Mediatek jpgdecsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt2712-jpgdecsys", "syscon"
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- #clock-cells: Must be 1
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The jpgdecsys controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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jpgdecsys: syscon@19000000 {
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compatible = "mediatek,mt2712-jpgdecsys", "syscon";
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reg = <0 0x19000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,22 @@
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Mediatek mcucfg controller
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============================
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The Mediatek mcucfg controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mcucfg", "syscon"
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- #clock-cells: Must be 1
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The mcucfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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mcucfg: syscon@10220000 {
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compatible = "mediatek,mt2712-mcucfg", "syscon";
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reg = <0 0x10220000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,22 @@
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Mediatek mfgcfg controller
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============================
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The Mediatek mfgcfg controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-mfgcfg", "syscon"
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- #clock-cells: Must be 1
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The mfgcfg controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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mfgcfg: syscon@13000000 {
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compatible = "mediatek,mt2712-mfgcfg", "syscon";
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reg = <0 0x13000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-mmsys", "syscon"
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- "mediatek,mt2712-mmsys", "syscon"
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- "mediatek,mt6797-mmsys", "syscon"
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- "mediatek,mt8173-mmsys", "syscon"
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- #clock-cells: Must be 1
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@ -0,0 +1,22 @@
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MediaTek PCIESYS controller
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============================
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The MediaTek PCIESYS controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-pciesys", "syscon"
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- #clock-cells: Must be 1
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The PCIESYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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pciesys: pciesys@1a100800 {
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compatible = "mediatek,mt7622-pciesys", "syscon";
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reg = <0 0x1a100800 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -8,6 +8,8 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-pericfg", "syscon"
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- "mediatek,mt2712-pericfg", "syscon"
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- "mediatek,mt7622-pericfg", "syscon"
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- "mediatek,mt8135-pericfg", "syscon"
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- "mediatek,mt8173-pericfg", "syscon"
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- #clock-cells: Must be 1
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@ -0,0 +1,22 @@
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MediaTek SGMIISYS controller
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============================
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The MediaTek SGMIISYS controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-sgmiisys", "syscon"
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- #clock-cells: Must be 1
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The SGMIISYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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sgmiisys: sgmiisys@1b128000 {
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compatible = "mediatek,mt7622-sgmiisys", "syscon";
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reg = <0 0x1b128000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -0,0 +1,22 @@
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MediaTek SSUSBSYS controller
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============================
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The MediaTek SSUSBSYS controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be:
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- "mediatek,mt7622-ssusbsys", "syscon"
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- #clock-cells: Must be 1
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The SSUSBSYS controller uses the common clk binding from
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The available clocks are defined in dt-bindings/clock/mt*-clk.h.
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Example:
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ssusbsys: ssusbsys@1a000000 {
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compatible = "mediatek,mt7622-ssusbsys", "syscon";
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reg = <0 0x1a000000 0 0x1000>;
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#clock-cells = <1>;
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};
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@ -7,7 +7,9 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-topckgen"
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- "mediatek,mt2712-topckgen", "syscon"
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- "mediatek,mt6797-topckgen"
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- "mediatek,mt7622-topckgen"
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- "mediatek,mt8135-topckgen"
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- "mediatek,mt8173-topckgen"
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- #clock-cells: Must be 1
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@ -7,6 +7,7 @@ Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2701-vdecsys", "syscon"
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- "mediatek,mt2712-vdecsys", "syscon"
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- "mediatek,mt6797-vdecsys", "syscon"
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- "mediatek,mt8173-vdecsys", "syscon"
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- #clock-cells: Must be 1
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@ -6,6 +6,7 @@ The Mediatek vencsys controller provides various clocks to the system.
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Required Properties:
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- compatible: Should be one of:
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- "mediatek,mt2712-vencsys", "syscon"
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- "mediatek,mt6797-vencsys", "syscon"
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- "mediatek,mt8173-vencsys", "syscon"
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- #clock-cells: Must be 1
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@ -50,6 +50,56 @@ config COMMON_CLK_MT2701_BDPSYS
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---help---
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This driver supports Mediatek MT2701 bdpsys clocks.
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config COMMON_CLK_MT2712
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bool "Clock driver for Mediatek MT2712"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK && ARM64
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---help---
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This driver supports Mediatek MT2712 basic clocks.
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config COMMON_CLK_MT2712_BDPSYS
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bool "Clock driver for Mediatek MT2712 bdpsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 bdpsys clocks.
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config COMMON_CLK_MT2712_IMGSYS
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bool "Clock driver for Mediatek MT2712 imgsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 imgsys clocks.
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config COMMON_CLK_MT2712_JPGDECSYS
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bool "Clock driver for Mediatek MT2712 jpgdecsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 jpgdecsys clocks.
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config COMMON_CLK_MT2712_MFGCFG
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bool "Clock driver for Mediatek MT2712 mfgcfg"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 mfgcfg clocks.
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config COMMON_CLK_MT2712_MMSYS
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bool "Clock driver for Mediatek MT2712 mmsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 mmsys clocks.
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config COMMON_CLK_MT2712_VDECSYS
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bool "Clock driver for Mediatek MT2712 vdecsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 vdecsys clocks.
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config COMMON_CLK_MT2712_VENCSYS
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bool "Clock driver for Mediatek MT2712 vencsys"
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depends on COMMON_CLK_MT2712
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---help---
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This driver supports Mediatek MT2712 vencsys clocks.
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config COMMON_CLK_MT6797
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bool "Clock driver for Mediatek MT6797"
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depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
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@ -82,6 +132,36 @@ config COMMON_CLK_MT6797_VENCSYS
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---help---
|
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This driver supports Mediatek MT6797 vencsys clocks.
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config COMMON_CLK_MT7622
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bool "Clock driver for MediaTek MT7622"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
|
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---help---
|
||||
This driver supports MediaTek MT7622 basic clocks and clocks
|
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required for various periperals found on MediaTek.
|
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|
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config COMMON_CLK_MT7622_ETHSYS
|
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bool "Clock driver for MediaTek MT7622 ETHSYS"
|
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depends on COMMON_CLK_MT7622
|
||||
---help---
|
||||
This driver add support for clocks for Ethernet and SGMII
|
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required on MediaTek MT7622 SoC.
|
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|
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config COMMON_CLK_MT7622_HIFSYS
|
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bool "Clock driver for MediaTek MT7622 HIFSYS"
|
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depends on COMMON_CLK_MT7622
|
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---help---
|
||||
This driver supports MediaTek MT7622 HIFSYS clocks providing
|
||||
to PCI-E and USB.
|
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|
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config COMMON_CLK_MT7622_AUDSYS
|
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bool "Clock driver for MediaTek MT7622 AUDSYS"
|
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depends on COMMON_CLK_MT7622
|
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---help---
|
||||
This driver supports MediaTek MT7622 AUDSYS clocks providing
|
||||
to audio consumers such as I2S and TDM.
|
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|
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config COMMON_CLK_MT8135
|
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bool "Clock driver for Mediatek MT8135"
|
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depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
|
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|
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@ -12,5 +12,17 @@ obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
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obj-$(CONFIG_COMMON_CLK_MT2701_IMGSYS) += clk-mt2701-img.o
|
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obj-$(CONFIG_COMMON_CLK_MT2701_MMSYS) += clk-mt2701-mm.o
|
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obj-$(CONFIG_COMMON_CLK_MT2701_VDECSYS) += clk-mt2701-vdec.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_BDPSYS) += clk-mt2712-bdp.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_IMGSYS) += clk-mt2712-img.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_JPGDECSYS) += clk-mt2712-jpgdec.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_MFGCFG) += clk-mt2712-mfg.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_MMSYS) += clk-mt2712-mm.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_VDECSYS) += clk-mt2712-vdec.o
|
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obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
|
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obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622.o
|
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obj-$(CONFIG_COMMON_CLK_MT7622_ETHSYS) += clk-mt7622-eth.o
|
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obj-$(CONFIG_COMMON_CLK_MT7622_HIFSYS) += clk-mt7622-hif.o
|
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obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
|
||||
obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
|
||||
|
||||
@ -750,7 +750,7 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
|
||||
|
||||
static struct clk_onecell_data *infra_clk_data;
|
||||
|
||||
static void mtk_infrasys_init_early(struct device_node *node)
|
||||
static void __init mtk_infrasys_init_early(struct device_node *node)
|
||||
{
|
||||
int r, i;
|
||||
|
||||
|
||||
102
drivers/clk/mediatek/clk-mt2712-bdp.c
Normal file
102
drivers/clk/mediatek/clk-mt2712-bdp.c
Normal file
@ -0,0 +1,102 @@
|
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/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs bdp_cg_regs = {
|
||||
.set_ofs = 0x100,
|
||||
.clr_ofs = 0x100,
|
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.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
#define GATE_BDP(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &bdp_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate bdp_clks[] = {
|
||||
GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
|
||||
GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
|
||||
GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
|
||||
GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
|
||||
GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
|
||||
GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
|
||||
GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
|
||||
GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
|
||||
GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
|
||||
GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
|
||||
GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
|
||||
GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
|
||||
GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
|
||||
GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
|
||||
GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
|
||||
GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
|
||||
};
|
||||
|
||||
static int clk_mt2712_bdp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_bdp[] = {
|
||||
{ .compatible = "mediatek,mt2712-bdpsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_bdp_drv = {
|
||||
.probe = clk_mt2712_bdp_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-bdp",
|
||||
.of_match_table = of_match_clk_mt2712_bdp,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_bdp_drv);
|
||||
80
drivers/clk/mediatek/clk-mt2712-img.c
Normal file
80
drivers/clk/mediatek/clk-mt2712-img.c
Normal file
@ -0,0 +1,80 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs img_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_IMG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &img_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate img_clks[] = {
|
||||
GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
|
||||
GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
|
||||
GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
|
||||
GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
|
||||
GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
|
||||
GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
|
||||
};
|
||||
|
||||
static int clk_mt2712_img_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_img[] = {
|
||||
{ .compatible = "mediatek,mt2712-imgsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_img_drv = {
|
||||
.probe = clk_mt2712_img_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-img",
|
||||
.of_match_table = of_match_clk_mt2712_img,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_img_drv);
|
||||
76
drivers/clk/mediatek/clk-mt2712-jpgdec.c
Normal file
76
drivers/clk/mediatek/clk-mt2712-jpgdec.c
Normal file
@ -0,0 +1,76 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs jpgdec_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_JPGDEC(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &jpgdec_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate jpgdec_clks[] = {
|
||||
GATE_JPGDEC(CLK_JPGDEC_JPGDEC1, "jpgdec_jpgdec1", "jpgdec_sel", 0),
|
||||
GATE_JPGDEC(CLK_JPGDEC_JPGDEC, "jpgdec_jpgdec", "jpgdec_sel", 4),
|
||||
};
|
||||
|
||||
static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_jpgdec[] = {
|
||||
{ .compatible = "mediatek,mt2712-jpgdecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_jpgdec_drv = {
|
||||
.probe = clk_mt2712_jpgdec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-jpgdec",
|
||||
.of_match_table = of_match_clk_mt2712_jpgdec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_jpgdec_drv);
|
||||
75
drivers/clk/mediatek/clk-mt2712-mfg.c
Normal file
75
drivers/clk/mediatek/clk-mt2712-mfg.c
Normal file
@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mfg_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_MFG(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mfg_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mfg_clks[] = {
|
||||
GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
|
||||
};
|
||||
|
||||
static int clk_mt2712_mfg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_mfg[] = {
|
||||
{ .compatible = "mediatek,mt2712-mfgcfg", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_mfg_drv = {
|
||||
.probe = clk_mt2712_mfg_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mfg",
|
||||
.of_match_table = of_match_clk_mt2712_mfg,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_mfg_drv);
|
||||
170
drivers/clk/mediatek/clk-mt2712-mm.c
Normal file
170
drivers/clk/mediatek/clk-mt2712-mm.c
Normal file
@ -0,0 +1,170 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs mm0_cg_regs = {
|
||||
.set_ofs = 0x104,
|
||||
.clr_ofs = 0x108,
|
||||
.sta_ofs = 0x100,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm1_cg_regs = {
|
||||
.set_ofs = 0x114,
|
||||
.clr_ofs = 0x118,
|
||||
.sta_ofs = 0x110,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs mm2_cg_regs = {
|
||||
.set_ofs = 0x224,
|
||||
.clr_ofs = 0x228,
|
||||
.sta_ofs = 0x220,
|
||||
};
|
||||
|
||||
#define GATE_MM0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_MM1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_MM2(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &mm2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate mm_clks[] = {
|
||||
/* MM0 */
|
||||
GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
|
||||
GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
|
||||
GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
|
||||
GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
|
||||
GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
|
||||
GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
|
||||
GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
|
||||
GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
|
||||
GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
|
||||
GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
|
||||
GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
|
||||
GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
|
||||
GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
|
||||
GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
|
||||
GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
|
||||
GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
|
||||
GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
|
||||
GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
|
||||
GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
|
||||
GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
|
||||
GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
|
||||
GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
|
||||
/* MM1 */
|
||||
GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
|
||||
GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
|
||||
GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
|
||||
GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
|
||||
GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
|
||||
GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
|
||||
GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
|
||||
GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
|
||||
GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
|
||||
GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
|
||||
GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
|
||||
GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
|
||||
GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
|
||||
GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
|
||||
GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
|
||||
GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
|
||||
GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
|
||||
GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
|
||||
GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
|
||||
GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
|
||||
GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
|
||||
GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
|
||||
GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
|
||||
GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
|
||||
GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
|
||||
GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
|
||||
/* MM2 */
|
||||
GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
|
||||
GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
|
||||
GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
|
||||
GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
|
||||
GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
|
||||
GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
|
||||
GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
|
||||
};
|
||||
|
||||
static int clk_mt2712_mm_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_mm[] = {
|
||||
{ .compatible = "mediatek,mt2712-mmsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_mm_drv = {
|
||||
.probe = clk_mt2712_mm_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-mm",
|
||||
.of_match_table = of_match_clk_mt2712_mm,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_mm_drv);
|
||||
94
drivers/clk/mediatek/clk-mt2712-vdec.c
Normal file
94
drivers/clk/mediatek/clk-mt2712-vdec.c
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs vdec0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x4,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs vdec1_cg_regs = {
|
||||
.set_ofs = 0x8,
|
||||
.clr_ofs = 0xc,
|
||||
.sta_ofs = 0x8,
|
||||
};
|
||||
|
||||
#define GATE_VDEC0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_VDEC1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &vdec1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate vdec_clks[] = {
|
||||
/* VDEC0 */
|
||||
GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
|
||||
/* VDEC1 */
|
||||
GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
|
||||
GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
|
||||
};
|
||||
|
||||
static int clk_mt2712_vdec_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_vdec[] = {
|
||||
{ .compatible = "mediatek,mt2712-vdecsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_vdec_drv = {
|
||||
.probe = clk_mt2712_vdec_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-vdec",
|
||||
.of_match_table = of_match_clk_mt2712_vdec,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_vdec_drv);
|
||||
77
drivers/clk/mediatek/clk-mt2712-venc.c
Normal file
77
drivers/clk/mediatek/clk-mt2712-venc.c
Normal file
@ -0,0 +1,77 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
|
||||
static const struct mtk_gate_regs venc_cg_regs = {
|
||||
.set_ofs = 0x4,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
#define GATE_VENC(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &venc_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate venc_clks[] = {
|
||||
GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
|
||||
GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
|
||||
GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
|
||||
};
|
||||
|
||||
static int clk_mt2712_venc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
|
||||
if (r != 0)
|
||||
pr_err("%s(): could not register clock provider: %d\n",
|
||||
__func__, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt2712_venc[] = {
|
||||
{ .compatible = "mediatek,mt2712-vencsys", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver clk_mt2712_venc_drv = {
|
||||
.probe = clk_mt2712_venc_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt2712-venc",
|
||||
.of_match_table = of_match_clk_mt2712_venc,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt2712_venc_drv);
|
||||
1435
drivers/clk/mediatek/clk-mt2712.c
Normal file
1435
drivers/clk/mediatek/clk-mt2712.c
Normal file
File diff suppressed because it is too large
Load Diff
195
drivers/clk/mediatek/clk-mt7622-aud.c
Normal file
195
drivers/clk/mediatek/clk-mt7622-aud.c
Normal file
@ -0,0 +1,195 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Chen Zhong <chen.zhong@mediatek.com>
|
||||
* Sean Wang <sean.wang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
|
||||
#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio2_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &audio3_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate_regs audio0_cg_regs = {
|
||||
.set_ofs = 0x0,
|
||||
.clr_ofs = 0x0,
|
||||
.sta_ofs = 0x0,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs audio1_cg_regs = {
|
||||
.set_ofs = 0x10,
|
||||
.clr_ofs = 0x10,
|
||||
.sta_ofs = 0x10,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs audio2_cg_regs = {
|
||||
.set_ofs = 0x14,
|
||||
.clr_ofs = 0x14,
|
||||
.sta_ofs = 0x14,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs audio3_cg_regs = {
|
||||
.set_ofs = 0x634,
|
||||
.clr_ofs = 0x634,
|
||||
.sta_ofs = 0x634,
|
||||
};
|
||||
|
||||
static const struct mtk_gate audio_clks[] = {
|
||||
/* AUDIO0 */
|
||||
GATE_AUDIO0(CLK_AUDIO_AFE, "audio_afe", "rtc", 2),
|
||||
GATE_AUDIO0(CLK_AUDIO_HDMI, "audio_hdmi", "apll1_ck_sel", 20),
|
||||
GATE_AUDIO0(CLK_AUDIO_SPDF, "audio_spdf", "apll1_ck_sel", 21),
|
||||
GATE_AUDIO0(CLK_AUDIO_APLL, "audio_apll", "apll1_ck_sel", 23),
|
||||
/* AUDIO1 */
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SIN1, "audio_i2sin1", "a1sys_hp_sel", 0),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SIN2, "audio_i2sin2", "a1sys_hp_sel", 1),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SIN3, "audio_i2sin3", "a1sys_hp_sel", 2),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SIN4, "audio_i2sin4", "a1sys_hp_sel", 3),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SO1, "audio_i2so1", "a1sys_hp_sel", 6),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SO2, "audio_i2so2", "a1sys_hp_sel", 7),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SO3, "audio_i2so3", "a1sys_hp_sel", 8),
|
||||
GATE_AUDIO1(CLK_AUDIO_I2SO4, "audio_i2so4", "a1sys_hp_sel", 9),
|
||||
GATE_AUDIO1(CLK_AUDIO_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
|
||||
GATE_AUDIO1(CLK_AUDIO_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
|
||||
GATE_AUDIO1(CLK_AUDIO_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
|
||||
GATE_AUDIO1(CLK_AUDIO_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
|
||||
GATE_AUDIO1(CLK_AUDIO_INTDIR, "audio_intdir", "intdir_sel", 20),
|
||||
GATE_AUDIO1(CLK_AUDIO_A1SYS, "audio_a1sys", "a1sys_hp_sel", 21),
|
||||
GATE_AUDIO1(CLK_AUDIO_A2SYS, "audio_a2sys", "a2sys_hp_sel", 22),
|
||||
/* AUDIO2 */
|
||||
GATE_AUDIO2(CLK_AUDIO_UL1, "audio_ul1", "a1sys_hp_sel", 0),
|
||||
GATE_AUDIO2(CLK_AUDIO_UL2, "audio_ul2", "a1sys_hp_sel", 1),
|
||||
GATE_AUDIO2(CLK_AUDIO_UL3, "audio_ul3", "a1sys_hp_sel", 2),
|
||||
GATE_AUDIO2(CLK_AUDIO_UL4, "audio_ul4", "a1sys_hp_sel", 3),
|
||||
GATE_AUDIO2(CLK_AUDIO_UL5, "audio_ul5", "a1sys_hp_sel", 4),
|
||||
GATE_AUDIO2(CLK_AUDIO_UL6, "audio_ul6", "a1sys_hp_sel", 5),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL1, "audio_dl1", "a1sys_hp_sel", 6),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL2, "audio_dl2", "a1sys_hp_sel", 7),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL3, "audio_dl3", "a1sys_hp_sel", 8),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL4, "audio_dl4", "a1sys_hp_sel", 9),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL5, "audio_dl5", "a1sys_hp_sel", 10),
|
||||
GATE_AUDIO2(CLK_AUDIO_DL6, "audio_dl6", "a1sys_hp_sel", 11),
|
||||
GATE_AUDIO2(CLK_AUDIO_DLMCH, "audio_dlmch", "a1sys_hp_sel", 12),
|
||||
GATE_AUDIO2(CLK_AUDIO_ARB1, "audio_arb1", "a1sys_hp_sel", 13),
|
||||
GATE_AUDIO2(CLK_AUDIO_AWB, "audio_awb", "a1sys_hp_sel", 14),
|
||||
GATE_AUDIO2(CLK_AUDIO_AWB2, "audio_awb2", "a1sys_hp_sel", 15),
|
||||
GATE_AUDIO2(CLK_AUDIO_DAI, "audio_dai", "a1sys_hp_sel", 16),
|
||||
GATE_AUDIO2(CLK_AUDIO_MOD, "audio_mod", "a1sys_hp_sel", 17),
|
||||
/* AUDIO3 */
|
||||
GATE_AUDIO3(CLK_AUDIO_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
|
||||
GATE_AUDIO3(CLK_AUDIO_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
|
||||
GATE_AUDIO3(CLK_AUDIO_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
|
||||
GATE_AUDIO3(CLK_AUDIO_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
|
||||
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
|
||||
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
|
||||
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
|
||||
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
|
||||
GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
|
||||
};
|
||||
|
||||
static int clk_mt7622_audiosys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7622_aud[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt7622-audsys",
|
||||
.data = clk_mt7622_audiosys_init,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int clk_mt7622_aud_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*clk_init)(struct platform_device *);
|
||||
int r;
|
||||
|
||||
clk_init = of_device_get_match_data(&pdev->dev);
|
||||
if (!clk_init)
|
||||
return -EINVAL;
|
||||
|
||||
r = clk_init(pdev);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt7622_aud_drv = {
|
||||
.probe = clk_mt7622_aud_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt7622-aud",
|
||||
.of_match_table = of_match_clk_mt7622_aud,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt7622_aud_drv);
|
||||
156
drivers/clk/mediatek/clk-mt7622-eth.c
Normal file
156
drivers/clk/mediatek/clk-mt7622-eth.c
Normal file
@ -0,0 +1,156 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Chen Zhong <chen.zhong@mediatek.com>
|
||||
* Sean Wang <sean.wang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
|
||||
#define GATE_ETH(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = ð_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate_regs eth_cg_regs = {
|
||||
.set_ofs = 0x30,
|
||||
.clr_ofs = 0x30,
|
||||
.sta_ofs = 0x30,
|
||||
};
|
||||
|
||||
static const struct mtk_gate eth_clks[] = {
|
||||
GATE_ETH(CLK_ETH_HSDMA_EN, "eth_hsdma_en", "eth_sel", 5),
|
||||
GATE_ETH(CLK_ETH_ESW_EN, "eth_esw_en", "eth_500m", 6),
|
||||
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "txclk_src_pre", 7),
|
||||
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "txclk_src_pre", 8),
|
||||
GATE_ETH(CLK_ETH_GP0_EN, "eth_gp0_en", "txclk_src_pre", 9),
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs sgmii_cg_regs = {
|
||||
.set_ofs = 0xE4,
|
||||
.clr_ofs = 0xE4,
|
||||
.sta_ofs = 0xE4,
|
||||
};
|
||||
|
||||
#define GATE_SGMII(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &sgmii_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate sgmii_clks[] = {
|
||||
GATE_SGMII(CLK_SGMII_TX250M_EN, "sgmii_tx250m_en",
|
||||
"ssusb_tx250m", 2),
|
||||
GATE_SGMII(CLK_SGMII_RX250M_EN, "sgmii_rx250m_en",
|
||||
"ssusb_eq_rx250m", 3),
|
||||
GATE_SGMII(CLK_SGMII_CDR_REF, "sgmii_cdr_ref",
|
||||
"ssusb_cdr_ref", 4),
|
||||
GATE_SGMII(CLK_SGMII_CDR_FB, "sgmii_cdr_fb",
|
||||
"ssusb_cdr_fb", 5),
|
||||
};
|
||||
|
||||
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7622_eth[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt7622-ethsys",
|
||||
.data = clk_mt7622_ethsys_init,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-sgmiisys",
|
||||
.data = clk_mt7622_sgmiisys_init,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int clk_mt7622_eth_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*clk_init)(struct platform_device *);
|
||||
int r;
|
||||
|
||||
clk_init = of_device_get_match_data(&pdev->dev);
|
||||
if (!clk_init)
|
||||
return -EINVAL;
|
||||
|
||||
r = clk_init(pdev);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt7622_eth_drv = {
|
||||
.probe = clk_mt7622_eth_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt7622-eth",
|
||||
.of_match_table = of_match_clk_mt7622_eth,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt7622_eth_drv);
|
||||
169
drivers/clk/mediatek/clk-mt7622-hif.c
Normal file
169
drivers/clk/mediatek/clk-mt7622-hif.c
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Chen Zhong <chen.zhong@mediatek.com>
|
||||
* Sean Wang <sean.wang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
|
||||
#define GATE_PCIE(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &pcie_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_SSUSB(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &ssusb_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
static const struct mtk_gate_regs pcie_cg_regs = {
|
||||
.set_ofs = 0x30,
|
||||
.clr_ofs = 0x30,
|
||||
.sta_ofs = 0x30,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs ssusb_cg_regs = {
|
||||
.set_ofs = 0x30,
|
||||
.clr_ofs = 0x30,
|
||||
.sta_ofs = 0x30,
|
||||
};
|
||||
|
||||
static const struct mtk_gate ssusb_clks[] = {
|
||||
GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
|
||||
"to_u2_phy_1p", 0),
|
||||
GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
|
||||
GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
|
||||
GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
|
||||
GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "axi_sel", 7),
|
||||
GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "hif_sel", 8),
|
||||
};
|
||||
|
||||
static const struct mtk_gate pcie_clks[] = {
|
||||
GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
|
||||
GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
|
||||
GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "axi_sel", 14),
|
||||
GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "hif_sel", 15),
|
||||
GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
|
||||
GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
|
||||
GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
|
||||
GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
|
||||
GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "axi_sel", 20),
|
||||
GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "hif_sel", 21),
|
||||
GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
|
||||
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
|
||||
GATE_PCIE(CLK_SATA_AHB_EN, "sata_ahb_en", "axi_sel", 26),
|
||||
GATE_PCIE(CLK_SATA_AXI_EN, "sata_axi_en", "hif_sel", 27),
|
||||
GATE_PCIE(CLK_SATA_ASIC_EN, "sata_asic_en", "sata_asic", 28),
|
||||
GATE_PCIE(CLK_SATA_RBC_EN, "sata_rbc_en", "sata_rbc", 29),
|
||||
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
|
||||
};
|
||||
|
||||
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static int clk_mt7622_pciesys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x34);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7622_hif[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt7622-pciesys",
|
||||
.data = clk_mt7622_pciesys_init,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-ssusbsys",
|
||||
.data = clk_mt7622_ssusbsys_init,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int clk_mt7622_hif_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*clk_init)(struct platform_device *);
|
||||
int r;
|
||||
|
||||
clk_init = of_device_get_match_data(&pdev->dev);
|
||||
if (!clk_init)
|
||||
return -EINVAL;
|
||||
|
||||
r = clk_init(pdev);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt7622_hif_drv = {
|
||||
.probe = clk_mt7622_hif_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt7622-hif",
|
||||
.of_match_table = of_match_clk_mt7622_hif,
|
||||
},
|
||||
};
|
||||
|
||||
builtin_platform_driver(clk_mt7622_hif_drv);
|
||||
780
drivers/clk/mediatek/clk-mt7622.c
Normal file
780
drivers/clk/mediatek/clk-mt7622.c
Normal file
@ -0,0 +1,780 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Chen Zhong <chen.zhong@mediatek.com>
|
||||
* Sean Wang <sean.wang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include "clk-mtk.h"
|
||||
#include "clk-gate.h"
|
||||
#include "clk-cpumux.h"
|
||||
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
#include <linux/clk.h> /* for consumer */
|
||||
|
||||
#define MT7622_PLL_FMAX (2500UL * MHZ)
|
||||
#define CON0_MT7622_RST_BAR BIT(27)
|
||||
|
||||
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
|
||||
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
|
||||
_pcw_shift, _div_table, _parent_name) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.reg = _reg, \
|
||||
.pwr_reg = _pwr_reg, \
|
||||
.en_mask = _en_mask, \
|
||||
.flags = _flags, \
|
||||
.rst_bar_mask = CON0_MT7622_RST_BAR, \
|
||||
.fmax = MT7622_PLL_FMAX, \
|
||||
.pcwbits = _pcwbits, \
|
||||
.pd_reg = _pd_reg, \
|
||||
.pd_shift = _pd_shift, \
|
||||
.tuner_reg = _tuner_reg, \
|
||||
.pcw_reg = _pcw_reg, \
|
||||
.pcw_shift = _pcw_shift, \
|
||||
.div_table = _div_table, \
|
||||
.parent_name = _parent_name, \
|
||||
}
|
||||
|
||||
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
|
||||
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
|
||||
_pcw_shift) \
|
||||
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,\
|
||||
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
|
||||
NULL, "clkxtal")
|
||||
|
||||
#define GATE_APMIXED(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &apmixed_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
|
||||
}
|
||||
|
||||
#define GATE_INFRA(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &infra_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_TOP0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &top0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_TOP1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &top1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_no_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_PERI0(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &peri0_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
#define GATE_PERI1(_id, _name, _parent, _shift) { \
|
||||
.id = _id, \
|
||||
.name = _name, \
|
||||
.parent_name = _parent, \
|
||||
.regs = &peri1_cg_regs, \
|
||||
.shift = _shift, \
|
||||
.ops = &mtk_clk_gate_ops_setclr, \
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(mt7622_clk_lock);
|
||||
|
||||
static const char * const infra_mux1_parents[] = {
|
||||
"clkxtal",
|
||||
"armpll",
|
||||
"main_core_en",
|
||||
"armpll"
|
||||
};
|
||||
|
||||
static const char * const axi_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll1_d2",
|
||||
"syspll_d5",
|
||||
"syspll1_d4",
|
||||
"univpll_d5",
|
||||
"univpll2_d2",
|
||||
"univpll_d7"
|
||||
};
|
||||
|
||||
static const char * const mem_parents[] = {
|
||||
"clkxtal",
|
||||
"dmpll_ck"
|
||||
};
|
||||
|
||||
static const char * const ddrphycfg_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll1_d8"
|
||||
};
|
||||
|
||||
static const char * const eth_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll1_d2",
|
||||
"univpll1_d2",
|
||||
"syspll1_d4",
|
||||
"univpll_d5",
|
||||
"clk_null",
|
||||
"univpll_d7"
|
||||
};
|
||||
|
||||
static const char * const pwm_parents[] = {
|
||||
"clkxtal",
|
||||
"univpll2_d4"
|
||||
};
|
||||
|
||||
static const char * const f10m_ref_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll4_d16"
|
||||
};
|
||||
|
||||
static const char * const nfi_infra_parents[] = {
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"clkxtal",
|
||||
"univpll2_d8",
|
||||
"syspll1_d8",
|
||||
"univpll1_d8",
|
||||
"syspll4_d2",
|
||||
"univpll2_d4",
|
||||
"univpll3_d2",
|
||||
"syspll1_d4"
|
||||
};
|
||||
|
||||
static const char * const flash_parents[] = {
|
||||
"clkxtal",
|
||||
"univpll_d80_d4",
|
||||
"syspll2_d8",
|
||||
"syspll3_d4",
|
||||
"univpll3_d4",
|
||||
"univpll1_d8",
|
||||
"syspll2_d4",
|
||||
"univpll2_d4"
|
||||
};
|
||||
|
||||
static const char * const uart_parents[] = {
|
||||
"clkxtal",
|
||||
"univpll2_d8"
|
||||
};
|
||||
|
||||
static const char * const spi0_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll3_d2",
|
||||
"clkxtal",
|
||||
"syspll2_d4",
|
||||
"syspll4_d2",
|
||||
"univpll2_d4",
|
||||
"univpll1_d8",
|
||||
"clkxtal"
|
||||
};
|
||||
|
||||
static const char * const spi1_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll3_d2",
|
||||
"clkxtal",
|
||||
"syspll4_d4",
|
||||
"syspll4_d2",
|
||||
"univpll2_d4",
|
||||
"univpll1_d8",
|
||||
"clkxtal"
|
||||
};
|
||||
|
||||
static const char * const msdc30_0_parents[] = {
|
||||
"clkxtal",
|
||||
"univpll2_d16",
|
||||
"univ48m"
|
||||
};
|
||||
|
||||
static const char * const a1sys_hp_parents[] = {
|
||||
"clkxtal",
|
||||
"aud1pll_ck",
|
||||
"aud2pll_ck",
|
||||
"clkxtal"
|
||||
};
|
||||
|
||||
static const char * const intdir_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll_d2",
|
||||
"univpll_d2",
|
||||
"sgmiipll_ck"
|
||||
};
|
||||
|
||||
static const char * const aud_intbus_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll1_d4",
|
||||
"syspll4_d2",
|
||||
"syspll3_d2"
|
||||
};
|
||||
|
||||
static const char * const pmicspi_parents[] = {
|
||||
"clkxtal",
|
||||
"clk_null",
|
||||
"clk_null",
|
||||
"clk_null",
|
||||
"clk_null",
|
||||
"univpll2_d16"
|
||||
};
|
||||
|
||||
static const char * const atb_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll1_d2",
|
||||
"syspll_d5"
|
||||
};
|
||||
|
||||
static const char * const audio_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll3_d4",
|
||||
"syspll4_d4",
|
||||
"univpll1_d16"
|
||||
};
|
||||
|
||||
static const char * const usb20_parents[] = {
|
||||
"clkxtal",
|
||||
"univpll3_d4",
|
||||
"syspll1_d8",
|
||||
"clkxtal"
|
||||
};
|
||||
|
||||
static const char * const aud1_parents[] = {
|
||||
"clkxtal",
|
||||
"aud1pll_ck"
|
||||
};
|
||||
|
||||
static const char * const aud2_parents[] = {
|
||||
"clkxtal",
|
||||
"aud2pll_ck"
|
||||
};
|
||||
|
||||
static const char * const asm_l_parents[] = {
|
||||
"clkxtal",
|
||||
"syspll_d5",
|
||||
"univpll2_d2",
|
||||
"univpll2_d4"
|
||||
};
|
||||
|
||||
static const char * const apll1_ck_parents[] = {
|
||||
"aud1_sel",
|
||||
"aud2_sel"
|
||||
};
|
||||
|
||||
static const char * const peribus_ck_parents[] = {
|
||||
"syspll1_d8",
|
||||
"syspll1_d4"
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs apmixed_cg_regs = {
|
||||
.set_ofs = 0x8,
|
||||
.clr_ofs = 0x8,
|
||||
.sta_ofs = 0x8,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs infra_cg_regs = {
|
||||
.set_ofs = 0x40,
|
||||
.clr_ofs = 0x44,
|
||||
.sta_ofs = 0x48,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top0_cg_regs = {
|
||||
.set_ofs = 0x120,
|
||||
.clr_ofs = 0x120,
|
||||
.sta_ofs = 0x120,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs top1_cg_regs = {
|
||||
.set_ofs = 0x128,
|
||||
.clr_ofs = 0x128,
|
||||
.sta_ofs = 0x128,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs peri0_cg_regs = {
|
||||
.set_ofs = 0x8,
|
||||
.clr_ofs = 0x10,
|
||||
.sta_ofs = 0x18,
|
||||
};
|
||||
|
||||
static const struct mtk_gate_regs peri1_cg_regs = {
|
||||
.set_ofs = 0xC,
|
||||
.clr_ofs = 0x14,
|
||||
.sta_ofs = 0x1C,
|
||||
};
|
||||
|
||||
static const struct mtk_pll_data plls[] = {
|
||||
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001,
|
||||
PLL_AO, 21, 0x0204, 24, 0, 0x0204, 0),
|
||||
PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0210, 0x021C, 0x00000001,
|
||||
HAVE_RST_BAR, 21, 0x0214, 24, 0, 0x0214, 0),
|
||||
PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0220, 0x022C, 0x00000001,
|
||||
HAVE_RST_BAR, 7, 0x0224, 24, 0, 0x0224, 14),
|
||||
PLL(CLK_APMIXED_ETH1PLL, "eth1pll", 0x0300, 0x0310, 0x00000001,
|
||||
0, 21, 0x0300, 1, 0, 0x0304, 0),
|
||||
PLL(CLK_APMIXED_ETH2PLL, "eth2pll", 0x0314, 0x0320, 0x00000001,
|
||||
0, 21, 0x0314, 1, 0, 0x0318, 0),
|
||||
PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x0324, 0x0330, 0x00000001,
|
||||
0, 31, 0x0324, 1, 0, 0x0328, 0),
|
||||
PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x0334, 0x0340, 0x00000001,
|
||||
0, 31, 0x0334, 1, 0, 0x0338, 0),
|
||||
PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x0344, 0x0354, 0x00000001,
|
||||
0, 21, 0x0344, 1, 0, 0x0348, 0),
|
||||
PLL(CLK_APMIXED_SGMIPLL, "sgmipll", 0x0358, 0x0368, 0x00000001,
|
||||
0, 21, 0x0358, 1, 0, 0x035C, 0),
|
||||
};
|
||||
|
||||
static const struct mtk_gate apmixed_clks[] = {
|
||||
GATE_APMIXED(CLK_APMIXED_MAIN_CORE_EN, "main_core_en", "mainpll", 5),
|
||||
};
|
||||
|
||||
static const struct mtk_gate infra_clks[] = {
|
||||
GATE_INFRA(CLK_INFRA_DBGCLK_PD, "infra_dbgclk_pd", "axi_sel", 0),
|
||||
GATE_INFRA(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 2),
|
||||
GATE_INFRA(CLK_INFRA_AUDIO_PD, "infra_audio_pd", "aud_intbus_sel", 5),
|
||||
GATE_INFRA(CLK_INFRA_IRRX_PD, "infra_irrx_pd", "irrx_sel", 16),
|
||||
GATE_INFRA(CLK_INFRA_APXGPT_PD, "infra_apxgpt_pd", "f10m_ref_sel", 18),
|
||||
GATE_INFRA(CLK_INFRA_PMIC_PD, "infra_pmic_pd", "pmicspi_sel", 22),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_clk top_fixed_clks[] = {
|
||||
FIXED_CLK(CLK_TOP_TO_U2_PHY, "to_u2_phy", "clkxtal",
|
||||
31250000),
|
||||
FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, "to_u2_phy_1p", "clkxtal",
|
||||
31250000),
|
||||
FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, "pcie0_pipe_en", "clkxtal",
|
||||
125000000),
|
||||
FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, "pcie1_pipe_en", "clkxtal",
|
||||
125000000),
|
||||
FIXED_CLK(CLK_TOP_SSUSB_TX250M, "ssusb_tx250m", "clkxtal",
|
||||
250000000),
|
||||
FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, "ssusb_eq_rx250m", "clkxtal",
|
||||
250000000),
|
||||
FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, "ssusb_cdr_ref", "clkxtal",
|
||||
33333333),
|
||||
FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, "ssusb_cdr_fb", "clkxtal",
|
||||
50000000),
|
||||
FIXED_CLK(CLK_TOP_SATA_ASIC, "sata_asic", "clkxtal",
|
||||
50000000),
|
||||
FIXED_CLK(CLK_TOP_SATA_RBC, "sata_rbc", "clkxtal",
|
||||
50000000),
|
||||
};
|
||||
|
||||
static const struct mtk_fixed_factor top_divs[] = {
|
||||
FACTOR(CLK_TOP_TO_USB3_SYS, "to_usb3_sys", "eth1pll", 1, 4),
|
||||
FACTOR(CLK_TOP_P1_1MHZ, "p1_1mhz", "eth1pll", 1, 500),
|
||||
FACTOR(CLK_TOP_4MHZ, "free_run_4mhz", "eth1pll", 1, 125),
|
||||
FACTOR(CLK_TOP_P0_1MHZ, "p0_1mhz", "eth1pll", 1, 500),
|
||||
FACTOR(CLK_TOP_TXCLK_SRC_PRE, "txclk_src_pre", "sgmiipll_d2", 1, 1),
|
||||
FACTOR(CLK_TOP_RTC, "rtc", "clkxtal", 1, 1024),
|
||||
FACTOR(CLK_TOP_MEMPLL, "mempll", "clkxtal", 32, 1),
|
||||
FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
|
||||
FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "mainpll", 1, 4),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "mainpll", 1, 8),
|
||||
FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "mainpll", 1, 16),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "mainpll", 1, 12),
|
||||
FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "mainpll", 1, 24),
|
||||
FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "mainpll", 1, 10),
|
||||
FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "mainpll", 1, 20),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "mainpll", 1, 14),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "mainpll", 1, 28),
|
||||
FACTOR(CLK_TOP_SYSPLL4_D16, "syspll4_d16", "mainpll", 1, 112),
|
||||
FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll", 1, 4),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll", 1, 8),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll", 1, 16),
|
||||
FACTOR(CLK_TOP_UNIVPLL1_D16, "univpll1_d16", "univpll", 1, 32),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll", 1, 6),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll", 1, 12),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll", 1, 24),
|
||||
FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll", 1, 48),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll", 1, 10),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll", 1, 20),
|
||||
FACTOR(CLK_TOP_UNIVPLL3_D16, "univpll3_d16", "univpll", 1, 80),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
|
||||
FACTOR(CLK_TOP_UNIVPLL_D80_D4, "univpll_d80_d4", "univpll", 1, 320),
|
||||
FACTOR(CLK_TOP_UNIV48M, "univ48m", "univpll", 1, 25),
|
||||
FACTOR(CLK_TOP_SGMIIPLL, "sgmiipll_ck", "sgmipll", 1, 1),
|
||||
FACTOR(CLK_TOP_SGMIIPLL_D2, "sgmiipll_d2", "sgmipll", 1, 2),
|
||||
FACTOR(CLK_TOP_AUD1PLL, "aud1pll_ck", "aud1pll", 1, 1),
|
||||
FACTOR(CLK_TOP_AUD2PLL, "aud2pll_ck", "aud2pll", 1, 1),
|
||||
FACTOR(CLK_TOP_AUD_I2S2_MCK, "aud_i2s2_mck", "i2s2_mck_sel", 1, 2),
|
||||
FACTOR(CLK_TOP_TO_USB3_REF, "to_usb3_ref", "univpll2_d4", 1, 4),
|
||||
FACTOR(CLK_TOP_PCIE1_MAC_EN, "pcie1_mac_en", "univpll1_d4", 1, 1),
|
||||
FACTOR(CLK_TOP_PCIE0_MAC_EN, "pcie0_mac_en", "univpll1_d4", 1, 1),
|
||||
FACTOR(CLK_TOP_ETH_500M, "eth_500m", "eth1pll", 1, 1),
|
||||
};
|
||||
|
||||
static const struct mtk_gate top_clks[] = {
|
||||
/* TOP0 */
|
||||
GATE_TOP0(CLK_TOP_APLL1_DIV_PD, "apll1_ck_div_pd", "apll1_ck_div", 0),
|
||||
GATE_TOP0(CLK_TOP_APLL2_DIV_PD, "apll2_ck_div_pd", "apll2_ck_div", 1),
|
||||
GATE_TOP0(CLK_TOP_I2S0_MCK_DIV_PD, "i2s0_mck_div_pd", "i2s0_mck_div",
|
||||
2),
|
||||
GATE_TOP0(CLK_TOP_I2S1_MCK_DIV_PD, "i2s1_mck_div_pd", "i2s1_mck_div",
|
||||
3),
|
||||
GATE_TOP0(CLK_TOP_I2S2_MCK_DIV_PD, "i2s2_mck_div_pd", "i2s2_mck_div",
|
||||
4),
|
||||
GATE_TOP0(CLK_TOP_I2S3_MCK_DIV_PD, "i2s3_mck_div_pd", "i2s3_mck_div",
|
||||
5),
|
||||
|
||||
/* TOP1 */
|
||||
GATE_TOP1(CLK_TOP_A1SYS_HP_DIV_PD, "a1sys_div_pd", "a1sys_div", 0),
|
||||
GATE_TOP1(CLK_TOP_A2SYS_HP_DIV_PD, "a2sys_div_pd", "a2sys_div", 16),
|
||||
};
|
||||
|
||||
static const struct mtk_clk_divider top_adj_divs[] = {
|
||||
DIV_ADJ(CLK_TOP_APLL1_DIV, "apll1_ck_div", "apll1_ck_sel",
|
||||
0x120, 24, 3),
|
||||
DIV_ADJ(CLK_TOP_APLL2_DIV, "apll2_ck_div", "apll2_ck_sel",
|
||||
0x120, 28, 3),
|
||||
DIV_ADJ(CLK_TOP_I2S0_MCK_DIV, "i2s0_mck_div", "i2s0_mck_sel",
|
||||
0x124, 0, 7),
|
||||
DIV_ADJ(CLK_TOP_I2S1_MCK_DIV, "i2s1_mck_div", "i2s1_mck_sel",
|
||||
0x124, 8, 7),
|
||||
DIV_ADJ(CLK_TOP_I2S2_MCK_DIV, "i2s2_mck_div", "aud_i2s2_mck",
|
||||
0x124, 16, 7),
|
||||
DIV_ADJ(CLK_TOP_I2S3_MCK_DIV, "i2s3_mck_div", "i2s3_mck_sel",
|
||||
0x124, 24, 7),
|
||||
DIV_ADJ(CLK_TOP_A1SYS_HP_DIV, "a1sys_div", "a1sys_hp_sel",
|
||||
0x128, 8, 7),
|
||||
DIV_ADJ(CLK_TOP_A2SYS_HP_DIV, "a2sys_div", "a2sys_hp_sel",
|
||||
0x128, 24, 7),
|
||||
};
|
||||
|
||||
static const struct mtk_gate peri_clks[] = {
|
||||
/* PERI0 */
|
||||
GATE_PERI0(CLK_PERI_THERM_PD, "peri_therm_pd", "axi_sel", 1),
|
||||
GATE_PERI0(CLK_PERI_PWM1_PD, "peri_pwm1_pd", "clkxtal", 2),
|
||||
GATE_PERI0(CLK_PERI_PWM2_PD, "peri_pwm2_pd", "clkxtal", 3),
|
||||
GATE_PERI0(CLK_PERI_PWM3_PD, "peri_pwm3_pd", "clkxtal", 4),
|
||||
GATE_PERI0(CLK_PERI_PWM4_PD, "peri_pwm4_pd", "clkxtal", 5),
|
||||
GATE_PERI0(CLK_PERI_PWM5_PD, "peri_pwm5_pd", "clkxtal", 6),
|
||||
GATE_PERI0(CLK_PERI_PWM6_PD, "peri_pwm6_pd", "clkxtal", 7),
|
||||
GATE_PERI0(CLK_PERI_PWM7_PD, "peri_pwm7_pd", "clkxtal", 8),
|
||||
GATE_PERI0(CLK_PERI_PWM_PD, "peri_pwm_pd", "clkxtal", 9),
|
||||
GATE_PERI0(CLK_PERI_AP_DMA_PD, "peri_ap_dma_pd", "axi_sel", 12),
|
||||
GATE_PERI0(CLK_PERI_MSDC30_0_PD, "peri_msdc30_0", "msdc30_0_sel", 13),
|
||||
GATE_PERI0(CLK_PERI_MSDC30_1_PD, "peri_msdc30_1", "msdc30_1_sel", 14),
|
||||
GATE_PERI0(CLK_PERI_UART0_PD, "peri_uart0_pd", "axi_sel", 17),
|
||||
GATE_PERI0(CLK_PERI_UART1_PD, "peri_uart1_pd", "axi_sel", 18),
|
||||
GATE_PERI0(CLK_PERI_UART2_PD, "peri_uart2_pd", "axi_sel", 19),
|
||||
GATE_PERI0(CLK_PERI_UART3_PD, "peri_uart3_pd", "axi_sel", 20),
|
||||
GATE_PERI0(CLK_PERI_UART4_PD, "peri_uart4_pd", "axi_sel", 21),
|
||||
GATE_PERI0(CLK_PERI_BTIF_PD, "peri_btif_pd", "axi_sel", 22),
|
||||
GATE_PERI0(CLK_PERI_I2C0_PD, "peri_i2c0_pd", "axi_sel", 23),
|
||||
GATE_PERI0(CLK_PERI_I2C1_PD, "peri_i2c1_pd", "axi_sel", 24),
|
||||
GATE_PERI0(CLK_PERI_I2C2_PD, "peri_i2c2_pd", "axi_sel", 25),
|
||||
GATE_PERI0(CLK_PERI_SPI1_PD, "peri_spi1_pd", "spi1_sel", 26),
|
||||
GATE_PERI0(CLK_PERI_AUXADC_PD, "peri_auxadc_pd", "clkxtal", 27),
|
||||
GATE_PERI0(CLK_PERI_SPI0_PD, "peri_spi0_pd", "spi0_sel", 28),
|
||||
GATE_PERI0(CLK_PERI_SNFI_PD, "peri_snfi_pd", "nfi_infra_sel", 29),
|
||||
GATE_PERI0(CLK_PERI_NFI_PD, "peri_nfi_pd", "axi_sel", 30),
|
||||
GATE_PERI0(CLK_PERI_NFIECC_PD, "peri_nfiecc_pd", "axi_sel", 31),
|
||||
|
||||
/* PERI1 */
|
||||
GATE_PERI1(CLK_PERI_FLASH_PD, "peri_flash_pd", "flash_sel", 1),
|
||||
GATE_PERI1(CLK_PERI_IRTX_PD, "peri_irtx_pd", "irtx_sel", 2),
|
||||
};
|
||||
|
||||
static struct mtk_composite infra_muxes[] __initdata = {
|
||||
MUX(CLK_INFRA_MUX1_SEL, "infra_mux1_sel", infra_mux1_parents,
|
||||
0x000, 2, 2),
|
||||
};
|
||||
|
||||
static struct mtk_composite top_muxes[] = {
|
||||
/* CLK_CFG_0 */
|
||||
MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
|
||||
0x040, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
|
||||
0x040, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
|
||||
0x040, 16, 1, 23),
|
||||
MUX_GATE(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
|
||||
0x040, 24, 3, 31),
|
||||
|
||||
/* CLK_CFG_1 */
|
||||
MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
|
||||
0x050, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_F10M_REF_SEL, "f10m_ref_sel", f10m_ref_parents,
|
||||
0x050, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_NFI_INFRA_SEL, "nfi_infra_sel", nfi_infra_parents,
|
||||
0x050, 16, 4, 23),
|
||||
MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
|
||||
0x050, 24, 3, 31),
|
||||
|
||||
/* CLK_CFG_2 */
|
||||
MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
|
||||
0x060, 0, 1, 7),
|
||||
MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi0_parents,
|
||||
0x060, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_SPI1_SEL, "spi1_sel", spi1_parents,
|
||||
0x060, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel", uart_parents,
|
||||
0x060, 24, 3, 31),
|
||||
|
||||
/* CLK_CFG_3 */
|
||||
MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_0_parents,
|
||||
0x070, 0, 3, 7),
|
||||
MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
|
||||
0x070, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel", a1sys_hp_parents,
|
||||
0x070, 16, 2, 23),
|
||||
MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel", a1sys_hp_parents,
|
||||
0x070, 24, 2, 31),
|
||||
|
||||
/* CLK_CFG_4 */
|
||||
MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
|
||||
0x080, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
|
||||
0x080, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
|
||||
0x080, 16, 3, 23),
|
||||
MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
|
||||
0x080, 24, 2, 31),
|
||||
|
||||
/* CLK_CFG_5 */
|
||||
MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents,
|
||||
0x090, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_HIF_SEL, "hif_sel", eth_parents,
|
||||
0x090, 8, 3, 15),
|
||||
MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
|
||||
0x090, 16, 2, 23),
|
||||
MUX_GATE(CLK_TOP_U2_SEL, "usb20_sel", usb20_parents,
|
||||
0x090, 24, 2, 31),
|
||||
|
||||
/* CLK_CFG_6 */
|
||||
MUX_GATE(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
|
||||
0x0A0, 0, 1, 7),
|
||||
MUX_GATE(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
|
||||
0x0A0, 8, 1, 15),
|
||||
MUX_GATE(CLK_TOP_IRRX_SEL, "irrx_sel", f10m_ref_parents,
|
||||
0x0A0, 16, 1, 23),
|
||||
MUX_GATE(CLK_TOP_IRTX_SEL, "irtx_sel", f10m_ref_parents,
|
||||
0x0A0, 24, 1, 31),
|
||||
|
||||
/* CLK_CFG_7 */
|
||||
MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel", asm_l_parents,
|
||||
0x0B0, 0, 2, 7),
|
||||
MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_l_parents,
|
||||
0x0B0, 8, 2, 15),
|
||||
MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_l_parents,
|
||||
0x0B0, 16, 2, 23),
|
||||
|
||||
/* CLK_AUDDIV_0 */
|
||||
MUX(CLK_TOP_APLL1_SEL, "apll1_ck_sel", apll1_ck_parents,
|
||||
0x120, 6, 1),
|
||||
MUX(CLK_TOP_APLL2_SEL, "apll2_ck_sel", apll1_ck_parents,
|
||||
0x120, 7, 1),
|
||||
MUX(CLK_TOP_I2S0_MCK_SEL, "i2s0_mck_sel", apll1_ck_parents,
|
||||
0x120, 8, 1),
|
||||
MUX(CLK_TOP_I2S1_MCK_SEL, "i2s1_mck_sel", apll1_ck_parents,
|
||||
0x120, 9, 1),
|
||||
MUX(CLK_TOP_I2S2_MCK_SEL, "i2s2_mck_sel", apll1_ck_parents,
|
||||
0x120, 10, 1),
|
||||
MUX(CLK_TOP_I2S3_MCK_SEL, "i2s3_mck_sel", apll1_ck_parents,
|
||||
0x120, 11, 1),
|
||||
};
|
||||
|
||||
static struct mtk_composite peri_muxes[] = {
|
||||
/* PERI_GLOBALCON_CKSEL */
|
||||
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
|
||||
};
|
||||
|
||||
static int mtk_topckgen_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
|
||||
|
||||
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
|
||||
clk_data);
|
||||
|
||||
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
|
||||
clk_data);
|
||||
|
||||
mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
|
||||
base, &mt7622_clk_lock, clk_data);
|
||||
|
||||
mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
|
||||
base, &mt7622_clk_lock, clk_data);
|
||||
|
||||
mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
|
||||
clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_AXI_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_MEM_SEL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_TOP_DDRPHYCFG_SEL]);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int __init mtk_infrasys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct clk_onecell_data *clk_data;
|
||||
int r;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
|
||||
clk_data);
|
||||
|
||||
mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes),
|
||||
clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get,
|
||||
clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
mtk_register_reset_controller(node, 1, 0x30);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_apmixedsys_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
|
||||
clk_data);
|
||||
|
||||
mtk_clk_register_gates(node, apmixed_clks,
|
||||
ARRAY_SIZE(apmixed_clks), clk_data);
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
|
||||
clk_prepare_enable(clk_data->clks[CLK_APMIXED_MAIN_CORE_EN]);
|
||||
|
||||
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
}
|
||||
|
||||
static int mtk_pericfg_init(struct platform_device *pdev)
|
||||
{
|
||||
struct clk_onecell_data *clk_data;
|
||||
void __iomem *base;
|
||||
int r;
|
||||
struct device_node *node = pdev->dev.of_node;
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
|
||||
|
||||
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
|
||||
clk_data);
|
||||
|
||||
mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base,
|
||||
&mt7622_clk_lock, clk_data);
|
||||
|
||||
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
clk_prepare_enable(clk_data->clks[CLK_PERI_UART0_PD]);
|
||||
|
||||
mtk_register_reset_controller(node, 2, 0x0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id of_match_clk_mt7622[] = {
|
||||
{
|
||||
.compatible = "mediatek,mt7622-apmixedsys",
|
||||
.data = mtk_apmixedsys_init,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-infracfg",
|
||||
.data = mtk_infrasys_init,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-topckgen",
|
||||
.data = mtk_topckgen_init,
|
||||
}, {
|
||||
.compatible = "mediatek,mt7622-pericfg",
|
||||
.data = mtk_pericfg_init,
|
||||
}, {
|
||||
/* sentinel */
|
||||
}
|
||||
};
|
||||
|
||||
static int clk_mt7622_probe(struct platform_device *pdev)
|
||||
{
|
||||
int (*clk_init)(struct platform_device *);
|
||||
int r;
|
||||
|
||||
clk_init = of_device_get_match_data(&pdev->dev);
|
||||
if (!clk_init)
|
||||
return -EINVAL;
|
||||
|
||||
r = clk_init(pdev);
|
||||
if (r)
|
||||
dev_err(&pdev->dev,
|
||||
"could not register clock provider: %s: %d\n",
|
||||
pdev->name, r);
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
static struct platform_driver clk_mt7622_drv = {
|
||||
.probe = clk_mt7622_probe,
|
||||
.driver = {
|
||||
.name = "clk-mt7622",
|
||||
.of_match_table = of_match_clk_mt7622,
|
||||
},
|
||||
};
|
||||
|
||||
static int clk_mt7622_init(void)
|
||||
{
|
||||
return platform_driver_register(&clk_mt7622_drv);
|
||||
}
|
||||
|
||||
arch_initcall(clk_mt7622_init);
|
||||
@ -207,6 +207,8 @@ struct mtk_pll_data {
|
||||
uint32_t en_mask;
|
||||
uint32_t pd_reg;
|
||||
uint32_t tuner_reg;
|
||||
uint32_t tuner_en_reg;
|
||||
uint8_t tuner_en_bit;
|
||||
int pd_shift;
|
||||
unsigned int flags;
|
||||
const struct clk_ops *ops;
|
||||
@ -216,6 +218,7 @@ struct mtk_pll_data {
|
||||
uint32_t pcw_reg;
|
||||
int pcw_shift;
|
||||
const struct mtk_pll_div_table *div_table;
|
||||
const char *parent_name;
|
||||
};
|
||||
|
||||
void mtk_clk_register_plls(struct device_node *node,
|
||||
|
||||
@ -47,6 +47,7 @@ struct mtk_clk_pll {
|
||||
void __iomem *pd_addr;
|
||||
void __iomem *pwr_addr;
|
||||
void __iomem *tuner_addr;
|
||||
void __iomem *tuner_en_addr;
|
||||
void __iomem *pcw_addr;
|
||||
const struct mtk_pll_data *data;
|
||||
};
|
||||
@ -227,7 +228,10 @@ static int mtk_pll_prepare(struct clk_hw *hw)
|
||||
r |= pll->data->en_mask;
|
||||
writel(r, pll->base_addr + REG_CON0);
|
||||
|
||||
if (pll->tuner_addr) {
|
||||
if (pll->tuner_en_addr) {
|
||||
r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit);
|
||||
writel(r, pll->tuner_en_addr);
|
||||
} else if (pll->tuner_addr) {
|
||||
r = readl(pll->tuner_addr) | AUDPLL_TUNER_EN;
|
||||
writel(r, pll->tuner_addr);
|
||||
}
|
||||
@ -254,7 +258,10 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
|
||||
writel(r, pll->base_addr + REG_CON0);
|
||||
}
|
||||
|
||||
if (pll->tuner_addr) {
|
||||
if (pll->tuner_en_addr) {
|
||||
r = readl(pll->tuner_en_addr) & ~BIT(pll->data->tuner_en_bit);
|
||||
writel(r, pll->tuner_en_addr);
|
||||
} else if (pll->tuner_addr) {
|
||||
r = readl(pll->tuner_addr) & ~AUDPLL_TUNER_EN;
|
||||
writel(r, pll->tuner_addr);
|
||||
}
|
||||
@ -297,13 +304,18 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
|
||||
pll->pcw_addr = base + data->pcw_reg;
|
||||
if (data->tuner_reg)
|
||||
pll->tuner_addr = base + data->tuner_reg;
|
||||
if (data->tuner_en_reg)
|
||||
pll->tuner_en_addr = base + data->tuner_en_reg;
|
||||
pll->hw.init = &init;
|
||||
pll->data = data;
|
||||
|
||||
init.name = data->name;
|
||||
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
|
||||
init.ops = &mtk_pll_ops;
|
||||
init.parent_names = &parent_name;
|
||||
if (data->parent_name)
|
||||
init.parent_names = &data->parent_name;
|
||||
else
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
clk = clk_register(NULL, &pll->hw);
|
||||
|
||||
427
include/dt-bindings/clock/mt2712-clk.h
Normal file
427
include/dt-bindings/clock/mt2712-clk.h
Normal file
@ -0,0 +1,427 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Weiyi Lu <weiyi.lu@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT2712_H
|
||||
#define _DT_BINDINGS_CLK_MT2712_H
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_MAINPLL 0
|
||||
#define CLK_APMIXED_UNIVPLL 1
|
||||
#define CLK_APMIXED_VCODECPLL 2
|
||||
#define CLK_APMIXED_VENCPLL 3
|
||||
#define CLK_APMIXED_APLL1 4
|
||||
#define CLK_APMIXED_APLL2 5
|
||||
#define CLK_APMIXED_LVDSPLL 6
|
||||
#define CLK_APMIXED_LVDSPLL2 7
|
||||
#define CLK_APMIXED_MSDCPLL 8
|
||||
#define CLK_APMIXED_MSDCPLL2 9
|
||||
#define CLK_APMIXED_TVDPLL 10
|
||||
#define CLK_APMIXED_MMPLL 11
|
||||
#define CLK_APMIXED_ARMCA35PLL 12
|
||||
#define CLK_APMIXED_ARMCA72PLL 13
|
||||
#define CLK_APMIXED_ETHERPLL 14
|
||||
#define CLK_APMIXED_NR_CLK 15
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_ARMCA35PLL 0
|
||||
#define CLK_TOP_ARMCA35PLL_600M 1
|
||||
#define CLK_TOP_ARMCA35PLL_400M 2
|
||||
#define CLK_TOP_ARMCA72PLL 3
|
||||
#define CLK_TOP_SYSPLL 4
|
||||
#define CLK_TOP_SYSPLL_D2 5
|
||||
#define CLK_TOP_SYSPLL1_D2 6
|
||||
#define CLK_TOP_SYSPLL1_D4 7
|
||||
#define CLK_TOP_SYSPLL1_D8 8
|
||||
#define CLK_TOP_SYSPLL1_D16 9
|
||||
#define CLK_TOP_SYSPLL_D3 10
|
||||
#define CLK_TOP_SYSPLL2_D2 11
|
||||
#define CLK_TOP_SYSPLL2_D4 12
|
||||
#define CLK_TOP_SYSPLL_D5 13
|
||||
#define CLK_TOP_SYSPLL3_D2 14
|
||||
#define CLK_TOP_SYSPLL3_D4 15
|
||||
#define CLK_TOP_SYSPLL_D7 16
|
||||
#define CLK_TOP_SYSPLL4_D2 17
|
||||
#define CLK_TOP_SYSPLL4_D4 18
|
||||
#define CLK_TOP_UNIVPLL 19
|
||||
#define CLK_TOP_UNIVPLL_D7 20
|
||||
#define CLK_TOP_UNIVPLL_D26 21
|
||||
#define CLK_TOP_UNIVPLL_D52 22
|
||||
#define CLK_TOP_UNIVPLL_D104 23
|
||||
#define CLK_TOP_UNIVPLL_D208 24
|
||||
#define CLK_TOP_UNIVPLL_D2 25
|
||||
#define CLK_TOP_UNIVPLL1_D2 26
|
||||
#define CLK_TOP_UNIVPLL1_D4 27
|
||||
#define CLK_TOP_UNIVPLL1_D8 28
|
||||
#define CLK_TOP_UNIVPLL_D3 29
|
||||
#define CLK_TOP_UNIVPLL2_D2 30
|
||||
#define CLK_TOP_UNIVPLL2_D4 31
|
||||
#define CLK_TOP_UNIVPLL2_D8 32
|
||||
#define CLK_TOP_UNIVPLL_D5 33
|
||||
#define CLK_TOP_UNIVPLL3_D2 34
|
||||
#define CLK_TOP_UNIVPLL3_D4 35
|
||||
#define CLK_TOP_UNIVPLL3_D8 36
|
||||
#define CLK_TOP_F_MP0_PLL1 37
|
||||
#define CLK_TOP_F_MP0_PLL2 38
|
||||
#define CLK_TOP_F_BIG_PLL1 39
|
||||
#define CLK_TOP_F_BIG_PLL2 40
|
||||
#define CLK_TOP_F_BUS_PLL1 41
|
||||
#define CLK_TOP_F_BUS_PLL2 42
|
||||
#define CLK_TOP_APLL1 43
|
||||
#define CLK_TOP_APLL1_D2 44
|
||||
#define CLK_TOP_APLL1_D4 45
|
||||
#define CLK_TOP_APLL1_D8 46
|
||||
#define CLK_TOP_APLL1_D16 47
|
||||
#define CLK_TOP_APLL2 48
|
||||
#define CLK_TOP_APLL2_D2 49
|
||||
#define CLK_TOP_APLL2_D4 50
|
||||
#define CLK_TOP_APLL2_D8 51
|
||||
#define CLK_TOP_APLL2_D16 52
|
||||
#define CLK_TOP_LVDSPLL 53
|
||||
#define CLK_TOP_LVDSPLL_D2 54
|
||||
#define CLK_TOP_LVDSPLL_D4 55
|
||||
#define CLK_TOP_LVDSPLL_D8 56
|
||||
#define CLK_TOP_LVDSPLL2 57
|
||||
#define CLK_TOP_LVDSPLL2_D2 58
|
||||
#define CLK_TOP_LVDSPLL2_D4 59
|
||||
#define CLK_TOP_LVDSPLL2_D8 60
|
||||
#define CLK_TOP_ETHERPLL_125M 61
|
||||
#define CLK_TOP_ETHERPLL_50M 62
|
||||
#define CLK_TOP_CVBS 63
|
||||
#define CLK_TOP_CVBS_D2 64
|
||||
#define CLK_TOP_SYS_26M 65
|
||||
#define CLK_TOP_MMPLL 66
|
||||
#define CLK_TOP_MMPLL_D2 67
|
||||
#define CLK_TOP_VENCPLL 68
|
||||
#define CLK_TOP_VENCPLL_D2 69
|
||||
#define CLK_TOP_VCODECPLL 70
|
||||
#define CLK_TOP_VCODECPLL_D2 71
|
||||
#define CLK_TOP_TVDPLL 72
|
||||
#define CLK_TOP_TVDPLL_D2 73
|
||||
#define CLK_TOP_TVDPLL_D4 74
|
||||
#define CLK_TOP_TVDPLL_D8 75
|
||||
#define CLK_TOP_TVDPLL_429M 76
|
||||
#define CLK_TOP_TVDPLL_429M_D2 77
|
||||
#define CLK_TOP_TVDPLL_429M_D4 78
|
||||
#define CLK_TOP_MSDCPLL 79
|
||||
#define CLK_TOP_MSDCPLL_D2 80
|
||||
#define CLK_TOP_MSDCPLL_D4 81
|
||||
#define CLK_TOP_MSDCPLL2 82
|
||||
#define CLK_TOP_MSDCPLL2_D2 83
|
||||
#define CLK_TOP_MSDCPLL2_D4 84
|
||||
#define CLK_TOP_CLK26M_D2 85
|
||||
#define CLK_TOP_D2A_ULCLK_6P5M 86
|
||||
#define CLK_TOP_VPLL3_DPIX 87
|
||||
#define CLK_TOP_VPLL_DPIX 88
|
||||
#define CLK_TOP_LTEPLL_FS26M 89
|
||||
#define CLK_TOP_DMPLL 90
|
||||
#define CLK_TOP_DSI0_LNTC 91
|
||||
#define CLK_TOP_DSI1_LNTC 92
|
||||
#define CLK_TOP_LVDSTX3_CLKDIG_CTS 93
|
||||
#define CLK_TOP_LVDSTX_CLKDIG_CTS 94
|
||||
#define CLK_TOP_CLKRTC_EXT 95
|
||||
#define CLK_TOP_CLKRTC_INT 96
|
||||
#define CLK_TOP_CSI0 97
|
||||
#define CLK_TOP_CVBSPLL 98
|
||||
#define CLK_TOP_AXI_SEL 99
|
||||
#define CLK_TOP_MEM_SEL 100
|
||||
#define CLK_TOP_MM_SEL 101
|
||||
#define CLK_TOP_PWM_SEL 102
|
||||
#define CLK_TOP_VDEC_SEL 103
|
||||
#define CLK_TOP_VENC_SEL 104
|
||||
#define CLK_TOP_MFG_SEL 105
|
||||
#define CLK_TOP_CAMTG_SEL 106
|
||||
#define CLK_TOP_UART_SEL 107
|
||||
#define CLK_TOP_SPI_SEL 108
|
||||
#define CLK_TOP_USB20_SEL 109
|
||||
#define CLK_TOP_USB30_SEL 110
|
||||
#define CLK_TOP_MSDC50_0_HCLK_SEL 111
|
||||
#define CLK_TOP_MSDC50_0_SEL 112
|
||||
#define CLK_TOP_MSDC30_1_SEL 113
|
||||
#define CLK_TOP_MSDC30_2_SEL 114
|
||||
#define CLK_TOP_MSDC30_3_SEL 115
|
||||
#define CLK_TOP_AUDIO_SEL 116
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 117
|
||||
#define CLK_TOP_PMICSPI_SEL 118
|
||||
#define CLK_TOP_DPILVDS1_SEL 119
|
||||
#define CLK_TOP_ATB_SEL 120
|
||||
#define CLK_TOP_NR_SEL 121
|
||||
#define CLK_TOP_NFI2X_SEL 122
|
||||
#define CLK_TOP_IRDA_SEL 123
|
||||
#define CLK_TOP_CCI400_SEL 124
|
||||
#define CLK_TOP_AUD_1_SEL 125
|
||||
#define CLK_TOP_AUD_2_SEL 126
|
||||
#define CLK_TOP_MEM_MFG_IN_AS_SEL 127
|
||||
#define CLK_TOP_AXI_MFG_IN_AS_SEL 128
|
||||
#define CLK_TOP_SCAM_SEL 129
|
||||
#define CLK_TOP_NFIECC_SEL 130
|
||||
#define CLK_TOP_PE2_MAC_P0_SEL 131
|
||||
#define CLK_TOP_PE2_MAC_P1_SEL 132
|
||||
#define CLK_TOP_DPILVDS_SEL 133
|
||||
#define CLK_TOP_MSDC50_3_HCLK_SEL 134
|
||||
#define CLK_TOP_HDCP_SEL 135
|
||||
#define CLK_TOP_HDCP_24M_SEL 136
|
||||
#define CLK_TOP_RTC_SEL 137
|
||||
#define CLK_TOP_SPINOR_SEL 138
|
||||
#define CLK_TOP_APLL_SEL 139
|
||||
#define CLK_TOP_APLL2_SEL 140
|
||||
#define CLK_TOP_A1SYS_HP_SEL 141
|
||||
#define CLK_TOP_A2SYS_HP_SEL 142
|
||||
#define CLK_TOP_ASM_L_SEL 143
|
||||
#define CLK_TOP_ASM_M_SEL 144
|
||||
#define CLK_TOP_ASM_H_SEL 145
|
||||
#define CLK_TOP_I2SO1_SEL 146
|
||||
#define CLK_TOP_I2SO2_SEL 147
|
||||
#define CLK_TOP_I2SO3_SEL 148
|
||||
#define CLK_TOP_TDMO0_SEL 149
|
||||
#define CLK_TOP_TDMO1_SEL 150
|
||||
#define CLK_TOP_I2SI1_SEL 151
|
||||
#define CLK_TOP_I2SI2_SEL 152
|
||||
#define CLK_TOP_I2SI3_SEL 153
|
||||
#define CLK_TOP_ETHER_125M_SEL 154
|
||||
#define CLK_TOP_ETHER_50M_SEL 155
|
||||
#define CLK_TOP_JPGDEC_SEL 156
|
||||
#define CLK_TOP_SPISLV_SEL 157
|
||||
#define CLK_TOP_ETHER_50M_RMII_SEL 158
|
||||
#define CLK_TOP_CAM2TG_SEL 159
|
||||
#define CLK_TOP_DI_SEL 160
|
||||
#define CLK_TOP_TVD_SEL 161
|
||||
#define CLK_TOP_I2C_SEL 162
|
||||
#define CLK_TOP_PWM_INFRA_SEL 163
|
||||
#define CLK_TOP_MSDC0P_AES_SEL 164
|
||||
#define CLK_TOP_CMSYS_SEL 165
|
||||
#define CLK_TOP_GCPU_SEL 166
|
||||
#define CLK_TOP_AUD_APLL1_SEL 167
|
||||
#define CLK_TOP_AUD_APLL2_SEL 168
|
||||
#define CLK_TOP_DA_AUDULL_VTX_6P5M_SEL 169
|
||||
#define CLK_TOP_APLL_DIV0 170
|
||||
#define CLK_TOP_APLL_DIV1 171
|
||||
#define CLK_TOP_APLL_DIV2 172
|
||||
#define CLK_TOP_APLL_DIV3 173
|
||||
#define CLK_TOP_APLL_DIV4 174
|
||||
#define CLK_TOP_APLL_DIV5 175
|
||||
#define CLK_TOP_APLL_DIV6 176
|
||||
#define CLK_TOP_APLL_DIV7 177
|
||||
#define CLK_TOP_APLL_DIV_PDN0 178
|
||||
#define CLK_TOP_APLL_DIV_PDN1 179
|
||||
#define CLK_TOP_APLL_DIV_PDN2 180
|
||||
#define CLK_TOP_APLL_DIV_PDN3 181
|
||||
#define CLK_TOP_APLL_DIV_PDN4 182
|
||||
#define CLK_TOP_APLL_DIV_PDN5 183
|
||||
#define CLK_TOP_APLL_DIV_PDN6 184
|
||||
#define CLK_TOP_APLL_DIV_PDN7 185
|
||||
#define CLK_TOP_NR_CLK 186
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_INFRA_DBGCLK 0
|
||||
#define CLK_INFRA_GCE 1
|
||||
#define CLK_INFRA_M4U 2
|
||||
#define CLK_INFRA_KP 3
|
||||
#define CLK_INFRA_AO_SPI0 4
|
||||
#define CLK_INFRA_AO_SPI1 5
|
||||
#define CLK_INFRA_AO_UART5 6
|
||||
#define CLK_INFRA_NR_CLK 7
|
||||
|
||||
/* PERICFG */
|
||||
|
||||
#define CLK_PERI_NFI 0
|
||||
#define CLK_PERI_THERM 1
|
||||
#define CLK_PERI_PWM0 2
|
||||
#define CLK_PERI_PWM1 3
|
||||
#define CLK_PERI_PWM2 4
|
||||
#define CLK_PERI_PWM3 5
|
||||
#define CLK_PERI_PWM4 6
|
||||
#define CLK_PERI_PWM5 7
|
||||
#define CLK_PERI_PWM6 8
|
||||
#define CLK_PERI_PWM7 9
|
||||
#define CLK_PERI_PWM 10
|
||||
#define CLK_PERI_AP_DMA 11
|
||||
#define CLK_PERI_MSDC30_0 12
|
||||
#define CLK_PERI_MSDC30_1 13
|
||||
#define CLK_PERI_MSDC30_2 14
|
||||
#define CLK_PERI_MSDC30_3 15
|
||||
#define CLK_PERI_UART0 16
|
||||
#define CLK_PERI_UART1 17
|
||||
#define CLK_PERI_UART2 18
|
||||
#define CLK_PERI_UART3 19
|
||||
#define CLK_PERI_I2C0 20
|
||||
#define CLK_PERI_I2C1 21
|
||||
#define CLK_PERI_I2C2 22
|
||||
#define CLK_PERI_I2C3 23
|
||||
#define CLK_PERI_I2C4 24
|
||||
#define CLK_PERI_AUXADC 25
|
||||
#define CLK_PERI_SPI0 26
|
||||
#define CLK_PERI_SPI 27
|
||||
#define CLK_PERI_I2C5 28
|
||||
#define CLK_PERI_SPI2 29
|
||||
#define CLK_PERI_SPI3 30
|
||||
#define CLK_PERI_SPI5 31
|
||||
#define CLK_PERI_UART4 32
|
||||
#define CLK_PERI_SFLASH 33
|
||||
#define CLK_PERI_GMAC 34
|
||||
#define CLK_PERI_PCIE0 35
|
||||
#define CLK_PERI_PCIE1 36
|
||||
#define CLK_PERI_GMAC_PCLK 37
|
||||
#define CLK_PERI_MSDC50_0_EN 38
|
||||
#define CLK_PERI_MSDC30_1_EN 39
|
||||
#define CLK_PERI_MSDC30_2_EN 40
|
||||
#define CLK_PERI_MSDC30_3_EN 41
|
||||
#define CLK_PERI_MSDC50_0_HCLK_EN 42
|
||||
#define CLK_PERI_MSDC50_3_HCLK_EN 43
|
||||
#define CLK_PERI_NR_CLK 44
|
||||
|
||||
/* MCUCFG */
|
||||
|
||||
#define CLK_MCU_MP0_SEL 0
|
||||
#define CLK_MCU_MP2_SEL 1
|
||||
#define CLK_MCU_BUS_SEL 2
|
||||
#define CLK_MCU_NR_CLK 3
|
||||
|
||||
/* MFGCFG */
|
||||
|
||||
#define CLK_MFG_BG3D 0
|
||||
#define CLK_MFG_NR_CLK 1
|
||||
|
||||
/* MMSYS */
|
||||
|
||||
#define CLK_MM_SMI_COMMON 0
|
||||
#define CLK_MM_SMI_LARB0 1
|
||||
#define CLK_MM_CAM_MDP 2
|
||||
#define CLK_MM_MDP_RDMA0 3
|
||||
#define CLK_MM_MDP_RDMA1 4
|
||||
#define CLK_MM_MDP_RSZ0 5
|
||||
#define CLK_MM_MDP_RSZ1 6
|
||||
#define CLK_MM_MDP_RSZ2 7
|
||||
#define CLK_MM_MDP_TDSHP0 8
|
||||
#define CLK_MM_MDP_TDSHP1 9
|
||||
#define CLK_MM_MDP_CROP 10
|
||||
#define CLK_MM_MDP_WDMA 11
|
||||
#define CLK_MM_MDP_WROT0 12
|
||||
#define CLK_MM_MDP_WROT1 13
|
||||
#define CLK_MM_FAKE_ENG 14
|
||||
#define CLK_MM_MUTEX_32K 15
|
||||
#define CLK_MM_DISP_OVL0 16
|
||||
#define CLK_MM_DISP_OVL1 17
|
||||
#define CLK_MM_DISP_RDMA0 18
|
||||
#define CLK_MM_DISP_RDMA1 19
|
||||
#define CLK_MM_DISP_RDMA2 20
|
||||
#define CLK_MM_DISP_WDMA0 21
|
||||
#define CLK_MM_DISP_WDMA1 22
|
||||
#define CLK_MM_DISP_COLOR0 23
|
||||
#define CLK_MM_DISP_COLOR1 24
|
||||
#define CLK_MM_DISP_AAL 25
|
||||
#define CLK_MM_DISP_GAMMA 26
|
||||
#define CLK_MM_DISP_UFOE 27
|
||||
#define CLK_MM_DISP_SPLIT0 28
|
||||
#define CLK_MM_DISP_OD 29
|
||||
#define CLK_MM_DISP_PWM0_MM 30
|
||||
#define CLK_MM_DISP_PWM0_26M 31
|
||||
#define CLK_MM_DISP_PWM1_MM 32
|
||||
#define CLK_MM_DISP_PWM1_26M 33
|
||||
#define CLK_MM_DSI0_ENGINE 34
|
||||
#define CLK_MM_DSI0_DIGITAL 35
|
||||
#define CLK_MM_DSI1_ENGINE 36
|
||||
#define CLK_MM_DSI1_DIGITAL 37
|
||||
#define CLK_MM_DPI_PIXEL 38
|
||||
#define CLK_MM_DPI_ENGINE 39
|
||||
#define CLK_MM_DPI1_PIXEL 40
|
||||
#define CLK_MM_DPI1_ENGINE 41
|
||||
#define CLK_MM_LVDS_PIXEL 42
|
||||
#define CLK_MM_LVDS_CTS 43
|
||||
#define CLK_MM_SMI_LARB4 44
|
||||
#define CLK_MM_SMI_COMMON1 45
|
||||
#define CLK_MM_SMI_LARB5 46
|
||||
#define CLK_MM_MDP_RDMA2 47
|
||||
#define CLK_MM_MDP_TDSHP2 48
|
||||
#define CLK_MM_DISP_OVL2 49
|
||||
#define CLK_MM_DISP_WDMA2 50
|
||||
#define CLK_MM_DISP_COLOR2 51
|
||||
#define CLK_MM_DISP_AAL1 52
|
||||
#define CLK_MM_DISP_OD1 53
|
||||
#define CLK_MM_LVDS1_PIXEL 54
|
||||
#define CLK_MM_LVDS1_CTS 55
|
||||
#define CLK_MM_SMI_LARB7 56
|
||||
#define CLK_MM_MDP_RDMA3 57
|
||||
#define CLK_MM_MDP_WROT2 58
|
||||
#define CLK_MM_DSI2 59
|
||||
#define CLK_MM_DSI2_DIGITAL 60
|
||||
#define CLK_MM_DSI3 61
|
||||
#define CLK_MM_DSI3_DIGITAL 62
|
||||
#define CLK_MM_NR_CLK 63
|
||||
|
||||
/* IMGSYS */
|
||||
|
||||
#define CLK_IMG_SMI_LARB2 0
|
||||
#define CLK_IMG_SENINF_SCAM_EN 1
|
||||
#define CLK_IMG_SENINF_CAM_EN 2
|
||||
#define CLK_IMG_CAM_SV_EN 3
|
||||
#define CLK_IMG_CAM_SV1_EN 4
|
||||
#define CLK_IMG_CAM_SV2_EN 5
|
||||
#define CLK_IMG_NR_CLK 6
|
||||
|
||||
/* BDPSYS */
|
||||
|
||||
#define CLK_BDP_BRIDGE_B 0
|
||||
#define CLK_BDP_BRIDGE_DRAM 1
|
||||
#define CLK_BDP_LARB_DRAM 2
|
||||
#define CLK_BDP_WR_CHANNEL_VDI_PXL 3
|
||||
#define CLK_BDP_WR_CHANNEL_VDI_DRAM 4
|
||||
#define CLK_BDP_WR_CHANNEL_VDI_B 5
|
||||
#define CLK_BDP_MT_B 6
|
||||
#define CLK_BDP_DISPFMT_27M 7
|
||||
#define CLK_BDP_DISPFMT_27M_VDOUT 8
|
||||
#define CLK_BDP_DISPFMT_27_74_74 9
|
||||
#define CLK_BDP_DISPFMT_2FS 10
|
||||
#define CLK_BDP_DISPFMT_2FS_2FS74_148 11
|
||||
#define CLK_BDP_DISPFMT_B 12
|
||||
#define CLK_BDP_VDO_DRAM 13
|
||||
#define CLK_BDP_VDO_2FS 14
|
||||
#define CLK_BDP_VDO_B 15
|
||||
#define CLK_BDP_WR_CHANNEL_DI_PXL 16
|
||||
#define CLK_BDP_WR_CHANNEL_DI_DRAM 17
|
||||
#define CLK_BDP_WR_CHANNEL_DI_B 18
|
||||
#define CLK_BDP_NR_AGENT 19
|
||||
#define CLK_BDP_NR_DRAM 20
|
||||
#define CLK_BDP_NR_B 21
|
||||
#define CLK_BDP_BRIDGE_RT_B 22
|
||||
#define CLK_BDP_BRIDGE_RT_DRAM 23
|
||||
#define CLK_BDP_LARB_RT_DRAM 24
|
||||
#define CLK_BDP_TVD_TDC 25
|
||||
#define CLK_BDP_TVD_54 26
|
||||
#define CLK_BDP_TVD_CBUS 27
|
||||
#define CLK_BDP_NR_CLK 28
|
||||
|
||||
/* VDECSYS */
|
||||
|
||||
#define CLK_VDEC_CKEN 0
|
||||
#define CLK_VDEC_LARB1_CKEN 1
|
||||
#define CLK_VDEC_IMGRZ_CKEN 2
|
||||
#define CLK_VDEC_NR_CLK 3
|
||||
|
||||
/* VENCSYS */
|
||||
|
||||
#define CLK_VENC_SMI_COMMON_CON 0
|
||||
#define CLK_VENC_VENC 1
|
||||
#define CLK_VENC_SMI_LARB6 2
|
||||
#define CLK_VENC_NR_CLK 3
|
||||
|
||||
/* JPGDECSYS */
|
||||
|
||||
#define CLK_JPGDEC_JPGDEC1 0
|
||||
#define CLK_JPGDEC_JPGDEC 1
|
||||
#define CLK_JPGDEC_NR_CLK 2
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT2712_H */
|
||||
289
include/dt-bindings/clock/mt7622-clk.h
Normal file
289
include/dt-bindings/clock/mt7622-clk.h
Normal file
@ -0,0 +1,289 @@
|
||||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Chen Zhong <chen.zhong@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_MT7622_H
|
||||
#define _DT_BINDINGS_CLK_MT7622_H
|
||||
|
||||
/* TOPCKGEN */
|
||||
|
||||
#define CLK_TOP_TO_U2_PHY 0
|
||||
#define CLK_TOP_TO_U2_PHY_1P 1
|
||||
#define CLK_TOP_PCIE0_PIPE_EN 2
|
||||
#define CLK_TOP_PCIE1_PIPE_EN 3
|
||||
#define CLK_TOP_SSUSB_TX250M 4
|
||||
#define CLK_TOP_SSUSB_EQ_RX250M 5
|
||||
#define CLK_TOP_SSUSB_CDR_REF 6
|
||||
#define CLK_TOP_SSUSB_CDR_FB 7
|
||||
#define CLK_TOP_SATA_ASIC 8
|
||||
#define CLK_TOP_SATA_RBC 9
|
||||
#define CLK_TOP_TO_USB3_SYS 10
|
||||
#define CLK_TOP_P1_1MHZ 11
|
||||
#define CLK_TOP_4MHZ 12
|
||||
#define CLK_TOP_P0_1MHZ 13
|
||||
#define CLK_TOP_TXCLK_SRC_PRE 14
|
||||
#define CLK_TOP_RTC 15
|
||||
#define CLK_TOP_MEMPLL 16
|
||||
#define CLK_TOP_DMPLL 17
|
||||
#define CLK_TOP_SYSPLL_D2 18
|
||||
#define CLK_TOP_SYSPLL1_D2 19
|
||||
#define CLK_TOP_SYSPLL1_D4 20
|
||||
#define CLK_TOP_SYSPLL1_D8 21
|
||||
#define CLK_TOP_SYSPLL2_D4 22
|
||||
#define CLK_TOP_SYSPLL2_D8 23
|
||||
#define CLK_TOP_SYSPLL_D5 24
|
||||
#define CLK_TOP_SYSPLL3_D2 25
|
||||
#define CLK_TOP_SYSPLL3_D4 26
|
||||
#define CLK_TOP_SYSPLL4_D2 27
|
||||
#define CLK_TOP_SYSPLL4_D4 28
|
||||
#define CLK_TOP_SYSPLL4_D16 29
|
||||
#define CLK_TOP_UNIVPLL 30
|
||||
#define CLK_TOP_UNIVPLL_D2 31
|
||||
#define CLK_TOP_UNIVPLL1_D2 32
|
||||
#define CLK_TOP_UNIVPLL1_D4 33
|
||||
#define CLK_TOP_UNIVPLL1_D8 34
|
||||
#define CLK_TOP_UNIVPLL1_D16 35
|
||||
#define CLK_TOP_UNIVPLL2_D2 36
|
||||
#define CLK_TOP_UNIVPLL2_D4 37
|
||||
#define CLK_TOP_UNIVPLL2_D8 38
|
||||
#define CLK_TOP_UNIVPLL2_D16 39
|
||||
#define CLK_TOP_UNIVPLL_D5 40
|
||||
#define CLK_TOP_UNIVPLL3_D2 41
|
||||
#define CLK_TOP_UNIVPLL3_D4 42
|
||||
#define CLK_TOP_UNIVPLL3_D16 43
|
||||
#define CLK_TOP_UNIVPLL_D7 44
|
||||
#define CLK_TOP_UNIVPLL_D80_D4 45
|
||||
#define CLK_TOP_UNIV48M 46
|
||||
#define CLK_TOP_SGMIIPLL 47
|
||||
#define CLK_TOP_SGMIIPLL_D2 48
|
||||
#define CLK_TOP_AUD1PLL 49
|
||||
#define CLK_TOP_AUD2PLL 50
|
||||
#define CLK_TOP_AUD_I2S2_MCK 51
|
||||
#define CLK_TOP_TO_USB3_REF 52
|
||||
#define CLK_TOP_PCIE1_MAC_EN 53
|
||||
#define CLK_TOP_PCIE0_MAC_EN 54
|
||||
#define CLK_TOP_ETH_500M 55
|
||||
#define CLK_TOP_AXI_SEL 56
|
||||
#define CLK_TOP_MEM_SEL 57
|
||||
#define CLK_TOP_DDRPHYCFG_SEL 58
|
||||
#define CLK_TOP_ETH_SEL 59
|
||||
#define CLK_TOP_PWM_SEL 60
|
||||
#define CLK_TOP_F10M_REF_SEL 61
|
||||
#define CLK_TOP_NFI_INFRA_SEL 62
|
||||
#define CLK_TOP_FLASH_SEL 63
|
||||
#define CLK_TOP_UART_SEL 64
|
||||
#define CLK_TOP_SPI0_SEL 65
|
||||
#define CLK_TOP_SPI1_SEL 66
|
||||
#define CLK_TOP_MSDC50_0_SEL 67
|
||||
#define CLK_TOP_MSDC30_0_SEL 68
|
||||
#define CLK_TOP_MSDC30_1_SEL 69
|
||||
#define CLK_TOP_A1SYS_HP_SEL 70
|
||||
#define CLK_TOP_A2SYS_HP_SEL 71
|
||||
#define CLK_TOP_INTDIR_SEL 72
|
||||
#define CLK_TOP_AUD_INTBUS_SEL 73
|
||||
#define CLK_TOP_PMICSPI_SEL 74
|
||||
#define CLK_TOP_SCP_SEL 75
|
||||
#define CLK_TOP_ATB_SEL 76
|
||||
#define CLK_TOP_HIF_SEL 77
|
||||
#define CLK_TOP_AUDIO_SEL 78
|
||||
#define CLK_TOP_U2_SEL 79
|
||||
#define CLK_TOP_AUD1_SEL 80
|
||||
#define CLK_TOP_AUD2_SEL 81
|
||||
#define CLK_TOP_IRRX_SEL 82
|
||||
#define CLK_TOP_IRTX_SEL 83
|
||||
#define CLK_TOP_ASM_L_SEL 84
|
||||
#define CLK_TOP_ASM_M_SEL 85
|
||||
#define CLK_TOP_ASM_H_SEL 86
|
||||
#define CLK_TOP_APLL1_SEL 87
|
||||
#define CLK_TOP_APLL2_SEL 88
|
||||
#define CLK_TOP_I2S0_MCK_SEL 89
|
||||
#define CLK_TOP_I2S1_MCK_SEL 90
|
||||
#define CLK_TOP_I2S2_MCK_SEL 91
|
||||
#define CLK_TOP_I2S3_MCK_SEL 92
|
||||
#define CLK_TOP_APLL1_DIV 93
|
||||
#define CLK_TOP_APLL2_DIV 94
|
||||
#define CLK_TOP_I2S0_MCK_DIV 95
|
||||
#define CLK_TOP_I2S1_MCK_DIV 96
|
||||
#define CLK_TOP_I2S2_MCK_DIV 97
|
||||
#define CLK_TOP_I2S3_MCK_DIV 98
|
||||
#define CLK_TOP_A1SYS_HP_DIV 99
|
||||
#define CLK_TOP_A2SYS_HP_DIV 100
|
||||
#define CLK_TOP_APLL1_DIV_PD 101
|
||||
#define CLK_TOP_APLL2_DIV_PD 102
|
||||
#define CLK_TOP_I2S0_MCK_DIV_PD 103
|
||||
#define CLK_TOP_I2S1_MCK_DIV_PD 104
|
||||
#define CLK_TOP_I2S2_MCK_DIV_PD 105
|
||||
#define CLK_TOP_I2S3_MCK_DIV_PD 106
|
||||
#define CLK_TOP_A1SYS_HP_DIV_PD 107
|
||||
#define CLK_TOP_A2SYS_HP_DIV_PD 108
|
||||
#define CLK_TOP_NR_CLK 109
|
||||
|
||||
/* INFRACFG */
|
||||
|
||||
#define CLK_INFRA_MUX1_SEL 0
|
||||
#define CLK_INFRA_DBGCLK_PD 1
|
||||
#define CLK_INFRA_AUDIO_PD 2
|
||||
#define CLK_INFRA_IRRX_PD 3
|
||||
#define CLK_INFRA_APXGPT_PD 4
|
||||
#define CLK_INFRA_PMIC_PD 5
|
||||
#define CLK_INFRA_TRNG 6
|
||||
#define CLK_INFRA_NR_CLK 7
|
||||
|
||||
/* PERICFG */
|
||||
|
||||
#define CLK_PERIBUS_SEL 0
|
||||
#define CLK_PERI_THERM_PD 1
|
||||
#define CLK_PERI_PWM1_PD 2
|
||||
#define CLK_PERI_PWM2_PD 3
|
||||
#define CLK_PERI_PWM3_PD 4
|
||||
#define CLK_PERI_PWM4_PD 5
|
||||
#define CLK_PERI_PWM5_PD 6
|
||||
#define CLK_PERI_PWM6_PD 7
|
||||
#define CLK_PERI_PWM7_PD 8
|
||||
#define CLK_PERI_PWM_PD 9
|
||||
#define CLK_PERI_AP_DMA_PD 10
|
||||
#define CLK_PERI_MSDC30_0_PD 11
|
||||
#define CLK_PERI_MSDC30_1_PD 12
|
||||
#define CLK_PERI_UART0_PD 13
|
||||
#define CLK_PERI_UART1_PD 14
|
||||
#define CLK_PERI_UART2_PD 15
|
||||
#define CLK_PERI_UART3_PD 16
|
||||
#define CLK_PERI_UART4_PD 17
|
||||
#define CLK_PERI_BTIF_PD 18
|
||||
#define CLK_PERI_I2C0_PD 19
|
||||
#define CLK_PERI_I2C1_PD 20
|
||||
#define CLK_PERI_I2C2_PD 21
|
||||
#define CLK_PERI_SPI1_PD 22
|
||||
#define CLK_PERI_AUXADC_PD 23
|
||||
#define CLK_PERI_SPI0_PD 24
|
||||
#define CLK_PERI_SNFI_PD 25
|
||||
#define CLK_PERI_NFI_PD 26
|
||||
#define CLK_PERI_NFIECC_PD 27
|
||||
#define CLK_PERI_FLASH_PD 28
|
||||
#define CLK_PERI_IRTX_PD 29
|
||||
#define CLK_PERI_NR_CLK 30
|
||||
|
||||
/* APMIXEDSYS */
|
||||
|
||||
#define CLK_APMIXED_ARMPLL 0
|
||||
#define CLK_APMIXED_MAINPLL 1
|
||||
#define CLK_APMIXED_UNIV2PLL 2
|
||||
#define CLK_APMIXED_ETH1PLL 3
|
||||
#define CLK_APMIXED_ETH2PLL 4
|
||||
#define CLK_APMIXED_AUD1PLL 5
|
||||
#define CLK_APMIXED_AUD2PLL 6
|
||||
#define CLK_APMIXED_TRGPLL 7
|
||||
#define CLK_APMIXED_SGMIPLL 8
|
||||
#define CLK_APMIXED_MAIN_CORE_EN 9
|
||||
#define CLK_APMIXED_NR_CLK 10
|
||||
|
||||
/* AUDIOSYS */
|
||||
|
||||
#define CLK_AUDIO_AFE 0
|
||||
#define CLK_AUDIO_HDMI 1
|
||||
#define CLK_AUDIO_SPDF 2
|
||||
#define CLK_AUDIO_APLL 3
|
||||
#define CLK_AUDIO_I2SIN1 4
|
||||
#define CLK_AUDIO_I2SIN2 5
|
||||
#define CLK_AUDIO_I2SIN3 6
|
||||
#define CLK_AUDIO_I2SIN4 7
|
||||
#define CLK_AUDIO_I2SO1 8
|
||||
#define CLK_AUDIO_I2SO2 9
|
||||
#define CLK_AUDIO_I2SO3 10
|
||||
#define CLK_AUDIO_I2SO4 11
|
||||
#define CLK_AUDIO_ASRCI1 12
|
||||
#define CLK_AUDIO_ASRCI2 13
|
||||
#define CLK_AUDIO_ASRCO1 14
|
||||
#define CLK_AUDIO_ASRCO2 15
|
||||
#define CLK_AUDIO_INTDIR 16
|
||||
#define CLK_AUDIO_A1SYS 17
|
||||
#define CLK_AUDIO_A2SYS 18
|
||||
#define CLK_AUDIO_UL1 19
|
||||
#define CLK_AUDIO_UL2 20
|
||||
#define CLK_AUDIO_UL3 21
|
||||
#define CLK_AUDIO_UL4 22
|
||||
#define CLK_AUDIO_UL5 23
|
||||
#define CLK_AUDIO_UL6 24
|
||||
#define CLK_AUDIO_DL1 25
|
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#define CLK_AUDIO_DL2 26
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#define CLK_AUDIO_DL3 27
|
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#define CLK_AUDIO_DL4 28
|
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#define CLK_AUDIO_DL5 29
|
||||
#define CLK_AUDIO_DL6 30
|
||||
#define CLK_AUDIO_DLMCH 31
|
||||
#define CLK_AUDIO_ARB1 32
|
||||
#define CLK_AUDIO_AWB 33
|
||||
#define CLK_AUDIO_AWB2 34
|
||||
#define CLK_AUDIO_DAI 35
|
||||
#define CLK_AUDIO_MOD 36
|
||||
#define CLK_AUDIO_ASRCI3 37
|
||||
#define CLK_AUDIO_ASRCI4 38
|
||||
#define CLK_AUDIO_ASRCO3 39
|
||||
#define CLK_AUDIO_ASRCO4 40
|
||||
#define CLK_AUDIO_MEM_ASRC1 41
|
||||
#define CLK_AUDIO_MEM_ASRC2 42
|
||||
#define CLK_AUDIO_MEM_ASRC3 43
|
||||
#define CLK_AUDIO_MEM_ASRC4 44
|
||||
#define CLK_AUDIO_MEM_ASRC5 45
|
||||
#define CLK_AUDIO_NR_CLK 46
|
||||
|
||||
/* SSUSBSYS */
|
||||
|
||||
#define CLK_SSUSB_U2_PHY_1P_EN 0
|
||||
#define CLK_SSUSB_U2_PHY_EN 1
|
||||
#define CLK_SSUSB_REF_EN 2
|
||||
#define CLK_SSUSB_SYS_EN 3
|
||||
#define CLK_SSUSB_MCU_EN 4
|
||||
#define CLK_SSUSB_DMA_EN 5
|
||||
#define CLK_SSUSB_NR_CLK 6
|
||||
|
||||
/* PCIESYS */
|
||||
|
||||
#define CLK_PCIE_P1_AUX_EN 0
|
||||
#define CLK_PCIE_P1_OBFF_EN 1
|
||||
#define CLK_PCIE_P1_AHB_EN 2
|
||||
#define CLK_PCIE_P1_AXI_EN 3
|
||||
#define CLK_PCIE_P1_MAC_EN 4
|
||||
#define CLK_PCIE_P1_PIPE_EN 5
|
||||
#define CLK_PCIE_P0_AUX_EN 6
|
||||
#define CLK_PCIE_P0_OBFF_EN 7
|
||||
#define CLK_PCIE_P0_AHB_EN 8
|
||||
#define CLK_PCIE_P0_AXI_EN 9
|
||||
#define CLK_PCIE_P0_MAC_EN 10
|
||||
#define CLK_PCIE_P0_PIPE_EN 11
|
||||
#define CLK_SATA_AHB_EN 12
|
||||
#define CLK_SATA_AXI_EN 13
|
||||
#define CLK_SATA_ASIC_EN 14
|
||||
#define CLK_SATA_RBC_EN 15
|
||||
#define CLK_SATA_PM_EN 16
|
||||
#define CLK_PCIE_NR_CLK 17
|
||||
|
||||
/* ETHSYS */
|
||||
|
||||
#define CLK_ETH_HSDMA_EN 0
|
||||
#define CLK_ETH_ESW_EN 1
|
||||
#define CLK_ETH_GP2_EN 2
|
||||
#define CLK_ETH_GP1_EN 3
|
||||
#define CLK_ETH_GP0_EN 4
|
||||
#define CLK_ETH_NR_CLK 5
|
||||
|
||||
/* SGMIISYS */
|
||||
|
||||
#define CLK_SGMII_TX250M_EN 0
|
||||
#define CLK_SGMII_RX250M_EN 1
|
||||
#define CLK_SGMII_CDR_REF 2
|
||||
#define CLK_SGMII_CDR_FB 3
|
||||
#define CLK_SGMII_NR_CLK 4
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MT7622_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user