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Snap for 8105527 from 5fe9d9e1c9 to android12-5.10-keystone-qcom-release

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Change-Id: Ic7839be67bcf4ccba1278833da3e0276c4d5a640
This commit is contained in:
Android Build Coastguard Worker 2022-01-22 01:00:22 +00:00
commit 495c24a231
1589 changed files with 18292 additions and 10576 deletions
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6
Documentation/admin-guide/devices.txt
View File

@ -3003,10 +3003,10 @@
65 = /dev/infiniband/issm1 Second InfiniBand IsSM device
...
127 = /dev/infiniband/issm63 63rd InfiniBand IsSM device
128 = /dev/infiniband/uverbs0 First InfiniBand verbs device
129 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
192 = /dev/infiniband/uverbs0 First InfiniBand verbs device
193 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
...
159 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
223 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
232 char Biometric Devices
0 = /dev/biometric/sensor0/fingerprint first fingerprint sensor on first device

7
Documentation/admin-guide/kernel-parameters.txt
View File

@ -6085,6 +6085,13 @@
improve timer resolution at the expense of processing
more timer interrupts.
xen.balloon_boot_timeout= [XEN]
The time (in seconds) to wait before giving up to boot
in case initial ballooning fails to free enough memory.
Applies only when running as HVM or PVH guest and
started with less memory configured than allowed at
max. Default is 180.
xen.event_eoi_delay= [XEN]
How long to delay EOI handling in case of event
storms (jiffies). Default is 10.

2
Documentation/devicetree/bindings/arm/tegra.yaml
View File

@ -54,7 +54,7 @@ properties:
- const: toradex,apalis_t30
- const: nvidia,tegra30
- items:
- const: toradex,apalis_t30-eval-v1.1
- const: toradex,apalis_t30-v1.1-eval
- const: toradex,apalis_t30-eval
- const: toradex,apalis_t30-v1.1
- const: toradex,apalis_t30

2
Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
View File

@ -18,7 +18,7 @@ properties:
const: ti,sn65dsi86
reg:
const: 0x2d
enum: [ 0x2c, 0x2d ]
enable-gpios:
maxItems: 1

2
Documentation/devicetree/bindings/mtd/gpmc-nand.txt
View File

@ -122,7 +122,7 @@ on various other factors also like;
so the device should have enough free bytes available its OOB/Spare
area to accommodate ECC for entire page. In general following expression
helps in determining if given device can accommodate ECC syndrome:
"2 + (PAGESIZE / 512) * ECC_BYTES" >= OOBSIZE"
"2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE"
where
OOBSIZE number of bytes in OOB/spare area
PAGESIZE number of bytes in main-area of device page

8
Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
View File

@ -43,19 +43,19 @@ group emmc_nb
group pwm0
- pin 11 (GPIO1-11)
- functions pwm, gpio
- functions pwm, led, gpio
group pwm1
- pin 12
- functions pwm, gpio
- functions pwm, led, gpio
group pwm2
- pin 13
- functions pwm, gpio
- functions pwm, led, gpio
group pwm3
- pin 14
- functions pwm, gpio
- functions pwm, led, gpio
group pmic1
- pin 7

23
Documentation/devicetree/bindings/regulator/samsung,s5m8767.txt
View File

@ -13,6 +13,14 @@ common regulator binding documented in:
Required properties of the main device node (the parent!):
- s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used
for selecting GPIO DVS lines. It is one-to-one mapped to dvs gpio lines.
[1] If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
property is specified, then all the eight voltage values for the
's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified.
Optional properties of the main device node (the parent!):
- s5m8767,pmic-buck2-dvs-voltage: A set of 8 voltage values in micro-volt (uV)
units for buck2 when changing voltage using gpio dvs. Refer to [1] below
for additional information.
@ -25,26 +33,13 @@ Required properties of the main device node (the parent!):
units for buck4 when changing voltage using gpio dvs. Refer to [1] below
for additional information.
- s5m8767,pmic-buck-ds-gpios: GPIO specifiers for three host gpio's used
for selecting GPIO DVS lines. It is one-to-one mapped to dvs gpio lines.
[1] If none of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
property is specified, the 's5m8767,pmic-buck[2/3/4]-dvs-voltage'
property should specify atleast one voltage level (which would be a
safe operating voltage).
If either of the 's5m8767,pmic-buck[2/3/4]-uses-gpio-dvs' optional
property is specified, then all the eight voltage values for the
's5m8767,pmic-buck[2/3/4]-dvs-voltage' should be specified.
Optional properties of the main device node (the parent!):
- s5m8767,pmic-buck2-uses-gpio-dvs: 'buck2' can be controlled by gpio dvs.
- s5m8767,pmic-buck3-uses-gpio-dvs: 'buck3' can be controlled by gpio dvs.
- s5m8767,pmic-buck4-uses-gpio-dvs: 'buck4' can be controlled by gpio dvs.
Additional properties required if either of the optional properties are used:
- s5m8767,pmic-buck234-default-dvs-idx: Default voltage setting selected from
- s5m8767,pmic-buck-default-dvs-idx: Default voltage setting selected from
the possible 8 options selectable by the dvs gpios. The value of this
property should be between 0 and 7. If not specified or if out of range, the
default value of this property is set to 0.

10
Documentation/filesystems/fscrypt.rst
View File

@ -176,11 +176,11 @@ Master Keys
Each encrypted directory tree is protected by a *master key*. Master
keys can be up to 64 bytes long, and must be at least as long as the
greater of the key length needed by the contents and filenames
encryption modes being used. For example, if AES-256-XTS is used for
contents encryption, the master key must be 64 bytes (512 bits). Note
that the XTS mode is defined to require a key twice as long as that
required by the underlying block cipher.
greater of the security strength of the contents and filenames
encryption modes being used. For example, if any AES-256 mode is
used, the master key must be at least 256 bits, i.e. 32 bytes. A
stricter requirement applies if the key is used by a v1 encryption
policy and AES-256-XTS is used; such keys must be 64 bytes.
To "unlock" an encrypted directory tree, userspace must provide the
appropriate master key. There can be any number of master keys, each

2
Makefile
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
VERSION = 5
PATCHLEVEL = 10
SUBLEVEL = 66
SUBLEVEL = 81
EXTRAVERSION =
NAME = Dare mighty things

6012
android/abi_gki_aarch64.xml
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File diff suppressed because it is too large Load Diff

3
arch/Kconfig
View File

@ -1146,6 +1146,9 @@ config RELR
config ARCH_HAS_MEM_ENCRYPT
bool
config ARCH_HAS_CC_PLATFORM
bool
config HAVE_SPARSE_SYSCALL_NR
bool
help

6
arch/alpha/include/asm/io.h
View File

@ -60,7 +60,7 @@ extern inline void set_hae(unsigned long new_hae)
* Change virtual addresses to physical addresses and vv.
*/
#ifdef USE_48_BIT_KSEG
static inline unsigned long virt_to_phys(void *address)
static inline unsigned long virt_to_phys(volatile void *address)
{
return (unsigned long)address - IDENT_ADDR;
}
@ -70,7 +70,7 @@ static inline void * phys_to_virt(unsigned long address)
return (void *) (address + IDENT_ADDR);
}
#else
static inline unsigned long virt_to_phys(void *address)
static inline unsigned long virt_to_phys(volatile void *address)
{
unsigned long phys = (unsigned long)address;
@ -106,7 +106,7 @@ static inline void * phys_to_virt(unsigned long address)
extern unsigned long __direct_map_base;
extern unsigned long __direct_map_size;
static inline unsigned long __deprecated virt_to_bus(void *address)
static inline unsigned long __deprecated virt_to_bus(volatile void *address)
{
unsigned long phys = virt_to_phys(address);
unsigned long bus = phys + __direct_map_base;

2
arch/arc/mm/cache.c
View File

@ -1123,7 +1123,7 @@ void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
clear_page(to);
clear_bit(PG_dc_clean, &page->flags);
}
EXPORT_SYMBOL(clear_user_page);
/**********************************************************************
* Explicit Cache flush request from user space via syscall

1
arch/arm/Kconfig
View File

@ -88,6 +88,7 @@ config ARM
select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
select HAVE_FUNCTION_TRACER if !XIP_KERNEL
select HAVE_FUTEX_CMPXCHG if FUTEX
select HAVE_GCC_PLUGINS
select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
select HAVE_IDE if PCI || ISA || PCMCIA

22
arch/arm/Makefile
View File

@ -60,15 +60,15 @@ KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra)
# Note that GCC does not numerically define an architecture version
# macro, but instead defines a whole series of macros which makes
# testing for a specific architecture or later rather impossible.
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m -Wa,-march=armv7-m
arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6)
arch-$(CONFIG_CPU_32v7M) =-D__LINUX_ARM_ARCH__=7 -march=armv7-m
arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 -march=armv7-a
arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 -march=armv6
# Only override the compiler option if ARMv6. The ARMv6K extensions are
# always available in ARMv7
ifeq ($(CONFIG_CPU_32v6),y)
arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k)
arch-$(CONFIG_CPU_32v6K) =-D__LINUX_ARM_ARCH__=6 -march=armv6k
endif
arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 $(call cc-option,-march=armv5te,-march=armv4t)
arch-$(CONFIG_CPU_32v5) =-D__LINUX_ARM_ARCH__=5 -march=armv5te
arch-$(CONFIG_CPU_32v4T) =-D__LINUX_ARM_ARCH__=4 -march=armv4t
arch-$(CONFIG_CPU_32v4) =-D__LINUX_ARM_ARCH__=4 -march=armv4
arch-$(CONFIG_CPU_32v3) =-D__LINUX_ARM_ARCH__=3 -march=armv3m
@ -82,7 +82,7 @@ tune-$(CONFIG_CPU_ARM720T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM740T) =-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM9TDMI) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM940T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM946E) =$(call cc-option,-mtune=arm9e,-mtune=arm9tdmi)
tune-$(CONFIG_CPU_ARM946E) =-mtune=arm9e
tune-$(CONFIG_CPU_ARM920T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM922T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_ARM925T) =-mtune=arm9tdmi
@ -90,11 +90,11 @@ tune-$(CONFIG_CPU_ARM926T) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_FA526) =-mtune=arm9tdmi
tune-$(CONFIG_CPU_SA110) =-mtune=strongarm110
tune-$(CONFIG_CPU_SA1100) =-mtune=strongarm1100
tune-$(CONFIG_CPU_XSCALE) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
tune-$(CONFIG_CPU_XSC3) =$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
tune-$(CONFIG_CPU_FEROCEON) =$(call cc-option,-mtune=marvell-f,-mtune=xscale)
tune-$(CONFIG_CPU_V6) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
tune-$(CONFIG_CPU_V6K) =$(call cc-option,-mtune=arm1136j-s,-mtune=strongarm)
tune-$(CONFIG_CPU_XSCALE) =-mtune=xscale
tune-$(CONFIG_CPU_XSC3) =-mtune=xscale
tune-$(CONFIG_CPU_FEROCEON) =-mtune=xscale
tune-$(CONFIG_CPU_V6) =-mtune=arm1136j-s
tune-$(CONFIG_CPU_V6K) =-mtune=arm1136j-s
# Evaluate tune cc-option calls now
tune-y := $(tune-y)

2
arch/arm/boot/compressed/Makefile
View File

@ -84,6 +84,8 @@ compress-$(CONFIG_KERNEL_LZ4) = lz4
libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o
ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
CFLAGS_REMOVE_atags_to_fdt.o += -Wframe-larger-than=${CONFIG_FRAME_WARN}
CFLAGS_atags_to_fdt.o += -Wframe-larger-than=1280
OBJS += $(libfdt_objs) atags_to_fdt.o
endif

3
arch/arm/boot/compressed/decompress.c
View File

@ -47,7 +47,10 @@ extern char * strchrnul(const char *, int);
#endif
#ifdef CONFIG_KERNEL_XZ
/* Prevent KASAN override of string helpers in decompressor */
#undef memmove
#define memmove memmove
#undef memcpy
#define memcpy memcpy
#include "../../../../lib/decompress_unxz.c"
#endif

2
arch/arm/boot/dts/at91-kizbox3_common.dtsi
View File

@ -336,7 +336,7 @@ &pwm0 {
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {

2
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@ -662,7 +662,7 @@ &rtt {
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
status = "okay";
input@0 {

3
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
View File

@ -71,7 +71,6 @@ apb {
isc: isc@f0008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isc_base &pinctrl_isc_data_8bit &pinctrl_isc_data_9_10 &pinctrl_isc_data_11_12>;
status = "okay";
};
qspi1: spi@f0024000 {
@ -138,7 +137,7 @@ i2c3: i2c@600 {
};
shdwc@f8048010 {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {

2
arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
View File

@ -205,7 +205,7 @@ &sdmmc0 {
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {

2
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -693,7 +693,7 @@ &sdmmc0 {
};
&shutdown_controller {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {

2
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
View File

@ -203,7 +203,7 @@ i2c2: i2c@600 {
};
shdwc@f8048010 {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
input@0 {
reg = <0>;

2
arch/arm/boot/dts/at91-sama5d2_xplained.dts
View File

@ -347,7 +347,7 @@ i2c2: i2c@600 {
};
shdwc@f8048010 {
atmel,shdwc-debouncer = <976>;
debounce-delay-us = <976>;
atmel,wakeup-rtc-timer;
input@0 {

2
arch/arm/boot/dts/at91-tse850-3.dts
View File

@ -262,7 +262,7 @@ &pwm0 {
&macb1 {
status = "okay";
phy-mode = "rgmii";
phy-mode = "rmii";
#address-cells = <1>;
#size-cells = <0>;

11
arch/arm/boot/dts/bcm2711-rpi-4-b.dts
View File

@ -54,8 +54,8 @@ sd_io_1v8_reg: sd_io_1v8_reg {
regulator-always-on;
regulator-settling-time-us = <5000>;
gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
states = <1800000 0x1
3300000 0x0>;
states = <1800000 0x1>,
<3300000 0x0>;
status = "okay";
};
@ -255,15 +255,16 @@ phy1: ethernet-phy@1 {
};
&pcie0 {
pci@1,0 {
pci@0,0 {
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
reg = <0 0 0 0 0>;
usb@1,0 {
reg = <0x10000 0 0 0 0>;
usb@0,0 {
reg = <0 0 0 0 0>;
resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>;
};
};

4
arch/arm/boot/dts/bcm2711.dtsi
View File

@ -514,8 +514,8 @@ genet_mdio: mdio@e14 {
compatible = "brcm,genet-mdio-v5";
reg = <0xe14 0x8>;
reg-names = "mdio";
#address-cells = <0x0>;
#size-cells = <0x1>;
#address-cells = <0x1>;
#size-cells = <0x0>;
};
};
};

2
arch/arm/boot/dts/bcm4708-netgear-r6250.dts
View File

@ -20,7 +20,7 @@ chosen {
bootargs = "console=ttyS0,115200 earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
View File

@ -19,7 +19,7 @@ chosen {
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
View File

@ -19,7 +19,7 @@ chosen {
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;

2
arch/arm/boot/dts/bcm4709-linksys-ea9200.dts
View File

@ -16,7 +16,7 @@ chosen {
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-netgear-r7000.dts
View File

@ -19,7 +19,7 @@ chosen {
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-netgear-r8000.dts
View File

@ -30,7 +30,7 @@ chosen {
bootargs = "console=ttyS0,115200";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x08000000>;

2
arch/arm/boot/dts/bcm4709-tplink-archer-c9-v1.dts
View File

@ -15,7 +15,7 @@ chosen {
bootargs = "console=ttyS0,115200 earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

2
arch/arm/boot/dts/bcm47094-luxul-xwc-2000.dts
View File

@ -16,7 +16,7 @@ chosen {
bootargs = "earlycon";
};
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>,
<0x88000000 0x18000000>;

2
arch/arm/boot/dts/bcm53016-meraki-mr32.dts
View File

@ -20,7 +20,7 @@ chosen {
bootargs = " console=ttyS0,115200n8 earlycon";
};
memory {
memory@0 {
reg = <0x00000000 0x08000000>;
device_type = "memory";
};

2
arch/arm/boot/dts/bcm94708.dts
View File

@ -38,7 +38,7 @@ / {
model = "NorthStar SVK (BCM94708)";
compatible = "brcm,bcm94708", "brcm,bcm4708";
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

2
arch/arm/boot/dts/bcm94709.dts
View File

@ -38,7 +38,7 @@ / {
model = "NorthStar SVK (BCM94709)";
compatible = "brcm,bcm94709", "brcm,bcm4709", "brcm,bcm4708";
memory {
memory@0 {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};

4
arch/arm/boot/dts/imx53-m53menlo.dts
View File

@ -56,6 +56,7 @@ eth {
panel {
compatible = "edt,etm0700g0dh6";
pinctrl-0 = <&pinctrl_display_gpio>;
pinctrl-names = "default";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
port {
@ -76,8 +77,7 @@ reg_usbh1_vbus: regulator-usbh1-vbus {
regulator-name = "vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
gpio = <&gpio1 2 0>;
};
};

23
arch/arm/boot/dts/imx53-ppd.dts
View File

@ -70,6 +70,12 @@ cko2_11M: sgtl-clock-cko2 {
clock-frequency = <11289600>;
};
achc_24M: achc-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
sgtlsound: sound {
compatible = "fsl,imx53-cpuvo-sgtl5000",
"fsl,imx-audio-sgtl5000";
@ -313,16 +319,13 @@ &gpio4 11 GPIO_ACTIVE_LOW
&gpio4 12 GPIO_ACTIVE_LOW>;
status = "okay";
spidev0: spi@0 {
compatible = "ge,achc";
reg = <0>;
spi-max-frequency = <1000000>;
};
spidev1: spi@1 {
compatible = "ge,achc";
reg = <1>;
spi-max-frequency = <1000000>;
spidev0: spi@1 {
compatible = "ge,achc", "nxp,kinetis-k20";
reg = <1>, <0>;
vdd-supply = <&reg_3v3>;
vdda-supply = <&reg_3v3>;
clocks = <&achc_24M>;
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
};
gpioxra0: gpio@2 {

5
arch/arm/boot/dts/imx6dl-yapp4-common.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pwm/pwm.h>
/ {
@ -275,6 +276,7 @@ chan@0 {
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
chan@1 {
@ -282,6 +284,7 @@ chan@1 {
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
chan@2 {
@ -289,6 +292,7 @@ chan@2 {
led-cur = /bits/ 8 <0x20>;
max-cur = /bits/ 8 <0x60>;
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
chan@3 {
@ -296,6 +300,7 @@ chan@3 {
led-cur = /bits/ 8 <0x0>;
max-cur = /bits/ 8 <0x0>;
reg = <3>;
color = <LED_COLOR_ID_WHITE>;
};
};

11
arch/arm/boot/dts/imx6qdl-pico.dtsi
View File

@ -176,7 +176,18 @@ &fec {
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id";
phy-reset-gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@1 {
reg = <1>;
qca,clk-out-frequency = <125000000>;
};
};
};
&hdmi {

2
arch/arm/boot/dts/omap3-gta04.dtsi
View File

@ -515,7 +515,7 @@ bma180@41 {
compatible = "bosch,bma180";
reg = <0x41>;
pinctrl-names = "default";
pintcrl-0 = <&bma180_pins>;
pinctrl-0 = <&bma180_pins>;
interrupt-parent = <&gpio4>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
};

2
arch/arm/boot/dts/omap3430-sdp.dts
View File

@ -101,7 +101,7 @@ partition@280000 {
nand@1,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
reg = <1 0 4>; /* CS1, offset 0, IO size 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */

13
arch/arm/boot/dts/qcom-apq8064.dtsi
View File

@ -198,7 +198,7 @@ cxo_board: cxo_board {
clock-frequency = <19200000>;
};
pxo_board {
pxo_board: pxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
@ -1148,7 +1148,7 @@ tcsr: syscon@1a400000 {
};
gpu: adreno-3xx@4300000 {
compatible = "qcom,adreno-3xx";
compatible = "qcom,adreno-320.2", "qcom,adreno";
reg = <0x04300000 0x20000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
@ -1163,7 +1163,6 @@ gpu: adreno-3xx@4300000 {
<&mmcc GFX3D_AHB_CLK>,
<&mmcc GFX3D_AXI_CLK>,
<&mmcc MMSS_IMEM_AHB_CLK>;
qcom,chipid = <0x03020002>;
iommus = <&gfx3d 0
&gfx3d 1
@ -1262,9 +1261,9 @@ dsi0: mdss_dsi@4700000 {
<&mmcc DSI1_BYTE_CLK>,
<&mmcc DSI_PIXEL_CLK>,
<&mmcc DSI1_ESC_CLK>;
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
"src_clk", "byte_clk", "pixel_clk",
"core_clk";
clock-names = "iface", "bus", "core_mmss",
"src", "byte", "pixel",
"core";
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
<&mmcc DSI1_ESC_SRC>,
@ -1306,7 +1305,7 @@ dsi0_phy: dsi-phy@4700200 {
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
clock-names = "iface_clk", "ref";
clocks = <&mmcc DSI_M_AHB_CLK>,
<&cxo_board>;
<&pxo_board>;
};

4
arch/arm/boot/dts/qcom-msm8974.dtsi
View File

@ -1528,8 +1528,8 @@ dsi_phy0: dsi-phy@fd922a00 {
#phy-cells = <0>;
qcom,dsi-phy-index = <0>;
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface";
clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
clock-names = "iface", "ref";
};
};

2
arch/arm/boot/dts/spear3xx.dtsi
View File

@ -47,7 +47,7 @@ dma@fc400000 {
};
gmac: eth@e0800000 {
compatible = "st,spear600-gmac";
compatible = "snps,dwmac-3.40a";
reg = <0xe0800000 0x8000>;
interrupts = <23 22>;
interrupt-names = "macirq", "eth_wake_irq";

8
arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
View File

@ -1091,7 +1091,7 @@ pins {
};
};
sai2a_pins_c: sai2a-4 {
sai2a_pins_c: sai2a-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */
@ -1102,7 +1102,7 @@ pins {
};
};
sai2a_sleep_pins_c: sai2a-5 {
sai2a_sleep_pins_c: sai2a-2 {
pins {
pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */
<STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */
@ -1147,14 +1147,14 @@ pins {
};
};
sai2b_pins_c: sai2a-4 {
sai2b_pins_c: sai2b-2 {
pins1 {
pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */
bias-disable;
};
};
sai2b_sleep_pins_c: sai2a-sleep-5 {
sai2b_sleep_pins_c: sai2b-sleep-2 {
pins {
pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */
};

16
arch/arm/boot/dts/stm32mp151.dtsi
View File

@ -811,7 +811,7 @@ sai1a: audio-controller@4400a004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
reg = <0x4 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 87 0x400 0x01>;
@ -821,7 +821,7 @@ sai1a: audio-controller@4400a004 {
sai1b: audio-controller@4400a024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
reg = <0x24 0x20>;
clocks = <&rcc SAI1_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 88 0x400 0x01>;
@ -842,7 +842,7 @@ sai2: sai@4400b000 {
sai2a: audio-controller@4400b004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x4 0x1c>;
reg = <0x4 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 89 0x400 0x01>;
@ -852,7 +852,7 @@ sai2a: audio-controller@4400b004 {
sai2b: audio-controller@4400b024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
reg = <0x24 0x20>;
clocks = <&rcc SAI2_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 90 0x400 0x01>;
@ -873,7 +873,7 @@ sai3: sai@4400c000 {
sai3a: audio-controller@4400c004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x04 0x1c>;
reg = <0x04 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 113 0x400 0x01>;
@ -883,7 +883,7 @@ sai3a: audio-controller@4400c004 {
sai3b: audio-controller@4400c024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
reg = <0x24 0x20>;
clocks = <&rcc SAI3_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 114 0x400 0x01>;
@ -1250,7 +1250,7 @@ sai4: sai@50027000 {
sai4a: audio-controller@50027004 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-a";
reg = <0x04 0x1c>;
reg = <0x04 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 99 0x400 0x01>;
@ -1260,7 +1260,7 @@ sai4a: audio-controller@50027004 {
sai4b: audio-controller@50027024 {
#sound-dai-cells = <0>;
compatible = "st,stm32-sai-sub-b";
reg = <0x24 0x1c>;
reg = <0x24 0x20>;
clocks = <&rcc SAI4_K>;
clock-names = "sai_ck";
dmas = <&dmamux1 100 0x400 0x01>;

8
arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi
View File

@ -172,15 +172,15 @@ sgtl5000_port: port {
sgtl5000_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
frame-master;
bitclock-master;
frame-master = <&sgtl5000_tx_endpoint>;
bitclock-master = <&sgtl5000_tx_endpoint>;
};
sgtl5000_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
frame-master;
bitclock-master;
frame-master = <&sgtl5000_rx_endpoint>;
bitclock-master = <&sgtl5000_rx_endpoint>;
};
};

6
arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi
View File

@ -185,8 +185,8 @@ &i2c2 { /* X6 I2C2 */
&i2c4 {
hdmi-transmitter@3d {
compatible = "adi,adv7513";
reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
reg-names = "main", "cec", "edid", "packet";
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
reg-names = "main", "edid", "cec", "packet";
clocks = <&cec_clock>;
clock-names = "cec";
@ -204,8 +204,6 @@ hdmi-transmitter@3d {
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
adi,input-style = <1>;
adi,input-justification = "evenly";
ports {
#address-cells = <1>;

2
arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi
View File

@ -198,7 +198,7 @@ flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-rx-bus-width = <4>;
spi-max-frequency = <108000000>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <1>;
};

8
arch/arm/boot/dts/stm32mp15xx-dkx.dtsi
View File

@ -212,15 +212,15 @@ cs42l51_port: port {
cs42l51_tx_endpoint: endpoint@0 {
reg = <0>;
remote-endpoint = <&sai2a_endpoint>;
frame-master;
bitclock-master;
frame-master = <&cs42l51_tx_endpoint>;
bitclock-master = <&cs42l51_tx_endpoint>;
};
cs42l51_rx_endpoint: endpoint@1 {
reg = <1>;
remote-endpoint = <&sai2b_endpoint>;
frame-master;
bitclock-master;
frame-master = <&cs42l51_rx_endpoint>;
bitclock-master = <&cs42l51_rx_endpoint>;
};
};
};

2
arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
View File

@ -112,7 +112,7 @@ &gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};

25
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
View File

@ -704,7 +704,6 @@ usb-phy@c5000000 {
nvidia,xcvr-setup-use-fuses;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
vbus-supply = <&vdd_vbus1>;
};
usb@c5008000 {
@ -716,7 +715,7 @@ usb-phy@c5008000 {
nvidia,xcvr-setup-use-fuses;
nvidia,xcvr-lsfslew = <2>;
nvidia,xcvr-lsrslew = <2>;
vbus-supply = <&vdd_vbus3>;
vbus-supply = <&vdd_5v0_sys>;
};
brcm_wifi_pwrseq: wifi-pwrseq {
@ -967,28 +966,6 @@ vdd_pnl: regulator@3 {
vin-supply = <&vdd_5v0_sys>;
};
vdd_vbus1: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "vdd_usb1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
vdd_vbus3: regulator@5 {
compatible = "regulator-fixed";
regulator-name = "vdd_usb3_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_5v0_sys>;
};
sound {
compatible = "nvidia,tegra-audio-wm8903-picasso",
"nvidia,tegra-audio-wm8903";

14
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -185,8 +185,9 @@ conf_ata {
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
"cdev1", "cdev2", "dap1", "dtb", "gma",
"gmb", "gmc", "gmd", "gme", "gpu7",
"gpv", "i2cp", "pta", "rm", "slxa",
"slxk", "spia", "spib", "uac";
"gpv", "i2cp", "irrx", "irtx", "pta",
"rm", "slxa", "slxk", "spia", "spib",
"uac";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
@ -211,7 +212,7 @@ conf_crtp {
conf_ddc {
nvidia,pins = "ddc", "dta", "dtd", "kbca",
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
"sdc";
"sdc", "uad", "uca";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
};
@ -221,10 +222,9 @@ conf_hdint {
"lvp0", "owc", "sdb";
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};
conf_irrx {
nvidia,pins = "irrx", "irtx", "sdd", "spic",
"spie", "spih", "uaa", "uab", "uad",
"uca", "ucb";
conf_sdd {
nvidia,pins = "sdd", "spic", "spie", "spih",
"uaa", "uab", "ucb";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
};

2
arch/arm/boot/dts/vexpress-v2m.dtsi
View File

@ -19,7 +19,7 @@
*/
/ {
bus@4000000 {
bus@40000000 {
motherboard {
model = "V2M-P1";
arm,hbi = <0x190>;

2
arch/arm/boot/dts/vexpress-v2p-ca9.dts
View File

@ -295,7 +295,7 @@ power-vd10-s3 {
};
};
smb: bus@4000000 {
smb: bus@40000000 {
compatible = "simple-bus";
#address-cells = <2>;

3
arch/arm/include/asm/ftrace.h
View File

@ -15,6 +15,9 @@ extern void __gnu_mcount_nc(void);
#ifdef CONFIG_DYNAMIC_FTRACE
struct dyn_arch_ftrace {
#ifdef CONFIG_ARM_MODULE_PLTS
struct module *mod;
#endif
};
static inline unsigned long ftrace_call_adjust(unsigned long addr)

8
arch/arm/include/asm/insn.h
View File

@ -13,18 +13,18 @@ arm_gen_nop(void)
}
unsigned long
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link);
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn);
static inline unsigned long
arm_gen_branch(unsigned long pc, unsigned long addr)
{
return __arm_gen_branch(pc, addr, false);
return __arm_gen_branch(pc, addr, false, true);
}
static inline unsigned long
arm_gen_branch_link(unsigned long pc, unsigned long addr)
arm_gen_branch_link(unsigned long pc, unsigned long addr, bool warn)
{
return __arm_gen_branch(pc, addr, true);
return __arm_gen_branch(pc, addr, true, warn);
}
#endif

10
arch/arm/include/asm/module.h
View File

@ -19,8 +19,18 @@ enum {
};
#endif
#define PLT_ENT_STRIDE L1_CACHE_BYTES
#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
struct plt_entries {
u32 ldr[PLT_ENT_COUNT];
u32 lit[PLT_ENT_COUNT];
};
struct mod_plt_sec {
struct elf32_shdr *plt;
struct plt_entries *plt_ent;
int plt_count;
};

4
arch/arm/include/asm/uaccess.h
View File

@ -200,6 +200,7 @@ extern int __get_user_64t_4(void *);
register unsigned long __l asm("r1") = __limit; \
register int __e asm("r0"); \
unsigned int __ua_flags = uaccess_save_and_enable(); \
int __tmp_e; \
switch (sizeof(*(__p))) { \
case 1: \
if (sizeof((x)) >= 8) \
@ -227,9 +228,10 @@ extern int __get_user_64t_4(void *);
break; \
default: __e = __get_user_bad(); break; \
} \
__tmp_e = __e; \
uaccess_restore(__ua_flags); \
x = (typeof(*(p))) __r2; \
__e; \
__tmp_e; \
})
#define get_user(x, p) \

46
arch/arm/kernel/ftrace.c
View File

@ -68,9 +68,10 @@ int ftrace_arch_code_modify_post_process(void)
return 0;
}
static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr,
bool warn)
{
return arm_gen_branch_link(pc, addr);
return arm_gen_branch_link(pc, addr, warn);
}
static int ftrace_modify_code(unsigned long pc, unsigned long old,
@ -104,14 +105,14 @@ int ftrace_update_ftrace_func(ftrace_func_t func)
int ret;
pc = (unsigned long)&ftrace_call;
new = ftrace_call_replace(pc, (unsigned long)func);
new = ftrace_call_replace(pc, (unsigned long)func, true);
ret = ftrace_modify_code(pc, 0, new, false);
#ifdef CONFIG_DYNAMIC_FTRACE_WITH_REGS
if (!ret) {
pc = (unsigned long)&ftrace_regs_call;
new = ftrace_call_replace(pc, (unsigned long)func);
new = ftrace_call_replace(pc, (unsigned long)func, true);
ret = ftrace_modify_code(pc, 0, new, false);
}
@ -124,10 +125,22 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr)
{
unsigned long new, old;
unsigned long ip = rec->ip;
unsigned long aaddr = adjust_address(rec, addr);
struct module *mod = NULL;
#ifdef CONFIG_ARM_MODULE_PLTS
mod = rec->arch.mod;
#endif
old = ftrace_nop_replace(rec);
new = ftrace_call_replace(ip, adjust_address(rec, addr));
new = ftrace_call_replace(ip, aaddr, !mod);
#ifdef CONFIG_ARM_MODULE_PLTS
if (!new && mod) {
aaddr = get_module_plt(mod, ip, aaddr);
new = ftrace_call_replace(ip, aaddr, true);
}
#endif
return ftrace_modify_code(rec->ip, old, new, true);
}
@ -140,9 +153,9 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
unsigned long new, old;
unsigned long ip = rec->ip;
old = ftrace_call_replace(ip, adjust_address(rec, old_addr));
old = ftrace_call_replace(ip, adjust_address(rec, old_addr), true);
new = ftrace_call_replace(ip, adjust_address(rec, addr));
new = ftrace_call_replace(ip, adjust_address(rec, addr), true);
return ftrace_modify_code(rec->ip, old, new, true);
}
@ -152,12 +165,29 @@ int ftrace_modify_call(struct dyn_ftrace *rec, unsigned long old_addr,
int ftrace_make_nop(struct module *mod,
struct dyn_ftrace *rec, unsigned long addr)
{
unsigned long aaddr = adjust_address(rec, addr);
unsigned long ip = rec->ip;
unsigned long old;
unsigned long new;
int ret;
old = ftrace_call_replace(ip, adjust_address(rec, addr));
#ifdef CONFIG_ARM_MODULE_PLTS
/* mod is only supplied during module loading */
if (!mod)
mod = rec->arch.mod;
else
rec->arch.mod = mod;
#endif
old = ftrace_call_replace(ip, aaddr,
!IS_ENABLED(CONFIG_ARM_MODULE_PLTS) || !mod);
#ifdef CONFIG_ARM_MODULE_PLTS
if (!old && mod) {
aaddr = get_module_plt(mod, ip, aaddr);
old = ftrace_call_replace(ip, aaddr, true);
}
#endif
new = ftrace_nop_replace(rec);
ret = ftrace_modify_code(ip, old, new, true);

19
arch/arm/kernel/insn.c
View File

@ -3,8 +3,9 @@
#include <linux/kernel.h>
#include <asm/opcodes.h>
static unsigned long
__arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
static unsigned long __arm_gen_branch_thumb2(unsigned long pc,
unsigned long addr, bool link,
bool warn)
{
unsigned long s, j1, j2, i1, i2, imm10, imm11;
unsigned long first, second;
@ -12,7 +13,7 @@ __arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
offset = (long)addr - (long)(pc + 4);
if (offset < -16777216 || offset > 16777214) {
WARN_ON_ONCE(1);
WARN_ON_ONCE(warn);
return 0;
}
@ -33,8 +34,8 @@ __arm_gen_branch_thumb2(unsigned long pc, unsigned long addr, bool link)
return __opcode_thumb32_compose(first, second);
}
static unsigned long
__arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
static unsigned long __arm_gen_branch_arm(unsigned long pc, unsigned long addr,
bool link, bool warn)
{
unsigned long opcode = 0xea000000;
long offset;
@ -44,7 +45,7 @@ __arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
offset = (long)addr - (long)(pc + 8);
if (unlikely(offset < -33554432 || offset > 33554428)) {
WARN_ON_ONCE(1);
WARN_ON_ONCE(warn);
return 0;
}
@ -54,10 +55,10 @@ __arm_gen_branch_arm(unsigned long pc, unsigned long addr, bool link)
}
unsigned long
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link)
__arm_gen_branch(unsigned long pc, unsigned long addr, bool link, bool warn)
{
if (IS_ENABLED(CONFIG_THUMB2_KERNEL))
return __arm_gen_branch_thumb2(pc, addr, link);
return __arm_gen_branch_thumb2(pc, addr, link, warn);
else
return __arm_gen_branch_arm(pc, addr, link);
return __arm_gen_branch_arm(pc, addr, link, warn);
}

49
arch/arm/kernel/module-plts.c
View File

@ -4,6 +4,7 @@
*/
#include <linux/elf.h>
#include <linux/ftrace.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/sort.h>
@ -12,10 +13,6 @@
#include <asm/cache.h>
#include <asm/opcodes.h>
#define PLT_ENT_STRIDE L1_CACHE_BYTES
#define PLT_ENT_COUNT (PLT_ENT_STRIDE / sizeof(u32))
#define PLT_ENT_SIZE (sizeof(struct plt_entries) / PLT_ENT_COUNT)
#ifdef CONFIG_THUMB2_KERNEL
#define PLT_ENT_LDR __opcode_to_mem_thumb32(0xf8dff000 | \
(PLT_ENT_STRIDE - 4))
@ -24,9 +21,11 @@
(PLT_ENT_STRIDE - 8))
#endif
struct plt_entries {
u32 ldr[PLT_ENT_COUNT];
u32 lit[PLT_ENT_COUNT];
static const u32 fixed_plts[] = {
#ifdef CONFIG_DYNAMIC_FTRACE
FTRACE_ADDR,
MCOUNT_ADDR,
#endif
};
static bool in_init(const struct module *mod, unsigned long loc)
@ -34,14 +33,40 @@ static bool in_init(const struct module *mod, unsigned long loc)
return loc - (u32)mod->init_layout.base < mod->init_layout.size;
}
static void prealloc_fixed(struct mod_plt_sec *pltsec, struct plt_entries *plt)
{
int i;
if (!ARRAY_SIZE(fixed_plts) || pltsec->plt_count)
return;
pltsec->plt_count = ARRAY_SIZE(fixed_plts);
for (i = 0; i < ARRAY_SIZE(plt->ldr); ++i)
plt->ldr[i] = PLT_ENT_LDR;
BUILD_BUG_ON(sizeof(fixed_plts) > sizeof(plt->lit));
memcpy(plt->lit, fixed_plts, sizeof(fixed_plts));
}
u32 get_module_plt(struct module *mod, unsigned long loc, Elf32_Addr val)
{
struct mod_plt_sec *pltsec = !in_init(mod, loc) ? &mod->arch.core :
&mod->arch.init;
struct plt_entries *plt;
int idx;
struct plt_entries *plt = (struct plt_entries *)pltsec->plt->sh_addr;
int idx = 0;
/* cache the address, ELF header is available only during module load */
if (!pltsec->plt_ent)
pltsec->plt_ent = (struct plt_entries *)pltsec->plt->sh_addr;
plt = pltsec->plt_ent;
prealloc_fixed(pltsec, plt);
for (idx = 0; idx < ARRAY_SIZE(fixed_plts); ++idx)
if (plt->lit[idx] == val)
return (u32)&plt->ldr[idx];
idx = 0;
/*
* Look for an existing entry pointing to 'val'. Given that the
* relocations are sorted, this will be the last entry we allocated.
@ -189,8 +214,8 @@ static unsigned int count_plts(const Elf32_Sym *syms, Elf32_Addr base,
int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
char *secstrings, struct module *mod)
{
unsigned long core_plts = 0;
unsigned long init_plts = 0;
unsigned long core_plts = ARRAY_SIZE(fixed_plts);
unsigned long init_plts = ARRAY_SIZE(fixed_plts);
Elf32_Shdr *s, *sechdrs_end = sechdrs + ehdr->e_shnum;
Elf32_Sym *syms = NULL;
@ -245,6 +270,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
mod->arch.core.plt->sh_size = round_up(core_plts * PLT_ENT_SIZE,
sizeof(struct plt_entries));
mod->arch.core.plt_count = 0;
mod->arch.core.plt_ent = NULL;
mod->arch.init.plt->sh_type = SHT_NOBITS;
mod->arch.init.plt->sh_flags = SHF_EXECINSTR | SHF_ALLOC;
@ -252,6 +278,7 @@ int module_frob_arch_sections(Elf_Ehdr *ehdr, Elf_Shdr *sechdrs,
mod->arch.init.plt->sh_size = round_up(init_plts * PLT_ENT_SIZE,
sizeof(struct plt_entries));
mod->arch.init.plt_count = 0;
mod->arch.init.plt_ent = NULL;
pr_debug("%s: plt=%x, init.plt=%x\n", __func__,
mod->arch.core.plt->sh_size, mod->arch.init.plt->sh_size);

3
arch/arm/kernel/stacktrace.c
View File

@ -54,8 +54,7 @@ int notrace unwind_frame(struct stackframe *frame)
frame->sp = frame->fp;
frame->fp = *(unsigned long *)(fp);
frame->pc = frame->lr;
frame->lr = *(unsigned long *)(fp + 4);
frame->pc = *(unsigned long *)(fp + 4);
#else
/* check current frame pointer is within bounds */
if (fp < low + 12 || fp > high - 4)

6
arch/arm/kernel/vmlinux-xip.lds.S
View File

@ -40,6 +40,10 @@ SECTIONS
ARM_DISCARD
*(.alt.smp.init)
*(.pv_table)
#ifndef CONFIG_ARM_UNWIND
*(.ARM.exidx) *(.ARM.exidx.*)
*(.ARM.extab) *(.ARM.extab.*)
#endif
}
. = XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR);
@ -172,7 +176,7 @@ ASSERT((__arch_info_end - __arch_info_begin), "no machine record defined")
ASSERT((_end - __bss_start) >= 12288, ".bss too small for CONFIG_XIP_DEFLATED_DATA")
#endif
#ifdef CONFIG_ARM_MPU
#if defined(CONFIG_ARM_MPU) && !defined(CONFIG_COMPILE_TEST)
/*
* Due to PMSAv7 restriction on base address and size we have to
* enforce minimal alignment restrictions. It was seen that weaker

58
arch/arm/mach-at91/pm.c
View File

@ -517,18 +517,22 @@ static const struct of_device_id ramc_ids[] __initconst = {
{ /*sentinel*/ }
};
static __init void at91_dt_ramc(void)
static __init int at91_dt_ramc(void)
{
struct device_node *np;
const struct of_device_id *of_id;
int idx = 0;
void *standby = NULL;
const struct ramc_info *ramc;
int ret;
for_each_matching_node_and_match(np, ramc_ids, &of_id) {
soc_pm.data.ramc[idx] = of_iomap(np, 0);
if (!soc_pm.data.ramc[idx])
panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
if (!soc_pm.data.ramc[idx]) {
pr_err("unable to map ramc[%d] cpu registers\n", idx);
ret = -ENOMEM;
goto unmap_ramc;
}
ramc = of_id->data;
if (!standby)
@ -538,15 +542,26 @@ static __init void at91_dt_ramc(void)
idx++;
}
if (!idx)
panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
if (!idx) {
pr_err("unable to find compatible ram controller node in dtb\n");
ret = -ENODEV;
goto unmap_ramc;
}
if (!standby) {
pr_warn("ramc no standby function available\n");
return;
return 0;
}
at91_cpuidle_device.dev.platform_data = standby;
return 0;
unmap_ramc:
while (idx)
iounmap(soc_pm.data.ramc[--idx]);
return ret;
}
static void at91rm9200_idle(void)
@ -869,6 +884,8 @@ static void __init at91_pm_init(void (*pm_idle)(void))
void __init at91rm9200_pm_init(void)
{
int ret;
if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
return;
@ -880,7 +897,9 @@ void __init at91rm9200_pm_init(void)
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
at91_dt_ramc();
ret = at91_dt_ramc();
if (ret)
return;
/*
* AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
@ -895,13 +914,17 @@ void __init sam9x60_pm_init(void)
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
at91_dt_ramc();
ret = at91_dt_ramc();
if (ret)
return;
at91_pm_init(NULL);
soc_pm.ws_ids = sam9x60_ws_ids;
@ -910,6 +933,8 @@ void __init sam9x60_pm_init(void)
void __init at91sam9_pm_init(void)
{
int ret;
if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
return;
@ -921,7 +946,10 @@ void __init at91sam9_pm_init(void)
soc_pm.data.standby_mode = AT91_PM_STANDBY;
soc_pm.data.suspend_mode = AT91_PM_ULP0;
at91_dt_ramc();
ret = at91_dt_ramc();
if (ret)
return;
at91_pm_init(at91sam9_idle);
}
@ -930,12 +958,16 @@ void __init sama5_pm_init(void)
static const int modes[] __initconst = {
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA5))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_dt_ramc();
ret = at91_dt_ramc();
if (ret)
return;
at91_pm_init(NULL);
}
@ -945,13 +977,17 @@ void __init sama5d2_pm_init(void)
AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
AT91_PM_BACKUP,
};
int ret;
if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
return;
at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
at91_pm_modes_init();
at91_dt_ramc();
ret = at91_dt_ramc();
if (ret)
return;
at91_pm_init(NULL);
soc_pm.ws_ids = sama5d2_ws_ids;

2
arch/arm/mach-imx/pm-imx6.c
View File

@ -9,6 +9,7 @@
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/genalloc.h>
#include <linux/irqchip/arm-gic.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of.h>
@ -618,6 +619,7 @@ static void __init imx6_pm_common_init(const struct imx6_pm_socdata
static void imx6_pm_stby_poweroff(void)
{
gic_cpu_if_down(0);
imx6_set_lpm(STOP_POWER_OFF);
imx6q_suspend_finish(0);

2
arch/arm/mach-omap2/omap_hwmod.c
View File

@ -3618,6 +3618,8 @@ int omap_hwmod_init_module(struct device *dev,
oh->flags |= HWMOD_SWSUP_SIDLE_ACT;
if (data->cfg->quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
oh->flags |= HWMOD_SWSUP_MSTANDBY;
if (data->cfg->quirks & SYSC_QUIRK_CLKDM_NOAUTO)
oh->flags |= HWMOD_CLKDM_NOAUTO;
error = omap_hwmod_check_module(dev, oh, data, sysc_fields,
rev_offs, sysc_offs, syss_offs,

22
arch/arm/mach-s3c/irq-s3c24xx.c
View File

@ -360,11 +360,25 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc,
asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs)
{
do {
if (likely(s3c_intc[0]))
if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
continue;
/*
* For platform based machines, neither ERR nor NULL can happen here.
* The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds:
*
* s3c_intc[0] = s3c24xx_init_intc()
*
* If this fails, the next calls to s3c24xx_init_intc() won't be executed.
*
* For DT machine, s3c_init_intc_of() could set the IRQ handler without
* setting s3c_intc[0] only if it was called with num_ctrl=0. There is no
* such code path, so again the s3c_intc[0] will have a valid pointer if
* set_handle_irq() is called.
*
* Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something.
*/
if (s3c24xx_handle_intc(s3c_intc[0], regs, 0))
continue;
if (s3c_intc[2])
if (!IS_ERR_OR_NULL(s3c_intc[2]))
if (s3c24xx_handle_intc(s3c_intc[2], regs, 64))
continue;

2
arch/arm/mm/Kconfig
View File

@ -753,7 +753,7 @@ config CPU_BIG_ENDIAN
config CPU_ENDIAN_BE8
bool
depends on CPU_BIG_ENDIAN
default CPU_V6 || CPU_V6K || CPU_V7
default CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
help
Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.

6
arch/arm/mm/init.c
View File

@ -378,7 +378,11 @@ static void __init free_highpages(void)
void __init mem_init(void)
{
#ifdef CONFIG_ARM_LPAE
swiotlb_init(1);
if (swiotlb_force == SWIOTLB_FORCE ||
max_pfn > arm_dma_pfn_limit)
swiotlb_init(1);
else
swiotlb_force = SWIOTLB_NO_FORCE;
#endif
set_max_mapnr(pfn_to_page(max_pfn) - mem_map);

4
arch/arm/mm/mmu.c
View File

@ -391,9 +391,9 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
FIXADDR_END);
BUG_ON(idx >= __end_of_fixed_addresses);
/* we only support device mappings until pgprot_kernel has been set */
/* We support only device mappings before pgprot_kernel is set. */
if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) &&
pgprot_val(pgprot_kernel) == 0))
pgprot_val(prot) && pgprot_val(pgprot_kernel) == 0))
return;
if (pgprot_val(prot))

1
arch/arm/mm/proc-macros.S
View File

@ -340,6 +340,7 @@ ENTRY(\name\()_cache_fns)
.macro define_tlb_functions name:req, flags_up:req, flags_smp
.type \name\()_tlb_fns, #object
.align 2
ENTRY(\name\()_tlb_fns)
.long \name\()_flush_user_tlb_range
.long \name\()_flush_kern_tlb_range

19
arch/arm/net/bpf_jit_32.c
View File

@ -36,6 +36,10 @@
* +-----+
* |RSVD | JIT scratchpad
* current ARM_SP => +-----+ <= (BPF_FP - STACK_SIZE + SCRATCH_SIZE)
* | ... | caller-saved registers
* +-----+
* | ... | arguments passed on stack
* ARM_SP during call => +-----|
* | |
* | ... | Function call stack
* | |
@ -63,6 +67,12 @@
*
* When popping registers off the stack at the end of a BPF function, we
* reference them via the current ARM_FP register.
*
* Some eBPF operations are implemented via a call to a helper function.
* Such calls are "invisible" in the eBPF code, so it is up to the calling
* program to preserve any caller-saved ARM registers during the call. The
* JIT emits code to push and pop those registers onto the stack, immediately
* above the callee stack frame.
*/
#define CALLEE_MASK (1 << ARM_R4 | 1 << ARM_R5 | 1 << ARM_R6 | \
1 << ARM_R7 | 1 << ARM_R8 | 1 << ARM_R9 | \
@ -70,6 +80,8 @@
#define CALLEE_PUSH_MASK (CALLEE_MASK | 1 << ARM_LR)
#define CALLEE_POP_MASK (CALLEE_MASK | 1 << ARM_PC)
#define CALLER_MASK (1 << ARM_R0 | 1 << ARM_R1 | 1 << ARM_R2 | 1 << ARM_R3)
enum {
/* Stack layout - these are offsets from (top of stack - 4) */
BPF_R2_HI,
@ -464,6 +476,7 @@ static inline int epilogue_offset(const struct jit_ctx *ctx)
static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
{
const int exclude_mask = BIT(ARM_R0) | BIT(ARM_R1);
const s8 *tmp = bpf2a32[TMP_REG_1];
#if __LINUX_ARM_ARCH__ == 7
@ -495,11 +508,17 @@ static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op)
emit(ARM_MOV_R(ARM_R0, rm), ctx);
}
/* Push caller-saved registers on stack */
emit(ARM_PUSH(CALLER_MASK & ~exclude_mask), ctx);
/* Call appropriate function */
emit_mov_i(ARM_IP, op == BPF_DIV ?
(u32)jit_udiv32 : (u32)jit_mod32, ctx);
emit_blx_r(ARM_IP, ctx);
/* Restore caller-saved registers from stack */
emit(ARM_POP(CALLER_MASK & ~exclude_mask), ctx);
/* Save return value */
if (rd != ARM_R0)
emit(ARM_MOV_R(rd, ARM_R0), ctx);

2
arch/arm/probes/kprobes/core.c
View File

@ -462,7 +462,7 @@ static struct undef_hook kprobes_arm_break_hook = {
#endif /* !CONFIG_THUMB2_KERNEL */
int __init arch_init_kprobes()
int __init arch_init_kprobes(void)
{
arm_probes_decode_init();
#ifdef CONFIG_THUMB2_KERNEL

2
arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
View File

@ -75,7 +75,7 @@ &emac {
pinctrl-0 = <&emac_rgmii_pins>;
phy-supply = <&reg_gmac_3v3>;
phy-handle = <&ext_rgmii_phy>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
status = "okay";
};

4
arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
View File

@ -32,14 +32,14 @@ hdmi_con_in: endpoint {
};
};
reg_vcc3v3: vcc3v3 {
reg_vcc3v3: regulator-vcc3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_vdd_cpu_gpu: vdd-cpu-gpu {
reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
compatible = "regulator-fixed";
regulator-name = "vdd-cpu-gpu";
regulator-min-microvolt = <1135000>;

2
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
View File

@ -139,7 +139,7 @@ vddcpu: regulator-vddcpu {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&dc_in>;
pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

2
arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
View File

@ -139,7 +139,7 @@ vddcpu: regulator-vddcpu {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

2
arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts
View File

@ -139,7 +139,7 @@ vddcpu: regulator-vddcpu {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&dc_in>;
pwm-supply = <&dc_in>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

4
arch/arm64/boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi
View File

@ -18,7 +18,7 @@ vddcpu_a: regulator-vddcpu-a {
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&dc_in>;
pwm-supply = <&dc_in>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
@ -37,7 +37,7 @@ vddcpu_b: regulator-vddcpu-b {
regulator-min-microvolt = <690000>;
regulator-max-microvolt = <1050000>;
vin-supply = <&vsys_3v3>;
pwm-supply = <&vsys_3v3>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

4
arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dtsi
View File

@ -128,7 +128,7 @@ vddcpu_a: regulator-vddcpu-a {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwm-supply = <&main_12v>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
@ -147,7 +147,7 @@ vddcpu_b: regulator-vddcpu-b {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

4
arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
View File

@ -96,7 +96,7 @@ vddcpu_a: regulator-vddcpu-a {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwm-supply = <&main_12v>;
pwms = <&pwm_ab 0 1250 0>;
pwm-dutycycle-range = <100 0>;
@ -115,7 +115,7 @@ vddcpu_b: regulator-vddcpu-b {
regulator-min-microvolt = <721000>;
regulator-max-microvolt = <1022000>;
vin-supply = <&main_12v>;
pwm-supply = <&main_12v>;
pwms = <&pwm_AO_cd 1 1250 0>;
pwm-dutycycle-range = <100 0>;

18
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -386,6 +386,24 @@ esdhc1: mmc@2150000 {
status = "disabled";
};
can0: can@2180000 {
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 1>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: can@2190000 {
compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>, <&clockgen 4 1>;
clock-names = "ipg", "per";
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;

8
arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
View File

@ -83,15 +83,9 @@ rtc@51 {
};
eeprom@52 {
compatible = "atmel,24c512";
compatible = "onnn,cat24c04", "atmel,24c04";
reg = <0x52>;
};
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
};
};
};
};

7
arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
View File

@ -58,14 +58,9 @@ temp-sensor@4c {
};
eeprom@52 {
compatible = "atmel,24c512";
compatible = "onnn,cat24c05", "atmel,24c04";
reg = <0x52>;
};
eeprom@53 {
compatible = "atmel,24c512";
reg = <0x53>;
};
};
&i2c3 {

4
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View File

@ -1215,13 +1215,13 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "nvidia,denver";
compatible = "nvidia,tegra132-denver";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "nvidia,denver";
compatible = "nvidia,tegra132-denver";
reg = <1>;
};
};

6
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View File

@ -1976,7 +1976,7 @@ pcie@141a0000 {
};
pcie_ep@14160000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
@ -2008,7 +2008,7 @@ pcie_ep@14160000 {
};
pcie_ep@14180000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
@ -2040,7 +2040,7 @@ pcie_ep@14180000 {
};
pcie_ep@141a0000 {
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
compatible = "nvidia,tegra194-pcie-ep";
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */

2
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -151,7 +151,7 @@ reserved-memory {
#size-cells = <2>;
ranges;
rpm_msg_ram: memory@0x60000 {
rpm_msg_ram: memory@60000 {
reg = <0x0 0x60000 0x0 0x6000>;
no-map;
};

2
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View File

@ -20,7 +20,7 @@ chosen {
stdout-path = "serial0";
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};

16
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -567,10 +567,10 @@ frame@b128000 {
pcie1: pci@10000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x10000000 0xf1d
0x10000f20 0xa8
0x00088000 0x2000
0x10100000 0x1000>;
reg = <0x10000000 0xf1d>,
<0x10000f20 0xa8>,
<0x00088000 0x2000>,
<0x10100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <1>;
@ -629,10 +629,10 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
pcie0: pci@20000000 {
compatible = "qcom,pcie-ipq8074";
reg = <0x20000000 0xf1d
0x20000f20 0xa8
0x00080000 0x2000
0x20100000 0x1000>;
reg = <0x20000000 0xf1d>,
<0x20000f20 0xa8>,
<0x00080000 0x2000>,
<0x20100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;

8
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -1322,11 +1322,17 @@ sound: sound@7702000 {
lpass: audio-controller@7708000 {
status = "disabled";
compatible = "qcom,lpass-cpu-apq8016";
/*
* Note: Unlike the name would suggest, the SEC_I2S_CLK
* is actually only used by Tertiary MI2S while
* Primary/Secondary MI2S both use the PRI_I2S_CLK.
*/
clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
<&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
<&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

6
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -14,16 +14,18 @@ / {
chosen { };
clocks {
xo_board: xo_board {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep_clk {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "sleep_clk";
};
};

4
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -17,14 +17,14 @@ / {
chosen { };
clocks {
xo_board: xo_board {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep_clk {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;

2
arch/arm64/boot/dts/qcom/pm8150.dtsi
View File

@ -48,7 +48,7 @@ pm8150_0: pmic@0 {
#size-cells = <0>;
pon: power-on@800 {
compatible = "qcom,pm8916-pon";
compatible = "qcom,pm8998-pon";
reg = <0x0800>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";

1
arch/arm64/boot/dts/qcom/pm8916.dtsi
View File

@ -86,7 +86,6 @@ adc-chan@f {
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};

263
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@ -17,14 +17,14 @@ / {
chosen { };
clocks {
xo_board: xo_board {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
clock-output-names = "xo_board";
};
sleep_clk: sleep_clk {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32764>;
@ -343,10 +343,19 @@ wlan_msa_mem: wlan-msa-mem@85700000 {
};
qhee_code: qhee-code@85800000 {
reg = <0x0 0x85800000 0x0 0x3700000>;
reg = <0x0 0x85800000 0x0 0x600000>;
no-map;
};
rmtfs_mem: memory@85e00000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x85e00000 0x0 0x200000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
smem_region: smem-mem@86000000 {
reg = <0 0x86000000 0 0x200000>;
no-map;
@ -357,58 +366,44 @@ tz_mem: memory@86200000 {
no-map;
};
modem_fw_mem: modem-fw-region@8ac00000 {
mpss_region: mpss@8ac00000 {
reg = <0x0 0x8ac00000 0x0 0x7e00000>;
no-map;
};
adsp_fw_mem: adsp-fw-region@92a00000 {
adsp_region: adsp@92a00000 {
reg = <0x0 0x92a00000 0x0 0x1e00000>;
no-map;
};
pil_mba_mem: pil-mba-region@94800000 {
mba_region: mba@94800000 {
reg = <0x0 0x94800000 0x0 0x200000>;
no-map;
};
buffer_mem: buffer-region@94a00000 {
buffer_mem: tzbuffer@94a00000 {
reg = <0x0 0x94a00000 0x0 0x100000>;
no-map;
};
venus_fw_mem: venus-fw-region@9f800000 {
venus_region: venus@9f800000 {
reg = <0x0 0x9f800000 0x0 0x800000>;
no-map;
};
secure_region2: secure-region2@f7c00000 {
reg = <0x0 0xf7c00000 0x0 0x5c00000>;
no-map;
};
adsp_mem: adsp-region@f6000000 {
reg = <0x0 0xf6000000 0x0 0x800000>;
no-map;
};
qseecom_ta_mem: qseecom-ta-region@fec00000 {
reg = <0x0 0xfec00000 0x0 0x1000000>;
no-map;
};
qseecom_mem: qseecom-region@f6800000 {
reg = <0x0 0xf6800000 0x0 0x1400000>;
no-map;
};
secure_display_memory: secure-region@f5c00000 {
reg = <0x0 0xf5c00000 0x0 0x5c00000>;
no-map;
};
cont_splash_mem: cont-splash-region@9d400000 {
reg = <0x0 0x9d400000 0x0 0x23ff000>;
zap_shader_region: gpu@fed00000 {
compatible = "shared-dma-pool";
reg = <0x0 0xfed00000 0x0 0xa00000>;
no-map;
};
};
@ -527,14 +522,18 @@ tcsr_mutex_regs: syscon@1f40000 {
reg = <0x01f40000 0x20000>;
};
tlmm: pinctrl@3000000 {
tlmm: pinctrl@3100000 {
compatible = "qcom,sdm630-pinctrl";
reg = <0x03000000 0xc00000>;
reg = <0x03100000 0x400000>,
<0x03500000 0x400000>,
<0x03900000 0x400000>;
reg-names = "south", "center", "north";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 114>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x2>;
#interrupt-cells = <2>;
blsp1_uart1_default: blsp1-uart1-default {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
@ -554,40 +553,48 @@ blsp1_uart2_default: blsp1-uart2-default {
bias-disable;
};
blsp2_uart1_tx_active: blsp2-uart1-tx-active {
pins = "gpio16";
drive-strength = <2>;
bias-disable;
blsp2_uart1_default: blsp2-uart1-active {
tx-rts {
pins = "gpio16", "gpio19";
function = "blsp_uart5";
drive-strength = <2>;
bias-disable;
};
rx {
/*
* Avoid garbage data while BT module
* is powered off or not driving signal
*/
pins = "gpio17";
function = "blsp_uart5";
drive-strength = <2>;
bias-pull-up;
};
cts {
/* Match the pull of the BT module */
pins = "gpio18";
function = "blsp_uart5";
drive-strength = <2>;
bias-pull-down;
};
};
blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
pins = "gpio16";
drive-strength = <2>;
bias-pull-up;
};
blsp2_uart1_sleep: blsp2-uart1-sleep {
tx {
pins = "gpio16";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
pins = "gpio17", "gpio18";
drive-strength = <2>;
bias-no-pull;
};
blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
pins = "gpio19";
drive-strength = <2>;
bias-disable;
};
blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
pins = "gpio19";
drive-strength = <2>;
bias-no-pull;
rx-cts-rts {
pins = "gpio17", "gpio18", "gpio19";
function = "gpio";
drive-strength = <2>;
bias-no-pull;
};
};
i2c1_default: i2c1-default {
@ -686,50 +693,106 @@ i2c8_sleep: i2c8-sleep {
bias-pull-up;
};
sdc1_clk_on: sdc1-clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
sdc1_state_on: sdc1-on {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <10>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_clk_off: sdc1-clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
sdc1_state_off: sdc1-off {
clk {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
cmd {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
rclk {
pins = "sdc1_rclk";
bias-pull-down;
};
};
sdc1_cmd_on: sdc1-cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <10>;
sdc2_state_on: sdc2-on {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <16>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <10>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio54";
bias-pull-up;
drive-strength = <2>;
};
};
sdc1_cmd_off: sdc1-cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc2_state_off: sdc2-off {
clk {
pins = "sdc2_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_data_on: sdc1-data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
cmd {
pins = "sdc2_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_off: sdc1-data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
data {
pins = "sdc2_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: sdc1-rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: sdc1-rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
sd-cd {
pins = "gpio54";
bias-disable;
drive-strength = <2>;
};
};
};
@ -821,8 +884,8 @@ sdhc_1: sdhci@c0c4000 {
clock-names = "core", "iface", "xo";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
bus-width = <8>;
non-removable;
@ -967,10 +1030,8 @@ blsp2_uart1: serial@c1af000 {
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
&blsp2_uart1_rfr_active>;
pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
&blsp2_uart1_rfr_sleep>;
pinctrl-0 = <&blsp2_uart1_default>;
pinctrl-1 = <&blsp2_uart1_sleep>;
status = "disabled";
};

2
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@ -2346,7 +2346,7 @@ apps_bcm_voter: bcm_voter {
};
};
epss_l3: interconnect@18591000 {
epss_l3: interconnect@18590000 {
compatible = "qcom,sm8250-epss-l3";
reg = <0 0x18590000 0 0x1000>;

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