UPSTREAM: media: v4l: Add HDR10 static metadata controls

Introduce Content light level and Mastering display colour
volume Colorimetry compound controls with relevant payload
structures and validation.

Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Reviewed-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
(cherry picked from commit 1ad0de78e7944eef171340d9fa00f0a59458991c)
BUG: 175389589

Change-Id: Ic5985500f2b7bb51699998a4dbe82d4966c0704c
Signed-off-by: Dikshita Agarwal <dikshita@codeaurora.org>
This commit is contained in:
Stanimir Varbanov 2021-01-19 16:06:42 +01:00 committed by Todd Kjos
parent 683232ea4c
commit 43461c878a
4 changed files with 106 additions and 0 deletions

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@ -1215,6 +1215,8 @@ const char *v4l2_ctrl_get_name(u32 id)
/* Colorimetry controls */
/* Keep the order of the 'case's the same as in v4l2-controls.h! */
case V4L2_CID_COLORIMETRY_CLASS: return "Colorimetry Controls";
case V4L2_CID_COLORIMETRY_HDR10_CLL_INFO: return "HDR10 Content Light Info";
case V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY: return "HDR10 Mastering Display";
default:
return NULL;
}
@ -1523,6 +1525,12 @@ void v4l2_ctrl_fill(u32 id, const char **name, enum v4l2_ctrl_type *type,
*type = V4L2_CTRL_TYPE_AREA;
*flags |= V4L2_CTRL_FLAG_READ_ONLY;
break;
case V4L2_CID_COLORIMETRY_HDR10_CLL_INFO:
*type = V4L2_CTRL_TYPE_HDR10_CLL_INFO;
break;
case V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY:
*type = V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY;
break;
default:
*type = V4L2_CTRL_TYPE_INTEGER;
break;
@ -1785,6 +1793,12 @@ static void std_log(const struct v4l2_ctrl *ctrl)
case V4L2_CTRL_TYPE_U32:
pr_cont("%u", (unsigned)*ptr.p_u32);
break;
case V4L2_CTRL_TYPE_HDR10_CLL_INFO:
pr_cont("HDR10_CLL_INFO");
break;
case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY:
pr_cont("HDR10_MASTERING_DISPLAY");
break;
default:
pr_cont("unknown type %d", ctrl->type);
break;
@ -1833,6 +1847,7 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
struct v4l2_ctrl_hevc_sps *p_hevc_sps;
struct v4l2_ctrl_hevc_pps *p_hevc_pps;
struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params;
struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering;
struct v4l2_area *area;
void *p = ptr.p + idx * ctrl->elem_size;
unsigned int i;
@ -1992,6 +2007,53 @@ static int std_validate_compound(const struct v4l2_ctrl *ctrl, u32 idx,
zero_padding(*p_hevc_slice_params);
break;
case V4L2_CTRL_TYPE_HDR10_CLL_INFO:
break;
case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY:
p_hdr10_mastering = p;
for (i = 0; i < 3; ++i) {
if (p_hdr10_mastering->display_primaries_x[i] <
V4L2_HDR10_MASTERING_PRIMARIES_X_LOW ||
p_hdr10_mastering->display_primaries_x[i] >
V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH ||
p_hdr10_mastering->display_primaries_y[i] <
V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW ||
p_hdr10_mastering->display_primaries_y[i] >
V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH)
return -EINVAL;
}
if (p_hdr10_mastering->white_point_x <
V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW ||
p_hdr10_mastering->white_point_x >
V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH ||
p_hdr10_mastering->white_point_y <
V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW ||
p_hdr10_mastering->white_point_y >
V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH)
return -EINVAL;
if (p_hdr10_mastering->max_display_mastering_luminance <
V4L2_HDR10_MASTERING_MAX_LUMA_LOW ||
p_hdr10_mastering->max_display_mastering_luminance >
V4L2_HDR10_MASTERING_MAX_LUMA_HIGH ||
p_hdr10_mastering->min_display_mastering_luminance <
V4L2_HDR10_MASTERING_MIN_LUMA_LOW ||
p_hdr10_mastering->min_display_mastering_luminance >
V4L2_HDR10_MASTERING_MIN_LUMA_HIGH)
return -EINVAL;
/* The following restriction comes from ITU-T Rec. H.265 spec */
if (p_hdr10_mastering->max_display_mastering_luminance ==
V4L2_HDR10_MASTERING_MAX_LUMA_LOW &&
p_hdr10_mastering->min_display_mastering_luminance ==
V4L2_HDR10_MASTERING_MIN_LUMA_HIGH)
return -EINVAL;
break;
case V4L2_CTRL_TYPE_AREA:
area = p;
if (!area->width || !area->height)
@ -2702,6 +2764,12 @@ static struct v4l2_ctrl *v4l2_ctrl_new(struct v4l2_ctrl_handler *hdl,
case V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS:
elem_size = sizeof(struct v4l2_ctrl_hevc_slice_params);
break;
case V4L2_CTRL_TYPE_HDR10_CLL_INFO:
elem_size = sizeof(struct v4l2_ctrl_hdr10_cll_info);
break;
case V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY:
elem_size = sizeof(struct v4l2_ctrl_hdr10_mastering_display);
break;
case V4L2_CTRL_TYPE_AREA:
elem_size = sizeof(struct v4l2_area);
break;

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@ -56,6 +56,8 @@ struct video_device;
* @p_hevc_sps: Pointer to an HEVC sequence parameter set structure.
* @p_hevc_pps: Pointer to an HEVC picture parameter set structure.
* @p_hevc_slice_params: Pointer to an HEVC slice parameters structure.
* @p_hdr10_cll: Pointer to an HDR10 Content Light Level structure.
* @p_hdr10_mastering: Pointer to an HDR10 Mastering Display structure.
* @p_area: Pointer to an area.
* @p: Pointer to a compound value.
* @p_const: Pointer to a constant compound value.
@ -80,6 +82,8 @@ union v4l2_ctrl_ptr {
struct v4l2_ctrl_hevc_sps *p_hevc_sps;
struct v4l2_ctrl_hevc_pps *p_hevc_pps;
struct v4l2_ctrl_hevc_slice_params *p_hevc_slice_params;
struct v4l2_ctrl_hdr10_cll_info *p_hdr10_cll;
struct v4l2_ctrl_hdr10_mastering_display *p_hdr10_mastering;
struct v4l2_area *p_area;
void *p;
const void *p_const;

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@ -1199,4 +1199,35 @@ enum v4l2_detect_md_mode {
#define V4L2_CID_COLORIMETRY_CLASS_BASE (V4L2_CTRL_CLASS_COLORIMETRY | 0x900)
#define V4L2_CID_COLORIMETRY_CLASS (V4L2_CTRL_CLASS_COLORIMETRY | 1)
#define V4L2_CID_COLORIMETRY_HDR10_CLL_INFO (V4L2_CID_COLORIMETRY_CLASS_BASE + 0)
struct v4l2_ctrl_hdr10_cll_info {
__u16 max_content_light_level;
__u16 max_pic_average_light_level;
};
#define V4L2_CID_COLORIMETRY_HDR10_MASTERING_DISPLAY (V4L2_CID_COLORIMETRY_CLASS_BASE + 1)
#define V4L2_HDR10_MASTERING_PRIMARIES_X_LOW 5
#define V4L2_HDR10_MASTERING_PRIMARIES_X_HIGH 37000
#define V4L2_HDR10_MASTERING_PRIMARIES_Y_LOW 5
#define V4L2_HDR10_MASTERING_PRIMARIES_Y_HIGH 42000
#define V4L2_HDR10_MASTERING_WHITE_POINT_X_LOW 5
#define V4L2_HDR10_MASTERING_WHITE_POINT_X_HIGH 37000
#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_LOW 5
#define V4L2_HDR10_MASTERING_WHITE_POINT_Y_HIGH 42000
#define V4L2_HDR10_MASTERING_MAX_LUMA_LOW 50000
#define V4L2_HDR10_MASTERING_MAX_LUMA_HIGH 100000000
#define V4L2_HDR10_MASTERING_MIN_LUMA_LOW 1
#define V4L2_HDR10_MASTERING_MIN_LUMA_HIGH 50000
struct v4l2_ctrl_hdr10_mastering_display {
__u16 display_primaries_x[3];
__u16 display_primaries_y[3];
__u16 white_point_x;
__u16 white_point_y;
__u32 max_display_mastering_luminance;
__u32 min_display_mastering_luminance;
};
#endif

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@ -1781,6 +1781,9 @@ enum v4l2_ctrl_type {
V4L2_CTRL_TYPE_U32 = 0x0102,
V4L2_CTRL_TYPE_AREA = 0x0106,
V4L2_CTRL_TYPE_HDR10_CLL_INFO = 0x0110,
V4L2_CTRL_TYPE_HDR10_MASTERING_DISPLAY = 0x0111,
V4L2_CTRL_TYPE_H264_SPS = 0x0200,
V4L2_CTRL_TYPE_H264_PPS = 0x0201,
V4L2_CTRL_TYPE_H264_SCALING_MATRIX = 0x0202,