drm/msm/adreno: Add A540 support
The A540 is a derivative of the A530, and is found in the MSM8998 SoC. Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Jeffrey Hugo
Rob Clark
parent
d67f1b6d0e
commit
370063ee42
@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
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git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 42463 bytes, from 2018-11-19 13:44:03)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14201 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43052 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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- /home/ubuntu/envytools/envytools/rnndb/./adreno.xml ( 501 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/adreno_pm4.xml ( 43155 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a5xx.xml ( 147291 bytes, from 2019-05-29 14:51:41)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx.xml ( 148461 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2019-05-29 01:28:15)
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- /home/ubuntu/envytools/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2019-05-29 01:28:15)
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Copyright (C) 2013-2018 by the following authors:
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Copyright (C) 2013-2019 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -2148,6 +2148,8 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
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#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
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#define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
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#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
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#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
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@ -318,12 +318,18 @@ static const struct {
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void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
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gpu_write(gpu, a5xx_hwcg[i].offset,
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state ? a5xx_hwcg[i].value : 0);
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if (adreno_is_a540(adreno_gpu)) {
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0);
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0);
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}
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gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0);
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gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180);
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}
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@ -507,6 +513,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003);
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if (adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
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/* Make all blocks contribute to the GPU BUSY perf counter */
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gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF);
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@ -567,7 +576,10 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000);
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gpu_write(gpu, REG_A5XX_CP_MEQ_THRESHOLDS, 0x40);
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
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if (adreno_is_a530(adreno_gpu))
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x40);
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if (adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_CP_MERCIU_SIZE, 0x400);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_2, 0x80000060);
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gpu_write(gpu, REG_A5XX_CP_ROQ_THRESHOLDS_1, 0x40201B16);
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@ -592,6 +604,8 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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/* Set the highest bank bit */
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gpu_write(gpu, REG_A5XX_TPL1_MODE_CNTL, 2 << 7);
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gpu_write(gpu, REG_A5XX_RB_MODE_CNTL, 2 << 1);
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if (adreno_is_a540(adreno_gpu))
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gpu_write(gpu, REG_A5XX_UCHE_DBG_ECO_CNTL_2, 2);
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/* Protect registers from the CP */
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gpu_write(gpu, REG_A5XX_CP_PROTECT_CNTL, 0x00000007);
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@ -656,6 +670,16 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1);
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gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
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/*
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* VPC corner case with local memory load kill leads to corrupt
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* internal state. Normal Disable does not work for all a5x chips.
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* So do the following setting to disable it.
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*/
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if (adreno_gpu->info->quirks & ADRENO_QUIRK_LMLOADKILL_DISABLE) {
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gpu_rmw(gpu, REG_A5XX_VPC_DBG_ECO_CNTL, 0, BIT(23));
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gpu_rmw(gpu, REG_A5XX_HLSQ_DBG_ECO_CNTL, BIT(18), 0);
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}
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ret = adreno_hw_init(gpu);
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if (ret)
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return ret;
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@ -32,6 +32,18 @@
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#define AGC_POWER_CONFIG_PRODUCTION_ID 1
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#define AGC_INIT_MSG_VALUE 0xBABEFACE
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/* AGC_LM_CONFIG (A540+) */
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#define AGC_LM_CONFIG (136/4)
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#define AGC_LM_CONFIG_GPU_VERSION_SHIFT 17
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#define AGC_LM_CONFIG_ENABLE_GPMU_ADAPTIVE 1
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#define AGC_LM_CONFIG_THROTTLE_DISABLE (2 << 8)
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#define AGC_LM_CONFIG_ISENSE_ENABLE (1 << 4)
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#define AGC_LM_CONFIG_ENABLE_ERROR (3 << 4)
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#define AGC_LM_CONFIG_LLM_ENABLED (1 << 16)
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#define AGC_LM_CONFIG_BCL_DISABLED (1 << 24)
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#define AGC_LEVEL_CONFIG (140/4)
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static struct {
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uint32_t reg;
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uint32_t value;
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@ -116,7 +128,7 @@ static inline uint32_t _get_mvolts(struct msm_gpu *gpu, uint32_t freq)
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}
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/* Setup thermal limit management */
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static void a5xx_lm_setup(struct msm_gpu *gpu)
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static void a530_lm_setup(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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@ -165,6 +177,45 @@ static void a5xx_lm_setup(struct msm_gpu *gpu)
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gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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}
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#define PAYLOAD_SIZE(_size) ((_size) * sizeof(u32))
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#define LM_DCVS_LIMIT 1
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#define LEVEL_CONFIG ~(0x303)
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static void a540_lm_setup(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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u32 config;
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/* The battery current limiter isn't enabled for A540 */
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config = AGC_LM_CONFIG_BCL_DISABLED;
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config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT;
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/* For now disable GPMU side throttling */
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config |= AGC_LM_CONFIG_THROTTLE_DISABLE;
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/* Until we get clock scaling 0 is always the active power level */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0);
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/* Fixed at 6000 for now */
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000);
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gpu_write(gpu, AGC_MSG_STATE, 0x80000001);
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gpu_write(gpu, AGC_MSG_COMMAND, AGC_POWER_CONFIG_PRODUCTION_ID);
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gpu_write(gpu, AGC_MSG_PAYLOAD(0), 5448);
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gpu_write(gpu, AGC_MSG_PAYLOAD(1), 1);
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gpu_write(gpu, AGC_MSG_PAYLOAD(2), _get_mvolts(gpu, gpu->fast_rate));
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gpu_write(gpu, AGC_MSG_PAYLOAD(3), gpu->fast_rate / 1000000);
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gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LM_CONFIG), config);
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gpu_write(gpu, AGC_MSG_PAYLOAD(AGC_LEVEL_CONFIG), LEVEL_CONFIG);
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gpu_write(gpu, AGC_MSG_PAYLOAD_SIZE,
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PAYLOAD_SIZE(AGC_LEVEL_CONFIG + 1));
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gpu_write(gpu, AGC_INIT_MSG_MAGIC, AGC_INIT_MSG_VALUE);
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}
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/* Enable SP/TP cpower collapse */
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static void a5xx_pc_init(struct msm_gpu *gpu)
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{
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@ -206,7 +257,8 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
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return -EINVAL;
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}
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gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
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if (adreno_is_a530(adreno_gpu))
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gpu_write(gpu, REG_A5XX_GPMU_WFI_CONFIG, 0x4014);
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/* Kick off the GPMU */
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gpu_write(gpu, REG_A5XX_GPMU_CM3_SYSRESET, 0x0);
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@ -220,12 +272,26 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
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DRM_ERROR("%s: GPMU firmware initialization timed out\n",
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gpu->name);
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if (!adreno_is_a530(adreno_gpu)) {
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u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1);
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if (val)
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DRM_ERROR("%s: GPMU firmware initialization failed: %d\n",
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gpu->name, val);
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}
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return 0;
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}
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/* Enable limits management */
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static void a5xx_lm_enable(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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/* This init sequence only applies to A530 */
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if (!adreno_is_a530(adreno_gpu))
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return;
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gpu_write(gpu, REG_A5XX_GDPM_INT_MASK, 0x0);
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gpu_write(gpu, REG_A5XX_GDPM_INT_EN, 0x0A);
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gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK, 0x01);
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@ -237,10 +303,14 @@ static void a5xx_lm_enable(struct msm_gpu *gpu)
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int a5xx_power_init(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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int ret;
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/* Set up the limits management */
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a5xx_lm_setup(gpu);
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if (adreno_is_a530(adreno_gpu))
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a530_lm_setup(gpu);
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else
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a540_lm_setup(gpu);
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/* Set up SP/TP power collpase */
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a5xx_pc_init(gpu);
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@ -144,6 +144,24 @@ static const struct adreno_info gpulist[] = {
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ADRENO_QUIRK_FAULT_DETECT_MASK,
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.init = a5xx_gpu_init,
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.zapfw = "a530_zap.mdt",
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}, {
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.rev = ADRENO_REV(5, 4, 0, 2),
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.revn = 540,
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.name = "A540",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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[ADRENO_FW_GPMU] = "a540_gpmu.fw2",
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},
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.gmem = SZ_1M,
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE,
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.init = a5xx_gpu_init,
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.zapfw = "a540_zap.mdt",
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}, {
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.rev = ADRENO_REV(6, 3, 0, ANY_ID),
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.revn = 630,
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@ -61,6 +61,7 @@ enum {
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enum adreno_quirks {
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ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
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ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
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ADRENO_QUIRK_LMLOADKILL_DISABLE = 3,
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};
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struct adreno_rev {
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@ -221,6 +222,11 @@ static inline int adreno_is_a530(struct adreno_gpu *gpu)
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return gpu->revn == 530;
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}
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static inline int adreno_is_a540(struct adreno_gpu *gpu)
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{
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return gpu->revn == 540;
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
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const char *fwname);
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