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arm64: dts: ti: k3-j721e-main: Fix "bus-range" upto 256 bus number for PCIe

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[ Upstream commit 5f46633565b1c1e1840a927676065d72b442dac4 ]

commit 4e5833884f ("arm64: dts: ti: k3-j721e-main: Add PCIe device
tree nodes") restricted PCIe bus numbers from 0 to 15 (due to SMMU
restriction in J721E). However since SMMU is not enabled, allow the full
supported bus numbers from 0 to 255.

Fixes: 4e5833884f ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodes")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210915055358.19997-3-kishon@ti.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Kishon Vijay Abraham I 2021-09-15 11:23:54 +05:30 committed by Greg Kroah-Hartman
parent 7a1617a991
commit 20baf01638
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
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@ -629,7 +629,7 @@ pcie0_rc: pcie@2900000 {
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
@ -678,7 +678,7 @@ pcie1_rc: pcie@2910000 {
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
@ -727,7 +727,7 @@ pcie2_rc: pcie@2920000 {
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x20000 0x10000>;
@ -776,7 +776,7 @@ pcie3_rc: pcie@2930000 {
clock-names = "fck";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x0 0xf>;
bus-range = <0x0 0xff>;
vendor-id = <0x104c>;
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x30000 0x10000>;