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[PATCH] ARM: Clean up commenting/spacing for Integrator

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Signed-off-by: Russell King <rmk@arm.linux.org.uk>
This commit is contained in:
Russell King 2005-05-03 12:22:19 +01:00
parent 5c3073e691
commit 1f9c381fa3
3 changed files with 59 additions and 57 deletions
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6
arch/arm/mach-integrator/core.c
View File

@ -216,7 +216,9 @@ integrator_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
write_seqlock(&xtime_lock); write_seqlock(&xtime_lock);
// ...clear the interrupt /*
* clear the interrupt
*/
timer1->TimerClear = 1; timer1->TimerClear = 1;
timer_tick(regs); timer_tick(regs);
@ -264,7 +266,7 @@ void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
timer1->TimerValue = timer_reload; timer1->TimerValue = timer_reload;
timer1->TimerControl = timer_ctrl; timer1->TimerControl = timer_ctrl;
/* /*
* Make irqs happen for the system timer * Make irqs happen for the system timer
*/ */
setup_irq(IRQ_TIMERINT1, &integrator_timer_irq); setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);

2
arch/arm/mach-integrator/leds.c
View File

@ -37,7 +37,7 @@ static void integrator_leds_event(led_event_t ledevt)
unsigned long flags; unsigned long flags;
const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE); const unsigned int dbg_base = IO_ADDRESS(INTEGRATOR_DBG_BASE);
unsigned int update_alpha_leds; unsigned int update_alpha_leds;
// yup, change the LEDs // yup, change the LEDs
local_irq_save(flags); local_irq_save(flags);
update_alpha_leds = 0; update_alpha_leds = 0;

108
include/asm-arm/arch-integrator/platform.h
View File

@ -20,14 +20,14 @@
* * Copyright © ARM Limited 1998. All rights reserved. * * Copyright © ARM Limited 1998. All rights reserved.
* ***********************************************************************/ * ***********************************************************************/
/* ************************************************************************ /* ************************************************************************
* *
* Integrator address map * Integrator address map
* *
* NOTE: This is a multi-hosted header file for use with uHAL and * NOTE: This is a multi-hosted header file for use with uHAL and
* supported debuggers. * supported debuggers.
* *
* $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $ * $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
* *
* ***********************************************************************/ * ***********************************************************************/
#ifndef __address_h #ifndef __address_h
@ -40,22 +40,22 @@
* Memory definitions * Memory definitions
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* Integrator memory map * Integrator memory map
* *
*/ */
#define INTEGRATOR_BOOT_ROM_LO 0x00000000 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
#define INTEGRATOR_BOOT_ROM_HI 0x20000000 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */ #define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K #define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
/* /*
* New Core Modules have different amounts of SSRAM, the amount of SSRAM * New Core Modules have different amounts of SSRAM, the amount of SSRAM
* fitted can be found in HDR_STAT. * fitted can be found in HDR_STAT.
* *
* The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to * The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
* the minimum amount of SSRAM fitted on any core module. * the minimum amount of SSRAM fitted on any core module.
* *
* New Core Modules also alias the SSRAM. * New Core Modules also alias the SSRAM.
* *
*/ */
#define INTEGRATOR_SSRAM_BASE 0x00000000 #define INTEGRATOR_SSRAM_BASE 0x00000000
#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
@ -67,9 +67,9 @@
#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K #define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
/* /*
* SDRAM is a SIMM therefore the size is not known. * SDRAM is a SIMM therefore the size is not known.
* *
*/ */
#define INTEGRATOR_SDRAM_BASE 0x00040000 #define INTEGRATOR_SDRAM_BASE 0x00040000
@ -79,9 +79,9 @@
#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000 #define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000 #define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
/* /*
* Logic expansion modules * Logic expansion modules
* *
*/ */
#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000 #define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000 #define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
@ -92,7 +92,7 @@
/* ------------------------------------------------------------------------ /* ------------------------------------------------------------------------
* Integrator header card registers * Integrator header card registers
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* *
*/ */
#define INTEGRATOR_HDR_ID_OFFSET 0x00 #define INTEGRATOR_HDR_ID_OFFSET 0x00
#define INTEGRATOR_HDR_PROC_OFFSET 0x04 #define INTEGRATOR_HDR_PROC_OFFSET 0x04
@ -185,12 +185,12 @@
/* ------------------------------------------------------------------------ /* ------------------------------------------------------------------------
* Integrator system registers * Integrator system registers
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* *
*/ */
/* /*
* System Controller * System Controller
* *
*/ */
#define INTEGRATOR_SC_ID_OFFSET 0x00 #define INTEGRATOR_SC_ID_OFFSET 0x00
#define INTEGRATOR_SC_OSC_OFFSET 0x04 #define INTEGRATOR_SC_OSC_OFFSET 0x04
@ -230,11 +230,11 @@
#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6) #define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7) #define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
/* /*
* External Bus Interface * External Bus Interface
* *
*/ */
#define INTEGRATOR_EBI_BASE 0x12000000 #define INTEGRATOR_EBI_BASE 0x12000000
#define INTEGRATOR_EBI_CSR0_OFFSET 0x00 #define INTEGRATOR_EBI_CSR0_OFFSET 0x00
#define INTEGRATOR_EBI_CSR1_OFFSET 0x04 #define INTEGRATOR_EBI_CSR1_OFFSET 0x04
@ -279,9 +279,9 @@
#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */ #define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */ #define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
/* /*
* LED's & Switches * LED's & Switches
* *
*/ */
#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00 #define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
#define INTEGRATOR_DBG_LEDS_OFFSET 0x04 #define INTEGRATOR_DBG_LEDS_OFFSET 0x04
@ -300,7 +300,7 @@
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
*/ */
/* PS2 Keyboard interface */ /* PS2 Keyboard interface */
#define KMI0_BASE INTEGRATOR_KBD_BASE #define KMI0_BASE INTEGRATOR_KBD_BASE
/* PS2 Mouse interface */ /* PS2 Mouse interface */
#define KMI1_BASE INTEGRATOR_MOUSE_BASE #define KMI1_BASE INTEGRATOR_MOUSE_BASE
@ -313,7 +313,7 @@
* This represents a fairly liberal usage of address space. Even though * This represents a fairly liberal usage of address space. Even though
* the V3 only has two windows (therefore we need to map stuff on the fly), * the V3 only has two windows (therefore we need to map stuff on the fly),
* we maintain the same addresses, even if they're not mapped. * we maintain the same addresses, even if they're not mapped.
* *
*/ */
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */ #define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? /* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
@ -326,7 +326,7 @@
*/ */
#define PHYS_PCI_V3_BASE 0x62000000 #define PHYS_PCI_V3_BASE 0x62000000
#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE #define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
/* 'export' these to UHAL */ /* 'export' these to UHAL */
#define UHAL_PCI_IO PCI_IO_BASE #define UHAL_PCI_IO PCI_IO_BASE
@ -334,7 +334,7 @@
#define UHAL_PCI_ALLOC_IO_BASE 0x00004000 #define UHAL_PCI_ALLOC_IO_BASE 0x00004000
#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE #define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
#define UHAL_PCI_MAX_SLOT 20 #define UHAL_PCI_MAX_SLOT 20
/* ======================================================================== /* ========================================================================
* Start of uHAL definitions * Start of uHAL definitions
* ======================================================================== * ========================================================================
@ -343,17 +343,17 @@
/* ------------------------------------------------------------------------ /* ------------------------------------------------------------------------
* Integrator Interrupt Controllers * Integrator Interrupt Controllers
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* *
* Offsets from interrupt controller base * Offsets from interrupt controller base
* *
* System Controller interrupt controller base is * System Controller interrupt controller base is
* *
* INTEGRATOR_IC_BASE + (header_number << 6) * INTEGRATOR_IC_BASE + (header_number << 6)
* *
* Core Module interrupt controller base is * Core Module interrupt controller base is
* *
* INTEGRATOR_HDR_IC * INTEGRATOR_HDR_IC
* *
*/ */
#define IRQ_STATUS 0 #define IRQ_STATUS 0
#define IRQ_RAW_STATUS 0x04 #define IRQ_RAW_STATUS 0x04
@ -374,22 +374,22 @@
/* ------------------------------------------------------------------------ /* ------------------------------------------------------------------------
* Interrupts * Interrupts
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* *
* *
* Each Core Module has two interrupts controllers, one on the core module * Each Core Module has two interrupts controllers, one on the core module
* itself and one in the system controller on the motherboard. The * itself and one in the system controller on the motherboard. The
* READ_INT macro in target.s reads both interrupt controllers and returns * READ_INT macro in target.s reads both interrupt controllers and returns
* a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller * a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
* and bits 24 to 31 are from the core module. * and bits 24 to 31 are from the core module.
* *
* The following definitions relate to the bitmask returned by READ_INT. * The following definitions relate to the bitmask returned by READ_INT.
* *
*/ */
/* ------------------------------------------------------------------------ /* ------------------------------------------------------------------------
* LED's - The header LED is not accessible via the uHAL API * LED's - The header LED is not accessible via the uHAL API
* ------------------------------------------------------------------------ * ------------------------------------------------------------------------
* *
*/ */
#define GREEN_LED 0x01 #define GREEN_LED 0x01
#define YELLOW_LED 0x02 #define YELLOW_LED 0x02
@ -399,44 +399,44 @@
#define LED_BANK INTEGRATOR_DBG_LEDS #define LED_BANK INTEGRATOR_DBG_LEDS
/* /*
* Memory definitions - run uHAL out of SSRAM. * Memory definitions - run uHAL out of SSRAM.
* *
*/ */
#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE #define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
/* /*
* Application Flash * Application Flash
* *
*/ */
#define FLASH_BASE INTEGRATOR_FLASH_BASE #define FLASH_BASE INTEGRATOR_FLASH_BASE
#define FLASH_SIZE INTEGRATOR_FLASH_SIZE #define FLASH_SIZE INTEGRATOR_FLASH_SIZE
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE SZ_128K #define FLASH_BLOCK_SIZE SZ_128K
/* /*
* Boot Flash * Boot Flash
* *
*/ */
#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI #define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE #define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
/* /*
* Clean base - dummy * Clean base - dummy
* *
*/ */
#define CLEAN_BASE EPROM_BASE #define CLEAN_BASE EPROM_BASE
/* /*
* Timer definitions * Timer definitions
* *
* Only use timer 1 & 2 * Only use timer 1 & 2
* (both run at 24MHz and will need the clock divider set to 16). * (both run at 24MHz and will need the clock divider set to 16).
* *
* Timer 0 runs at bus frequency and therefore could vary and currently * Timer 0 runs at bus frequency and therefore could vary and currently
* uHAL can't handle that. * uHAL can't handle that.
* *
*/ */
#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE #define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
@ -447,9 +447,9 @@
#define MAX_PERIOD 699050 #define MAX_PERIOD 699050
#define TICKS_PER_uSEC 24 #define TICKS_PER_uSEC 24
/* /*
* These are useconds NOT ticks. * These are useconds NOT ticks.
* *
*/ */
#define mSEC_1 1000 #define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5) #define mSEC_5 (mSEC_1 * 5)