Merge 5.10.67 into android12-5.10-lts
Changes in 5.10.67
rtc: tps65910: Correct driver module alias
io_uring: limit fixed table size by RLIMIT_NOFILE
io_uring: place fixed tables under memcg limits
io_uring: add ->splice_fd_in checks
io_uring: fail links of cancelled timeouts
io-wq: fix wakeup race when adding new work
btrfs: wake up async_delalloc_pages waiters after submit
btrfs: reset replace target device to allocation state on close
blk-zoned: allow zone management send operations without CAP_SYS_ADMIN
blk-zoned: allow BLKREPORTZONE without CAP_SYS_ADMIN
PCI/MSI: Skip masking MSI-X on Xen PV
powerpc/perf/hv-gpci: Fix counter value parsing
xen: fix setting of max_pfn in shared_info
9p/xen: Fix end of loop tests for list_for_each_entry
ceph: fix dereference of null pointer cf
selftests/ftrace: Fix requirement check of README file
tools/thermal/tmon: Add cross compiling support
clk: socfpga: agilex: fix the parents of the psi_ref_clk
clk: socfpga: agilex: fix up s2f_user0_clk representation
clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
pinctrl: stmfx: Fix hazardous u8[] to unsigned long cast
pinctrl: ingenic: Fix incorrect pull up/down info
soc: qcom: aoss: Fix the out of bound usage of cooling_devs
soc: aspeed: lpc-ctrl: Fix boundary check for mmap
soc: aspeed: p2a-ctrl: Fix boundary check for mmap
arm64: mm: Fix TLBI vs ASID rollover
arm64: head: avoid over-mapping in map_memory
iio: ltc2983: fix device probe
wcn36xx: Ensure finish scan is not requested before start scan
crypto: public_key: fix overflow during implicit conversion
block: bfq: fix bfq_set_next_ioprio_data()
power: supply: max17042: handle fails of reading status register
dm crypt: Avoid percpu_counter spinlock contention in crypt_page_alloc()
crypto: ccp - shutdown SEV firmware on kexec
VMCI: fix NULL pointer dereference when unmapping queue pair
media: uvc: don't do DMA on stack
media: rc-loopback: return number of emitters rather than error
s390/qdio: fix roll-back after timeout on ESTABLISH ccw
s390/qdio: cancel the ESTABLISH ccw after timeout
Revert "dmaengine: imx-sdma: refine to load context only once"
dmaengine: imx-sdma: remove duplicated sdma_load_context
libata: add ATA_HORKAGE_NO_NCQ_TRIM for Samsung 860 and 870 SSDs
ARM: 9105/1: atags_to_fdt: don't warn about stack size
f2fs: fix to do sanity check for sb/cp fields correctly
PCI/portdrv: Enable Bandwidth Notification only if port supports it
PCI: Restrict ASMedia ASM1062 SATA Max Payload Size Supported
PCI: Return ~0 data on pciconfig_read() CAP_SYS_ADMIN failure
PCI: xilinx-nwl: Enable the clock through CCF
PCI: aardvark: Configure PCIe resources from 'ranges' DT property
PCI: Export pci_pio_to_address() for module use
PCI: aardvark: Fix checking for PIO status
PCI: aardvark: Fix masking and unmasking legacy INTx interrupts
HID: input: do not report stylus battery state as "full"
f2fs: quota: fix potential deadlock
pinctrl: remove empty lines in pinctrl subsystem
pinctrl: armada-37xx: Correct PWM pins definitions
scsi: bsg: Remove support for SCSI_IOCTL_SEND_COMMAND
clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
IB/hfi1: Adjust pkey entry in index 0
RDMA/iwcm: Release resources if iw_cm module initialization fails
docs: Fix infiniband uverbs minor number
scsi: BusLogic: Use %X for u32 sized integer rather than %lX
pinctrl: samsung: Fix pinctrl bank pin count
vfio: Use config not menuconfig for VFIO_NOIOMMU
scsi: ufs: Fix memory corruption by ufshcd_read_desc_param()
cpuidle: pseries: Fixup CEDE0 latency only for POWER10 onwards
powerpc/stacktrace: Include linux/delay.h
RDMA/efa: Remove double QP type assignment
RDMA/mlx5: Delete not-available udata check
cpuidle: pseries: Mark pseries_idle_proble() as __init
f2fs: reduce the scope of setting fsck tag when de->name_len is zero
openrisc: don't printk() unconditionally
dma-debug: fix debugfs initialization order
NFSv4/pNFS: Fix a layoutget livelock loop
NFSv4/pNFS: Always allow update of a zero valued layout barrier
NFSv4/pnfs: The layout barrier indicate a minimal value for the seqid
SUNRPC: Fix potential memory corruption
SUNRPC/xprtrdma: Fix reconnection locking
SUNRPC query transport's source port
sunrpc: Fix return value of get_srcport()
scsi: fdomain: Fix error return code in fdomain_probe()
pinctrl: single: Fix error return code in pcs_parse_bits_in_pinctrl_entry()
powerpc/numa: Consider the max NUMA node for migratable LPAR
scsi: smartpqi: Fix an error code in pqi_get_raid_map()
scsi: qedi: Fix error codes in qedi_alloc_global_queues()
scsi: qedf: Fix error codes in qedf_alloc_global_queues()
powerpc/config: Renable MTD_PHYSMAP_OF
iommu/vt-d: Update the virtual command related registers
HID: i2c-hid: Fix Elan touchpad regression
clk: imx8m: fix clock tree update of TF-A managed clocks
KVM: PPC: Book3S HV: Fix copy_tofrom_guest routines
scsi: ufs: ufs-exynos: Fix static checker warning
KVM: PPC: Book3S HV Nested: Reflect guest PMU in-use to L0 when guest SPRs are live
platform/x86: dell-smbios-wmi: Add missing kfree in error-exit from run_smbios_call
powerpc/smp: Update cpu_core_map on all PowerPc systems
RDMA/hns: Fix QP's resp incomplete assignment
fscache: Fix cookie key hashing
clk: at91: clk-generated: Limit the requested rate to our range
KVM: PPC: Fix clearing never mapped TCEs in realmode
soc: mediatek: cmdq: add address shift in jump
f2fs: fix to account missing .skipped_gc_rwsem
f2fs: fix unexpected ENOENT comes from f2fs_map_blocks()
f2fs: fix to unmap pages from userspace process in punch_hole()
f2fs: deallocate compressed pages when error happens
f2fs: should put a page beyond EOF when preparing a write
MIPS: Malta: fix alignment of the devicetree buffer
kbuild: Fix 'no symbols' warning when CONFIG_TRIM_UNUSD_KSYMS=y
userfaultfd: prevent concurrent API initialization
drm/vc4: hdmi: Set HD_CTL_WHOLSMP and HD_CTL_CHALIGN_SET
drm/amdgpu: Fix amdgpu_ras_eeprom_init()
ASoC: atmel: ATMEL drivers don't need HAS_DMA
media: dib8000: rewrite the init prbs logic
libbpf: Fix reuse of pinned map on older kernel
x86/hyperv: fix for unwanted manipulation of sched_clock when TSC marked unstable
crypto: mxs-dcp - Use sg_mapping_iter to copy data
PCI: Use pci_update_current_state() in pci_enable_device_flags()
tipc: keep the skb in rcv queue until the whole data is read
net: phy: Fix data type in DP83822 dp8382x_disable_wol()
iio: dac: ad5624r: Fix incorrect handling of an optional regulator.
iavf: do not override the adapter state in the watchdog task
iavf: fix locking of critical sections
ARM: dts: qcom: apq8064: correct clock names
video: fbdev: kyro: fix a DoS bug by restricting user input
netlink: Deal with ESRCH error in nlmsg_notify()
Smack: Fix wrong semantics in smk_access_entry()
drm: avoid blocking in drm_clients_info's rcu section
drm: serialize drm_file.master with a new spinlock
drm: protect drm_master pointers in drm_lease.c
rcu: Fix macro name CONFIG_TASKS_RCU_TRACE
igc: Check if num of q_vectors is smaller than max before array access
usb: host: fotg210: fix the endpoint's transactional opportunities calculation
usb: host: fotg210: fix the actual_length of an iso packet
usb: gadget: u_ether: fix a potential null pointer dereference
USB: EHCI: ehci-mv: improve error handling in mv_ehci_enable()
usb: gadget: composite: Allow bMaxPower=0 if self-powered
staging: board: Fix uninitialized spinlock when attaching genpd
tty: serial: jsm: hold port lock when reporting modem line changes
bus: fsl-mc: fix mmio base address for child DPRCs
selftests: firmware: Fix ignored return val of asprintf() warn
drm/amd/display: Fix timer_per_pixel unit error
media: hantro: vp8: Move noisy WARN_ON to vpu_debug
media: platform: stm32: unprepare clocks at handling errors in probe
media: atomisp: Fix runtime PM imbalance in atomisp_pci_probe
media: atomisp: pci: fix error return code in atomisp_pci_probe()
nfp: fix return statement in nfp_net_parse_meta()
ethtool: improve compat ioctl handling
drm/amdgpu: Fix a printing message
drm/amd/amdgpu: Update debugfs link_settings output link_rate field in hex
bpf/tests: Fix copy-and-paste error in double word test
bpf/tests: Do not PASS tests without actually testing the result
drm/bridge: nwl-dsi: Avoid potential multiplication overflow on 32-bit
arm64: dts: allwinner: h6: tanix-tx6: Fix regulator node names
video: fbdev: asiliantfb: Error out if 'pixclock' equals zero
video: fbdev: kyro: Error out if 'pixclock' equals zero
video: fbdev: riva: Error out if 'pixclock' equals zero
ipv4: ip_output.c: Fix out-of-bounds warning in ip_copy_addrs()
flow_dissector: Fix out-of-bounds warnings
s390/jump_label: print real address in a case of a jump label bug
s390: make PCI mio support a machine flag
serial: 8250: Define RX trigger levels for OxSemi 950 devices
xtensa: ISS: don't panic in rs_init
hvsi: don't panic on tty_register_driver failure
serial: 8250_pci: make setup_port() parameters explicitly unsigned
staging: ks7010: Fix the initialization of the 'sleep_status' structure
samples: bpf: Fix tracex7 error raised on the missing argument
libbpf: Fix race when pinning maps in parallel
ata: sata_dwc_460ex: No need to call phy_exit() befre phy_init()
Bluetooth: skip invalid hci_sync_conn_complete_evt
workqueue: Fix possible memory leaks in wq_numa_init()
ARM: dts: stm32: Set {bitclock,frame}-master phandles on DHCOM SoM
ARM: dts: stm32: Set {bitclock,frame}-master phandles on ST DKx
ARM: dts: stm32: Update AV96 adv7513 node per dtbs_check
bonding: 3ad: fix the concurrency between __bond_release_one() and bond_3ad_state_machine_handler()
ARM: dts: at91: use the right property for shutdown controller
arm64: tegra: Fix Tegra194 PCIe EP compatible string
ASoC: Intel: bytcr_rt5640: Move "Platform Clock" routes to the maps for the matching in-/output
ASoC: Intel: update sof_pcm512x quirks
media: imx258: Rectify mismatch of VTS value
media: imx258: Limit the max analogue gain to 480
media: v4l2-dv-timings.c: fix wrong condition in two for-loops
media: TDA1997x: fix tda1997x_query_dv_timings() return value
media: tegra-cec: Handle errors of clk_prepare_enable()
gfs2: Fix glock recursion in freeze_go_xmote_bh
arm64: dts: qcom: sdm630: Rewrite memory map
arm64: dts: qcom: sdm630: Fix TLMM node and pinctrl configuration
serial: 8250_omap: Handle optional overrun-throttle-ms property
ARM: dts: imx53-ppd: Fix ACHC entry
arm64: dts: qcom: ipq8074: fix pci node reg property
arm64: dts: qcom: sdm660: use reg value for memory node
arm64: dts: qcom: ipq6018: drop '0x' from unit address
arm64: dts: qcom: sdm630: don't use underscore in node name
arm64: dts: qcom: msm8994: don't use underscore in node name
arm64: dts: qcom: msm8996: don't use underscore in node name
arm64: dts: qcom: sm8250: Fix epss_l3 unit address
nvmem: qfprom: Fix up qfprom_disable_fuse_blowing() ordering
net: ethernet: stmmac: Do not use unreachable() in ipq806x_gmac_probe()
drm/msm: mdp4: drop vblank get/put from prepare/complete_commit
drm/msm/dsi: Fix DSI and DSI PHY regulator config from SDM660
drm: xlnx: zynqmp_dpsub: Call pm_runtime_get_sync before setting pixel clock
drm: xlnx: zynqmp: release reset to DP controller before accessing DP registers
thunderbolt: Fix port linking by checking all adapters
drm/amd/display: fix missing writeback disablement if plane is removed
drm/amd/display: fix incorrect CM/TF programming sequence in dwb
selftests/bpf: Fix xdp_tx.c prog section name
drm/vmwgfx: fix potential UAF in vmwgfx_surface.c
Bluetooth: schedule SCO timeouts with delayed_work
Bluetooth: avoid circular locks in sco_sock_connect
drm/msm/dp: return correct edid checksum after corrupted edid checksum read
net/mlx5: Fix variable type to match 64bit
gpu: drm: amd: amdgpu: amdgpu_i2c: fix possible uninitialized-variable access in amdgpu_i2c_router_select_ddc_port()
drm/display: fix possible null-pointer dereference in dcn10_set_clock()
mac80211: Fix monitor MTU limit so that A-MSDUs get through
ARM: tegra: acer-a500: Remove bogus USB VBUS regulators
ARM: tegra: tamonten: Fix UART pad setting
arm64: tegra: Fix compatible string for Tegra132 CPUs
arm64: dts: ls1046a: fix eeprom entries
nvme-tcp: don't check blk_mq_tag_to_rq when receiving pdu data
nvme: code command_id with a genctr for use-after-free validation
Bluetooth: Fix handling of LE Enhanced Connection Complete
opp: Don't print an error if required-opps is missing
serial: sh-sci: fix break handling for sysrq
iomap: pass writeback errors to the mapping
tcp: enable data-less, empty-cookie SYN with TFO_SERVER_COOKIE_NOT_REQD
rpc: fix gss_svc_init cleanup on failure
selftests/bpf: Fix flaky send_signal test
hwmon: (pmbus/ibm-cffps) Fix write bits for LED control
staging: rts5208: Fix get_ms_information() heap buffer size
net: Fix offloading indirect devices dependency on qdisc order creation
kselftest/arm64: mte: Fix misleading output when skipping tests
kselftest/arm64: pac: Fix skipping of tests on systems without PAC
gfs2: Don't call dlm after protocol is unmounted
usb: chipidea: host: fix port index underflow and UBSAN complains
lockd: lockd server-side shouldn't set fl_ops
drm/exynos: Always initialize mapping in exynos_drm_register_dma()
rtl8xxxu: Fix the handling of TX A-MPDU aggregation
rtw88: use read_poll_timeout instead of fixed sleep
rtw88: wow: build wow function only if CONFIG_PM is on
rtw88: wow: fix size access error of probe request
octeontx2-pf: Fix NIX1_RX interface backpressure
m68knommu: only set CONFIG_ISA_DMA_API for ColdFire sub-arch
btrfs: tree-log: check btrfs_lookup_data_extent return value
soundwire: intel: fix potential race condition during power down
ASoC: Intel: Skylake: Fix module configuration for KPB and MIXER
ASoC: Intel: Skylake: Fix passing loadable flag for module
of: Don't allow __of_attached_node_sysfs() without CONFIG_SYSFS
mmc: sdhci-of-arasan: Modified SD default speed to 19MHz for ZynqMP
mmc: sdhci-of-arasan: Check return value of non-void funtions
mmc: rtsx_pci: Fix long reads when clock is prescaled
selftests/bpf: Enlarge select() timeout for test_maps
mmc: core: Return correct emmc response in case of ioctl error
cifs: fix wrong release in sess_alloc_buffer() failed path
Revert "USB: xhci: fix U1/U2 handling for hardware with XHCI_INTEL_HOST quirk set"
usb: musb: musb_dsps: request_irq() after initializing musb
usbip: give back URBs for unsent unlink requests during cleanup
usbip:vhci_hcd USB port can get stuck in the disabled state
ASoC: rockchip: i2s: Fix regmap_ops hang
ASoC: rockchip: i2s: Fixup config for DAIFMT_DSP_A/B
drm/amdkfd: Account for SH/SE count when setting up cu masks.
nfsd: fix crash on LOCKT on reexported NFSv3
iwlwifi: pcie: free RBs during configure
iwlwifi: mvm: fix a memory leak in iwl_mvm_mac_ctxt_beacon_changed
iwlwifi: mvm: avoid static queue number aliasing
iwlwifi: mvm: fix access to BSS elements
iwlwifi: fw: correctly limit to monitor dump
iwlwifi: mvm: Fix scan channel flags settings
net/mlx5: DR, fix a potential use-after-free bug
net/mlx5: DR, Enable QP retransmission
parport: remove non-zero check on count
selftests/bpf: Fix potential unreleased lock
wcn36xx: Fix missing frame timestamp for beacon/probe-resp
ath9k: fix OOB read ar9300_eeprom_restore_internal
ath9k: fix sleeping in atomic context
net: fix NULL pointer reference in cipso_v4_doi_free
fix array-index-out-of-bounds in taprio_change
net: w5100: check return value after calling platform_get_resource()
net: hns3: clean up a type mismatch warning
fs/io_uring Don't use the return value from import_iovec().
io_uring: remove duplicated io_size from rw
parisc: fix crash with signals and alloca
ovl: fix BUG_ON() in may_delete() when called from ovl_cleanup()
scsi: BusLogic: Fix missing pr_cont() use
scsi: qla2xxx: Changes to support kdump kernel
scsi: qla2xxx: Sync queue idx with queue_pair_map idx
cpufreq: powernv: Fix init_chip_info initialization in numa=off
s390/pv: fix the forcing of the swiotlb
hugetlb: fix hugetlb cgroup refcounting during vma split
mm/hmm: bypass devmap pte when all pfn requested flags are fulfilled
mm/hugetlb: initialize hugetlb_usage in mm_init
mm,vmscan: fix divide by zero in get_scan_count
memcg: enable accounting for pids in nested pid namespaces
libnvdimm/pmem: Fix crash triggered when I/O in-flight during unbind
platform/chrome: cros_ec_proto: Send command again when timeout occurs
lib/test_stackinit: Fix static initializer test
net: dsa: lantiq_gswip: fix maximum frame length
drm/mgag200: Select clock in PLL update functions
drm/msi/mdp4: populate priv->kms in mdp4_kms_init
drm/dp_mst: Fix return code on sideband message failure
drm/panfrost: Make sure MMU context lifetime is not bound to panfrost_priv
drm/amdgpu: Fix BUG_ON assert
drm/amd/display: Update number of DCN3 clock states
drm/amd/display: Update bounding box states (v2)
drm/panfrost: Simplify lock_region calculation
drm/panfrost: Use u64 for size in lock_region
drm/panfrost: Clamp lock region to Bifrost minimum
fanotify: limit number of event merge attempts
Linux 5.10.67
Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: Ic8df59518265d0cdf724e93e8922cde48fc85ce9
This commit is contained in:
Greg Kroah-Hartman
commit
08ed4cb090
@ -3003,10 +3003,10 @@
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|||||||
65 = /dev/infiniband/issm1 Second InfiniBand IsSM device
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65 = /dev/infiniband/issm1 Second InfiniBand IsSM device
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||||||
...
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...
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||||||
127 = /dev/infiniband/issm63 63rd InfiniBand IsSM device
|
127 = /dev/infiniband/issm63 63rd InfiniBand IsSM device
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||||||
128 = /dev/infiniband/uverbs0 First InfiniBand verbs device
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192 = /dev/infiniband/uverbs0 First InfiniBand verbs device
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||||||
129 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
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193 = /dev/infiniband/uverbs1 Second InfiniBand verbs device
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||||||
...
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...
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159 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
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223 = /dev/infiniband/uverbs31 31st InfiniBand verbs device
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||||||
|
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232 char Biometric Devices
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232 char Biometric Devices
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0 = /dev/biometric/sensor0/fingerprint first fingerprint sensor on first device
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0 = /dev/biometric/sensor0/fingerprint first fingerprint sensor on first device
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@ -43,19 +43,19 @@ group emmc_nb
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group pwm0
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group pwm0
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- pin 11 (GPIO1-11)
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- pin 11 (GPIO1-11)
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm1
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group pwm1
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- pin 12
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- pin 12
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm2
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group pwm2
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- pin 13
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- pin 13
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pwm3
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group pwm3
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- pin 14
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- pin 14
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- functions pwm, gpio
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- functions pwm, led, gpio
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group pmic1
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group pmic1
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- pin 7
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- pin 7
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2
Makefile
2
Makefile
@ -1,7 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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# SPDX-License-Identifier: GPL-2.0
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VERSION = 5
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VERSION = 5
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PATCHLEVEL = 10
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PATCHLEVEL = 10
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SUBLEVEL = 66
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SUBLEVEL = 67
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EXTRAVERSION =
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EXTRAVERSION =
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NAME = Dare mighty things
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NAME = Dare mighty things
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@ -84,6 +84,8 @@ compress-$(CONFIG_KERNEL_LZ4) = lz4
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libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o
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libfdt_objs := fdt_rw.o fdt_ro.o fdt_wip.o fdt.o
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ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
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ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
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CFLAGS_REMOVE_atags_to_fdt.o += -Wframe-larger-than=${CONFIG_FRAME_WARN}
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CFLAGS_atags_to_fdt.o += -Wframe-larger-than=1280
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OBJS += $(libfdt_objs) atags_to_fdt.o
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OBJS += $(libfdt_objs) atags_to_fdt.o
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endif
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endif
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@ -336,7 +336,7 @@ &pwm0 {
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};
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};
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&shutdown_controller {
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&shutdown_controller {
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atmel,shdwc-debouncer = <976>;
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debounce-delay-us = <976>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtc-timer;
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input@0 {
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input@0 {
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@ -662,7 +662,7 @@ &rtt {
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};
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};
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&shutdown_controller {
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&shutdown_controller {
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atmel,shdwc-debouncer = <976>;
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debounce-delay-us = <976>;
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status = "okay";
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status = "okay";
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|
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input@0 {
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input@0 {
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@ -138,7 +138,7 @@ i2c3: i2c@600 {
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};
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};
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|
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shdwc@f8048010 {
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shdwc@f8048010 {
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atmel,shdwc-debouncer = <976>;
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debounce-delay-us = <976>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtc-timer;
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|
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input@0 {
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input@0 {
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@ -205,7 +205,7 @@ &sdmmc0 {
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};
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};
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|
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&shutdown_controller {
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&shutdown_controller {
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atmel,shdwc-debouncer = <976>;
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debounce-delay-us = <976>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtc-timer;
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|
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input@0 {
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input@0 {
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@ -693,7 +693,7 @@ &sdmmc0 {
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};
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};
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|
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&shutdown_controller {
|
&shutdown_controller {
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||||||
atmel,shdwc-debouncer = <976>;
|
debounce-delay-us = <976>;
|
||||||
atmel,wakeup-rtc-timer;
|
atmel,wakeup-rtc-timer;
|
||||||
|
|
||||||
input@0 {
|
input@0 {
|
||||||
|
|||||||
@ -203,7 +203,7 @@ i2c2: i2c@600 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
shdwc@f8048010 {
|
shdwc@f8048010 {
|
||||||
atmel,shdwc-debouncer = <976>;
|
debounce-delay-us = <976>;
|
||||||
|
|
||||||
input@0 {
|
input@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
|
|||||||
@ -347,7 +347,7 @@ i2c2: i2c@600 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
shdwc@f8048010 {
|
shdwc@f8048010 {
|
||||||
atmel,shdwc-debouncer = <976>;
|
debounce-delay-us = <976>;
|
||||||
atmel,wakeup-rtc-timer;
|
atmel,wakeup-rtc-timer;
|
||||||
|
|
||||||
input@0 {
|
input@0 {
|
||||||
|
|||||||
@ -70,6 +70,12 @@ cko2_11M: sgtl-clock-cko2 {
|
|||||||
clock-frequency = <11289600>;
|
clock-frequency = <11289600>;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
achc_24M: achc-clock {
|
||||||
|
compatible = "fixed-clock";
|
||||||
|
#clock-cells = <0>;
|
||||||
|
clock-frequency = <24000000>;
|
||||||
|
};
|
||||||
|
|
||||||
sgtlsound: sound {
|
sgtlsound: sound {
|
||||||
compatible = "fsl,imx53-cpuvo-sgtl5000",
|
compatible = "fsl,imx53-cpuvo-sgtl5000",
|
||||||
"fsl,imx-audio-sgtl5000";
|
"fsl,imx-audio-sgtl5000";
|
||||||
@ -313,16 +319,13 @@ &gpio4 11 GPIO_ACTIVE_LOW
|
|||||||
&gpio4 12 GPIO_ACTIVE_LOW>;
|
&gpio4 12 GPIO_ACTIVE_LOW>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
|
|
||||||
spidev0: spi@0 {
|
spidev0: spi@1 {
|
||||||
compatible = "ge,achc";
|
compatible = "ge,achc", "nxp,kinetis-k20";
|
||||||
reg = <0>;
|
reg = <1>, <0>;
|
||||||
spi-max-frequency = <1000000>;
|
vdd-supply = <®_3v3>;
|
||||||
};
|
vdda-supply = <®_3v3>;
|
||||||
|
clocks = <&achc_24M>;
|
||||||
spidev1: spi@1 {
|
reset-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
|
||||||
compatible = "ge,achc";
|
|
||||||
reg = <1>;
|
|
||||||
spi-max-frequency = <1000000>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
gpioxra0: gpio@2 {
|
gpioxra0: gpio@2 {
|
||||||
|
|||||||
@ -1262,9 +1262,9 @@ dsi0: mdss_dsi@4700000 {
|
|||||||
<&mmcc DSI1_BYTE_CLK>,
|
<&mmcc DSI1_BYTE_CLK>,
|
||||||
<&mmcc DSI_PIXEL_CLK>,
|
<&mmcc DSI_PIXEL_CLK>,
|
||||||
<&mmcc DSI1_ESC_CLK>;
|
<&mmcc DSI1_ESC_CLK>;
|
||||||
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
|
clock-names = "iface", "bus", "core_mmss",
|
||||||
"src_clk", "byte_clk", "pixel_clk",
|
"src", "byte", "pixel",
|
||||||
"core_clk";
|
"core";
|
||||||
|
|
||||||
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
|
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
|
||||||
<&mmcc DSI1_ESC_SRC>,
|
<&mmcc DSI1_ESC_SRC>,
|
||||||
|
|||||||
@ -172,15 +172,15 @@ sgtl5000_port: port {
|
|||||||
sgtl5000_tx_endpoint: endpoint@0 {
|
sgtl5000_tx_endpoint: endpoint@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
remote-endpoint = <&sai2a_endpoint>;
|
remote-endpoint = <&sai2a_endpoint>;
|
||||||
frame-master;
|
frame-master = <&sgtl5000_tx_endpoint>;
|
||||||
bitclock-master;
|
bitclock-master = <&sgtl5000_tx_endpoint>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sgtl5000_rx_endpoint: endpoint@1 {
|
sgtl5000_rx_endpoint: endpoint@1 {
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
remote-endpoint = <&sai2b_endpoint>;
|
remote-endpoint = <&sai2b_endpoint>;
|
||||||
frame-master;
|
frame-master = <&sgtl5000_rx_endpoint>;
|
||||||
bitclock-master;
|
bitclock-master = <&sgtl5000_rx_endpoint>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -185,8 +185,8 @@ &i2c2 { /* X6 I2C2 */
|
|||||||
&i2c4 {
|
&i2c4 {
|
||||||
hdmi-transmitter@3d {
|
hdmi-transmitter@3d {
|
||||||
compatible = "adi,adv7513";
|
compatible = "adi,adv7513";
|
||||||
reg = <0x3d>, <0x2d>, <0x4d>, <0x5d>;
|
reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>;
|
||||||
reg-names = "main", "cec", "edid", "packet";
|
reg-names = "main", "edid", "cec", "packet";
|
||||||
clocks = <&cec_clock>;
|
clocks = <&cec_clock>;
|
||||||
clock-names = "cec";
|
clock-names = "cec";
|
||||||
|
|
||||||
@ -204,8 +204,6 @@ hdmi-transmitter@3d {
|
|||||||
adi,input-depth = <8>;
|
adi,input-depth = <8>;
|
||||||
adi,input-colorspace = "rgb";
|
adi,input-colorspace = "rgb";
|
||||||
adi,input-clock = "1x";
|
adi,input-clock = "1x";
|
||||||
adi,input-style = <1>;
|
|
||||||
adi,input-justification = "evenly";
|
|
||||||
|
|
||||||
ports {
|
ports {
|
||||||
#address-cells = <1>;
|
#address-cells = <1>;
|
||||||
|
|||||||
@ -212,15 +212,15 @@ cs42l51_port: port {
|
|||||||
cs42l51_tx_endpoint: endpoint@0 {
|
cs42l51_tx_endpoint: endpoint@0 {
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
remote-endpoint = <&sai2a_endpoint>;
|
remote-endpoint = <&sai2a_endpoint>;
|
||||||
frame-master;
|
frame-master = <&cs42l51_tx_endpoint>;
|
||||||
bitclock-master;
|
bitclock-master = <&cs42l51_tx_endpoint>;
|
||||||
};
|
};
|
||||||
|
|
||||||
cs42l51_rx_endpoint: endpoint@1 {
|
cs42l51_rx_endpoint: endpoint@1 {
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
remote-endpoint = <&sai2b_endpoint>;
|
remote-endpoint = <&sai2b_endpoint>;
|
||||||
frame-master;
|
frame-master = <&cs42l51_rx_endpoint>;
|
||||||
bitclock-master;
|
bitclock-master = <&cs42l51_rx_endpoint>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|||||||
@ -704,7 +704,6 @@ usb-phy@c5000000 {
|
|||||||
nvidia,xcvr-setup-use-fuses;
|
nvidia,xcvr-setup-use-fuses;
|
||||||
nvidia,xcvr-lsfslew = <2>;
|
nvidia,xcvr-lsfslew = <2>;
|
||||||
nvidia,xcvr-lsrslew = <2>;
|
nvidia,xcvr-lsrslew = <2>;
|
||||||
vbus-supply = <&vdd_vbus1>;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
usb@c5008000 {
|
usb@c5008000 {
|
||||||
@ -716,7 +715,7 @@ usb-phy@c5008000 {
|
|||||||
nvidia,xcvr-setup-use-fuses;
|
nvidia,xcvr-setup-use-fuses;
|
||||||
nvidia,xcvr-lsfslew = <2>;
|
nvidia,xcvr-lsfslew = <2>;
|
||||||
nvidia,xcvr-lsrslew = <2>;
|
nvidia,xcvr-lsrslew = <2>;
|
||||||
vbus-supply = <&vdd_vbus3>;
|
vbus-supply = <&vdd_5v0_sys>;
|
||||||
};
|
};
|
||||||
|
|
||||||
brcm_wifi_pwrseq: wifi-pwrseq {
|
brcm_wifi_pwrseq: wifi-pwrseq {
|
||||||
@ -967,28 +966,6 @@ vdd_pnl: regulator@3 {
|
|||||||
vin-supply = <&vdd_5v0_sys>;
|
vin-supply = <&vdd_5v0_sys>;
|
||||||
};
|
};
|
||||||
|
|
||||||
vdd_vbus1: regulator@4 {
|
|
||||||
compatible = "regulator-fixed";
|
|
||||||
regulator-name = "vdd_usb1_vbus";
|
|
||||||
regulator-min-microvolt = <5000000>;
|
|
||||||
regulator-max-microvolt = <5000000>;
|
|
||||||
regulator-always-on;
|
|
||||||
gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
|
|
||||||
enable-active-high;
|
|
||||||
vin-supply = <&vdd_5v0_sys>;
|
|
||||||
};
|
|
||||||
|
|
||||||
vdd_vbus3: regulator@5 {
|
|
||||||
compatible = "regulator-fixed";
|
|
||||||
regulator-name = "vdd_usb3_vbus";
|
|
||||||
regulator-min-microvolt = <5000000>;
|
|
||||||
regulator-max-microvolt = <5000000>;
|
|
||||||
regulator-always-on;
|
|
||||||
gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
|
|
||||||
enable-active-high;
|
|
||||||
vin-supply = <&vdd_5v0_sys>;
|
|
||||||
};
|
|
||||||
|
|
||||||
sound {
|
sound {
|
||||||
compatible = "nvidia,tegra-audio-wm8903-picasso",
|
compatible = "nvidia,tegra-audio-wm8903-picasso",
|
||||||
"nvidia,tegra-audio-wm8903";
|
"nvidia,tegra-audio-wm8903";
|
||||||
|
|||||||
@ -185,8 +185,9 @@ conf_ata {
|
|||||||
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
nvidia,pins = "ata", "atb", "atc", "atd", "ate",
|
||||||
"cdev1", "cdev2", "dap1", "dtb", "gma",
|
"cdev1", "cdev2", "dap1", "dtb", "gma",
|
||||||
"gmb", "gmc", "gmd", "gme", "gpu7",
|
"gmb", "gmc", "gmd", "gme", "gpu7",
|
||||||
"gpv", "i2cp", "pta", "rm", "slxa",
|
"gpv", "i2cp", "irrx", "irtx", "pta",
|
||||||
"slxk", "spia", "spib", "uac";
|
"rm", "slxa", "slxk", "spia", "spib",
|
||||||
|
"uac";
|
||||||
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
|
||||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||||
};
|
};
|
||||||
@ -211,7 +212,7 @@ conf_crtp {
|
|||||||
conf_ddc {
|
conf_ddc {
|
||||||
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
nvidia,pins = "ddc", "dta", "dtd", "kbca",
|
||||||
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
"kbcb", "kbcc", "kbcd", "kbce", "kbcf",
|
||||||
"sdc";
|
"sdc", "uad", "uca";
|
||||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||||
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
nvidia,tristate = <TEGRA_PIN_DISABLE>;
|
||||||
};
|
};
|
||||||
@ -221,10 +222,9 @@ conf_hdint {
|
|||||||
"lvp0", "owc", "sdb";
|
"lvp0", "owc", "sdb";
|
||||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||||
};
|
};
|
||||||
conf_irrx {
|
conf_sdd {
|
||||||
nvidia,pins = "irrx", "irtx", "sdd", "spic",
|
nvidia,pins = "sdd", "spic", "spie", "spih",
|
||||||
"spie", "spih", "uaa", "uab", "uad",
|
"uaa", "uab", "ucb";
|
||||||
"uca", "ucb";
|
|
||||||
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
nvidia,pull = <TEGRA_PIN_PULL_UP>;
|
||||||
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
nvidia,tristate = <TEGRA_PIN_ENABLE>;
|
||||||
};
|
};
|
||||||
|
|||||||
@ -32,14 +32,14 @@ hdmi_con_in: endpoint {
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
reg_vcc3v3: vcc3v3 {
|
reg_vcc3v3: regulator-vcc3v3 {
|
||||||
compatible = "regulator-fixed";
|
compatible = "regulator-fixed";
|
||||||
regulator-name = "vcc3v3";
|
regulator-name = "vcc3v3";
|
||||||
regulator-min-microvolt = <3300000>;
|
regulator-min-microvolt = <3300000>;
|
||||||
regulator-max-microvolt = <3300000>;
|
regulator-max-microvolt = <3300000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
reg_vdd_cpu_gpu: vdd-cpu-gpu {
|
reg_vdd_cpu_gpu: regulator-vdd-cpu-gpu {
|
||||||
compatible = "regulator-fixed";
|
compatible = "regulator-fixed";
|
||||||
regulator-name = "vdd-cpu-gpu";
|
regulator-name = "vdd-cpu-gpu";
|
||||||
regulator-min-microvolt = <1135000>;
|
regulator-min-microvolt = <1135000>;
|
||||||
|
|||||||
@ -83,15 +83,9 @@ rtc@51 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
eeprom@52 {
|
eeprom@52 {
|
||||||
compatible = "atmel,24c512";
|
compatible = "onnn,cat24c04", "atmel,24c04";
|
||||||
reg = <0x52>;
|
reg = <0x52>;
|
||||||
};
|
};
|
||||||
|
|
||||||
eeprom@53 {
|
|
||||||
compatible = "atmel,24c512";
|
|
||||||
reg = <0x53>;
|
|
||||||
};
|
|
||||||
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|||||||
@ -58,14 +58,9 @@ temp-sensor@4c {
|
|||||||
};
|
};
|
||||||
|
|
||||||
eeprom@52 {
|
eeprom@52 {
|
||||||
compatible = "atmel,24c512";
|
compatible = "onnn,cat24c05", "atmel,24c04";
|
||||||
reg = <0x52>;
|
reg = <0x52>;
|
||||||
};
|
};
|
||||||
|
|
||||||
eeprom@53 {
|
|
||||||
compatible = "atmel,24c512";
|
|
||||||
reg = <0x53>;
|
|
||||||
};
|
|
||||||
};
|
};
|
||||||
|
|
||||||
&i2c3 {
|
&i2c3 {
|
||||||
|
|||||||
@ -1215,13 +1215,13 @@ cpus {
|
|||||||
|
|
||||||
cpu@0 {
|
cpu@0 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "nvidia,denver";
|
compatible = "nvidia,tegra132-denver";
|
||||||
reg = <0>;
|
reg = <0>;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpu@1 {
|
cpu@1 {
|
||||||
device_type = "cpu";
|
device_type = "cpu";
|
||||||
compatible = "nvidia,denver";
|
compatible = "nvidia,tegra132-denver";
|
||||||
reg = <1>;
|
reg = <1>;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|||||||
@ -1976,7 +1976,7 @@ pcie@141a0000 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@14160000 {
|
pcie_ep@14160000 {
|
||||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
compatible = "nvidia,tegra194-pcie-ep";
|
||||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>;
|
||||||
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
|
||||||
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
<0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||||
@ -2008,7 +2008,7 @@ pcie_ep@14160000 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@14180000 {
|
pcie_ep@14180000 {
|
||||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
compatible = "nvidia,tegra194-pcie-ep";
|
||||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
|
||||||
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
|
||||||
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
<0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||||
@ -2040,7 +2040,7 @@ pcie_ep@14180000 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
pcie_ep@141a0000 {
|
pcie_ep@141a0000 {
|
||||||
compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
|
compatible = "nvidia,tegra194-pcie-ep";
|
||||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
|
||||||
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
|
||||||
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
<0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
|
||||||
|
|||||||
@ -151,7 +151,7 @@ reserved-memory {
|
|||||||
#size-cells = <2>;
|
#size-cells = <2>;
|
||||||
ranges;
|
ranges;
|
||||||
|
|
||||||
rpm_msg_ram: memory@0x60000 {
|
rpm_msg_ram: memory@60000 {
|
||||||
reg = <0x0 0x60000 0x0 0x6000>;
|
reg = <0x0 0x60000 0x0 0x6000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|||||||
@ -20,7 +20,7 @@ chosen {
|
|||||||
stdout-path = "serial0";
|
stdout-path = "serial0";
|
||||||
};
|
};
|
||||||
|
|
||||||
memory {
|
memory@40000000 {
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x0 0x40000000 0x0 0x20000000>;
|
reg = <0x0 0x40000000 0x0 0x20000000>;
|
||||||
};
|
};
|
||||||
|
|||||||
@ -567,10 +567,10 @@ frame@b128000 {
|
|||||||
|
|
||||||
pcie1: pci@10000000 {
|
pcie1: pci@10000000 {
|
||||||
compatible = "qcom,pcie-ipq8074";
|
compatible = "qcom,pcie-ipq8074";
|
||||||
reg = <0x10000000 0xf1d
|
reg = <0x10000000 0xf1d>,
|
||||||
0x10000f20 0xa8
|
<0x10000f20 0xa8>,
|
||||||
0x00088000 0x2000
|
<0x00088000 0x2000>,
|
||||||
0x10100000 0x1000>;
|
<0x10100000 0x1000>;
|
||||||
reg-names = "dbi", "elbi", "parf", "config";
|
reg-names = "dbi", "elbi", "parf", "config";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
linux,pci-domain = <1>;
|
linux,pci-domain = <1>;
|
||||||
@ -629,10 +629,10 @@ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
|
|||||||
|
|
||||||
pcie0: pci@20000000 {
|
pcie0: pci@20000000 {
|
||||||
compatible = "qcom,pcie-ipq8074";
|
compatible = "qcom,pcie-ipq8074";
|
||||||
reg = <0x20000000 0xf1d
|
reg = <0x20000000 0xf1d>,
|
||||||
0x20000f20 0xa8
|
<0x20000f20 0xa8>,
|
||||||
0x00080000 0x2000
|
<0x00080000 0x2000>,
|
||||||
0x20100000 0x1000>;
|
<0x20100000 0x1000>;
|
||||||
reg-names = "dbi", "elbi", "parf", "config";
|
reg-names = "dbi", "elbi", "parf", "config";
|
||||||
device_type = "pci";
|
device_type = "pci";
|
||||||
linux,pci-domain = <0>;
|
linux,pci-domain = <0>;
|
||||||
|
|||||||
@ -14,16 +14,18 @@ / {
|
|||||||
chosen { };
|
chosen { };
|
||||||
|
|
||||||
clocks {
|
clocks {
|
||||||
xo_board: xo_board {
|
xo_board: xo-board {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <19200000>;
|
clock-frequency = <19200000>;
|
||||||
|
clock-output-names = "xo_board";
|
||||||
};
|
};
|
||||||
|
|
||||||
sleep_clk: sleep_clk {
|
sleep_clk: sleep-clk {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32768>;
|
clock-frequency = <32768>;
|
||||||
|
clock-output-names = "sleep_clk";
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -17,14 +17,14 @@ / {
|
|||||||
chosen { };
|
chosen { };
|
||||||
|
|
||||||
clocks {
|
clocks {
|
||||||
xo_board: xo_board {
|
xo_board: xo-board {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <19200000>;
|
clock-frequency = <19200000>;
|
||||||
clock-output-names = "xo_board";
|
clock-output-names = "xo_board";
|
||||||
};
|
};
|
||||||
|
|
||||||
sleep_clk: sleep_clk {
|
sleep_clk: sleep-clk {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32764>;
|
clock-frequency = <32764>;
|
||||||
|
|||||||
@ -17,14 +17,14 @@ / {
|
|||||||
chosen { };
|
chosen { };
|
||||||
|
|
||||||
clocks {
|
clocks {
|
||||||
xo_board: xo_board {
|
xo_board: xo-board {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <19200000>;
|
clock-frequency = <19200000>;
|
||||||
clock-output-names = "xo_board";
|
clock-output-names = "xo_board";
|
||||||
};
|
};
|
||||||
|
|
||||||
sleep_clk: sleep_clk {
|
sleep_clk: sleep-clk {
|
||||||
compatible = "fixed-clock";
|
compatible = "fixed-clock";
|
||||||
#clock-cells = <0>;
|
#clock-cells = <0>;
|
||||||
clock-frequency = <32764>;
|
clock-frequency = <32764>;
|
||||||
@ -343,10 +343,19 @@ wlan_msa_mem: wlan-msa-mem@85700000 {
|
|||||||
};
|
};
|
||||||
|
|
||||||
qhee_code: qhee-code@85800000 {
|
qhee_code: qhee-code@85800000 {
|
||||||
reg = <0x0 0x85800000 0x0 0x3700000>;
|
reg = <0x0 0x85800000 0x0 0x600000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
rmtfs_mem: memory@85e00000 {
|
||||||
|
compatible = "qcom,rmtfs-mem";
|
||||||
|
reg = <0x0 0x85e00000 0x0 0x200000>;
|
||||||
|
no-map;
|
||||||
|
|
||||||
|
qcom,client-id = <1>;
|
||||||
|
qcom,vmid = <15>;
|
||||||
|
};
|
||||||
|
|
||||||
smem_region: smem-mem@86000000 {
|
smem_region: smem-mem@86000000 {
|
||||||
reg = <0 0x86000000 0 0x200000>;
|
reg = <0 0x86000000 0 0x200000>;
|
||||||
no-map;
|
no-map;
|
||||||
@ -357,58 +366,44 @@ tz_mem: memory@86200000 {
|
|||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
modem_fw_mem: modem-fw-region@8ac00000 {
|
mpss_region: mpss@8ac00000 {
|
||||||
reg = <0x0 0x8ac00000 0x0 0x7e00000>;
|
reg = <0x0 0x8ac00000 0x0 0x7e00000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
adsp_fw_mem: adsp-fw-region@92a00000 {
|
adsp_region: adsp@92a00000 {
|
||||||
reg = <0x0 0x92a00000 0x0 0x1e00000>;
|
reg = <0x0 0x92a00000 0x0 0x1e00000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
pil_mba_mem: pil-mba-region@94800000 {
|
mba_region: mba@94800000 {
|
||||||
reg = <0x0 0x94800000 0x0 0x200000>;
|
reg = <0x0 0x94800000 0x0 0x200000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
buffer_mem: buffer-region@94a00000 {
|
buffer_mem: tzbuffer@94a00000 {
|
||||||
reg = <0x0 0x94a00000 0x0 0x100000>;
|
reg = <0x0 0x94a00000 0x0 0x100000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
venus_fw_mem: venus-fw-region@9f800000 {
|
venus_region: venus@9f800000 {
|
||||||
reg = <0x0 0x9f800000 0x0 0x800000>;
|
reg = <0x0 0x9f800000 0x0 0x800000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
secure_region2: secure-region2@f7c00000 {
|
|
||||||
reg = <0x0 0xf7c00000 0x0 0x5c00000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
|
|
||||||
adsp_mem: adsp-region@f6000000 {
|
adsp_mem: adsp-region@f6000000 {
|
||||||
reg = <0x0 0xf6000000 0x0 0x800000>;
|
reg = <0x0 0xf6000000 0x0 0x800000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
qseecom_ta_mem: qseecom-ta-region@fec00000 {
|
|
||||||
reg = <0x0 0xfec00000 0x0 0x1000000>;
|
|
||||||
no-map;
|
|
||||||
};
|
|
||||||
|
|
||||||
qseecom_mem: qseecom-region@f6800000 {
|
qseecom_mem: qseecom-region@f6800000 {
|
||||||
reg = <0x0 0xf6800000 0x0 0x1400000>;
|
reg = <0x0 0xf6800000 0x0 0x1400000>;
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
|
|
||||||
secure_display_memory: secure-region@f5c00000 {
|
zap_shader_region: gpu@fed00000 {
|
||||||
reg = <0x0 0xf5c00000 0x0 0x5c00000>;
|
compatible = "shared-dma-pool";
|
||||||
no-map;
|
reg = <0x0 0xfed00000 0x0 0xa00000>;
|
||||||
};
|
|
||||||
|
|
||||||
cont_splash_mem: cont-splash-region@9d400000 {
|
|
||||||
reg = <0x0 0x9d400000 0x0 0x23ff000>;
|
|
||||||
no-map;
|
no-map;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
@ -527,14 +522,18 @@ tcsr_mutex_regs: syscon@1f40000 {
|
|||||||
reg = <0x01f40000 0x20000>;
|
reg = <0x01f40000 0x20000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
tlmm: pinctrl@3000000 {
|
tlmm: pinctrl@3100000 {
|
||||||
compatible = "qcom,sdm630-pinctrl";
|
compatible = "qcom,sdm630-pinctrl";
|
||||||
reg = <0x03000000 0xc00000>;
|
reg = <0x03100000 0x400000>,
|
||||||
|
<0x03500000 0x400000>,
|
||||||
|
<0x03900000 0x400000>;
|
||||||
|
reg-names = "south", "center", "north";
|
||||||
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||||
gpio-controller;
|
gpio-controller;
|
||||||
#gpio-cells = <0x2>;
|
gpio-ranges = <&tlmm 0 0 114>;
|
||||||
|
#gpio-cells = <2>;
|
||||||
interrupt-controller;
|
interrupt-controller;
|
||||||
#interrupt-cells = <0x2>;
|
#interrupt-cells = <2>;
|
||||||
|
|
||||||
blsp1_uart1_default: blsp1-uart1-default {
|
blsp1_uart1_default: blsp1-uart1-default {
|
||||||
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
pins = "gpio0", "gpio1", "gpio2", "gpio3";
|
||||||
@ -554,40 +553,48 @@ blsp1_uart2_default: blsp1-uart2-default {
|
|||||||
bias-disable;
|
bias-disable;
|
||||||
};
|
};
|
||||||
|
|
||||||
blsp2_uart1_tx_active: blsp2-uart1-tx-active {
|
blsp2_uart1_default: blsp2-uart1-active {
|
||||||
pins = "gpio16";
|
tx-rts {
|
||||||
drive-strength = <2>;
|
pins = "gpio16", "gpio19";
|
||||||
bias-disable;
|
function = "blsp_uart5";
|
||||||
|
drive-strength = <2>;
|
||||||
|
bias-disable;
|
||||||
|
};
|
||||||
|
|
||||||
|
rx {
|
||||||
|
/*
|
||||||
|
* Avoid garbage data while BT module
|
||||||
|
* is powered off or not driving signal
|
||||||
|
*/
|
||||||
|
pins = "gpio17";
|
||||||
|
function = "blsp_uart5";
|
||||||
|
drive-strength = <2>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
|
cts {
|
||||||
|
/* Match the pull of the BT module */
|
||||||
|
pins = "gpio18";
|
||||||
|
function = "blsp_uart5";
|
||||||
|
drive-strength = <2>;
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
blsp2_uart1_tx_sleep: blsp2-uart1-tx-sleep {
|
blsp2_uart1_sleep: blsp2-uart1-sleep {
|
||||||
pins = "gpio16";
|
tx {
|
||||||
drive-strength = <2>;
|
pins = "gpio16";
|
||||||
bias-pull-up;
|
function = "gpio";
|
||||||
};
|
drive-strength = <2>;
|
||||||
|
bias-pull-up;
|
||||||
|
};
|
||||||
|
|
||||||
blsp2_uart1_rxcts_active: blsp2-uart1-rxcts-active {
|
rx-cts-rts {
|
||||||
pins = "gpio17", "gpio18";
|
pins = "gpio17", "gpio18", "gpio19";
|
||||||
drive-strength = <2>;
|
function = "gpio";
|
||||||
bias-disable;
|
drive-strength = <2>;
|
||||||
};
|
bias-no-pull;
|
||||||
|
};
|
||||||
blsp2_uart1_rxcts_sleep: blsp2-uart1-rxcts-sleep {
|
|
||||||
pins = "gpio17", "gpio18";
|
|
||||||
drive-strength = <2>;
|
|
||||||
bias-no-pull;
|
|
||||||
};
|
|
||||||
|
|
||||||
blsp2_uart1_rfr_active: blsp2-uart1-rfr-active {
|
|
||||||
pins = "gpio19";
|
|
||||||
drive-strength = <2>;
|
|
||||||
bias-disable;
|
|
||||||
};
|
|
||||||
|
|
||||||
blsp2_uart1_rfr_sleep: blsp2-uart1-rfr-sleep {
|
|
||||||
pins = "gpio19";
|
|
||||||
drive-strength = <2>;
|
|
||||||
bias-no-pull;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
i2c1_default: i2c1-default {
|
i2c1_default: i2c1-default {
|
||||||
@ -686,50 +693,106 @@ i2c8_sleep: i2c8-sleep {
|
|||||||
bias-pull-up;
|
bias-pull-up;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_clk_on: sdc1-clk-on {
|
sdc1_state_on: sdc1-on {
|
||||||
pins = "sdc1_clk";
|
clk {
|
||||||
bias-disable;
|
pins = "sdc1_clk";
|
||||||
drive-strength = <16>;
|
bias-disable;
|
||||||
|
drive-strength = <16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cmd {
|
||||||
|
pins = "sdc1_cmd";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
data {
|
||||||
|
pins = "sdc1_data";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rclk {
|
||||||
|
pins = "sdc1_rclk";
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_clk_off: sdc1-clk-off {
|
sdc1_state_off: sdc1-off {
|
||||||
pins = "sdc1_clk";
|
clk {
|
||||||
bias-disable;
|
pins = "sdc1_clk";
|
||||||
drive-strength = <2>;
|
bias-disable;
|
||||||
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cmd {
|
||||||
|
pins = "sdc1_cmd";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
data {
|
||||||
|
pins = "sdc1_data";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
|
rclk {
|
||||||
|
pins = "sdc1_rclk";
|
||||||
|
bias-pull-down;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_cmd_on: sdc1-cmd-on {
|
sdc2_state_on: sdc2-on {
|
||||||
pins = "sdc1_cmd";
|
clk {
|
||||||
bias-pull-up;
|
pins = "sdc2_clk";
|
||||||
drive-strength = <10>;
|
bias-disable;
|
||||||
|
drive-strength = <16>;
|
||||||
|
};
|
||||||
|
|
||||||
|
cmd {
|
||||||
|
pins = "sdc2_cmd";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
data {
|
||||||
|
pins = "sdc2_data";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <10>;
|
||||||
|
};
|
||||||
|
|
||||||
|
sd-cd {
|
||||||
|
pins = "gpio54";
|
||||||
|
bias-pull-up;
|
||||||
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_cmd_off: sdc1-cmd-off {
|
sdc2_state_off: sdc2-off {
|
||||||
pins = "sdc1_cmd";
|
clk {
|
||||||
bias-pull-up;
|
pins = "sdc2_clk";
|
||||||
drive-strength = <2>;
|
bias-disable;
|
||||||
};
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
|
|
||||||
sdc1_data_on: sdc1-data-on {
|
cmd {
|
||||||
pins = "sdc1_data";
|
pins = "sdc2_cmd";
|
||||||
bias-pull-up;
|
bias-pull-up;
|
||||||
drive-strength = <8>;
|
drive-strength = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_data_off: sdc1-data-off {
|
data {
|
||||||
pins = "sdc1_data";
|
pins = "sdc2_data";
|
||||||
bias-pull-up;
|
bias-pull-up;
|
||||||
drive-strength = <2>;
|
drive-strength = <2>;
|
||||||
};
|
};
|
||||||
|
|
||||||
sdc1_rclk_on: sdc1-rclk-on {
|
sd-cd {
|
||||||
pins = "sdc1_rclk";
|
pins = "gpio54";
|
||||||
bias-pull-down;
|
bias-disable;
|
||||||
};
|
drive-strength = <2>;
|
||||||
|
};
|
||||||
sdc1_rclk_off: sdc1-rclk-off {
|
|
||||||
pins = "sdc1_rclk";
|
|
||||||
bias-pull-down;
|
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -821,8 +884,8 @@ sdhc_1: sdhci@c0c4000 {
|
|||||||
clock-names = "core", "iface", "xo";
|
clock-names = "core", "iface", "xo";
|
||||||
|
|
||||||
pinctrl-names = "default", "sleep";
|
pinctrl-names = "default", "sleep";
|
||||||
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
|
pinctrl-0 = <&sdc1_state_on>;
|
||||||
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
|
pinctrl-1 = <&sdc1_state_off>;
|
||||||
|
|
||||||
bus-width = <8>;
|
bus-width = <8>;
|
||||||
non-removable;
|
non-removable;
|
||||||
@ -967,10 +1030,8 @@ blsp2_uart1: serial@c1af000 {
|
|||||||
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
|
dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
|
||||||
dma-names = "tx", "rx";
|
dma-names = "tx", "rx";
|
||||||
pinctrl-names = "default", "sleep";
|
pinctrl-names = "default", "sleep";
|
||||||
pinctrl-0 = <&blsp2_uart1_tx_active &blsp2_uart1_rxcts_active
|
pinctrl-0 = <&blsp2_uart1_default>;
|
||||||
&blsp2_uart1_rfr_active>;
|
pinctrl-1 = <&blsp2_uart1_sleep>;
|
||||||
pinctrl-1 = <&blsp2_uart1_tx_sleep &blsp2_uart1_rxcts_sleep
|
|
||||||
&blsp2_uart1_rfr_sleep>;
|
|
||||||
status = "disabled";
|
status = "disabled";
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -2346,7 +2346,7 @@ apps_bcm_voter: bcm_voter {
|
|||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
epss_l3: interconnect@18591000 {
|
epss_l3: interconnect@18590000 {
|
||||||
compatible = "qcom,sm8250-epss-l3";
|
compatible = "qcom,sm8250-epss-l3";
|
||||||
reg = <0 0x18590000 0 0x1000>;
|
reg = <0 0x18590000 0 0x1000>;
|
||||||
|
|
||||||
|
|||||||
@ -65,8 +65,8 @@
|
|||||||
#define EARLY_KASLR (0)
|
#define EARLY_KASLR (0)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define EARLY_ENTRIES(vstart, vend, shift) (((vend) >> (shift)) \
|
#define EARLY_ENTRIES(vstart, vend, shift) \
|
||||||
- ((vstart) >> (shift)) + 1 + EARLY_KASLR)
|
((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1 + EARLY_KASLR)
|
||||||
|
|
||||||
#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
|
#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
|
||||||
|
|
||||||
|
|||||||
@ -27,11 +27,32 @@ typedef struct {
|
|||||||
} mm_context_t;
|
} mm_context_t;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* This macro is only used by the TLBI and low-level switch_mm() code,
|
* We use atomic64_read() here because the ASID for an 'mm_struct' can
|
||||||
* neither of which can race with an ASID change. We therefore don't
|
* be reallocated when scheduling one of its threads following a
|
||||||
* need to reload the counter using atomic64_read().
|
* rollover event (see new_context() and flush_context()). In this case,
|
||||||
|
* a concurrent TLBI (e.g. via try_to_unmap_one() and ptep_clear_flush())
|
||||||
|
* may use a stale ASID. This is fine in principle as the new ASID is
|
||||||
|
* guaranteed to be clean in the TLB, but the TLBI routines have to take
|
||||||
|
* care to handle the following race:
|
||||||
|
*
|
||||||
|
* CPU 0 CPU 1 CPU 2
|
||||||
|
*
|
||||||
|
* // ptep_clear_flush(mm)
|
||||||
|
* xchg_relaxed(pte, 0)
|
||||||
|
* DSB ISHST
|
||||||
|
* old = ASID(mm)
|
||||||
|
* | <rollover>
|
||||||
|
* | new = new_context(mm)
|
||||||
|
* \-----------------> atomic_set(mm->context.id, new)
|
||||||
|
* cpu_switch_mm(mm)
|
||||||
|
* // Hardware walk of pte using new ASID
|
||||||
|
* TLBI(old)
|
||||||
|
*
|
||||||
|
* In this scenario, the barrier on CPU 0 and the dependency on CPU 1
|
||||||
|
* ensure that the page-table walker on CPU 1 *must* see the invalid PTE
|
||||||
|
* written by CPU 0.
|
||||||
*/
|
*/
|
||||||
#define ASID(mm) ((mm)->context.id.counter & 0xffff)
|
#define ASID(mm) (atomic64_read(&(mm)->context.id) & 0xffff)
|
||||||
|
|
||||||
static inline bool arm64_kernel_unmapped_at_el0(void)
|
static inline bool arm64_kernel_unmapped_at_el0(void)
|
||||||
{
|
{
|
||||||
|
|||||||
@ -245,9 +245,10 @@ static inline void flush_tlb_all(void)
|
|||||||
|
|
||||||
static inline void flush_tlb_mm(struct mm_struct *mm)
|
static inline void flush_tlb_mm(struct mm_struct *mm)
|
||||||
{
|
{
|
||||||
unsigned long asid = __TLBI_VADDR(0, ASID(mm));
|
unsigned long asid;
|
||||||
|
|
||||||
dsb(ishst);
|
dsb(ishst);
|
||||||
|
asid = __TLBI_VADDR(0, ASID(mm));
|
||||||
__tlbi(aside1is, asid);
|
__tlbi(aside1is, asid);
|
||||||
__tlbi_user(aside1is, asid);
|
__tlbi_user(aside1is, asid);
|
||||||
dsb(ish);
|
dsb(ish);
|
||||||
@ -256,9 +257,10 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
|
|||||||
static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
|
static inline void flush_tlb_page_nosync(struct vm_area_struct *vma,
|
||||||
unsigned long uaddr)
|
unsigned long uaddr)
|
||||||
{
|
{
|
||||||
unsigned long addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
|
unsigned long addr;
|
||||||
|
|
||||||
dsb(ishst);
|
dsb(ishst);
|
||||||
|
addr = __TLBI_VADDR(uaddr, ASID(vma->vm_mm));
|
||||||
__tlbi(vale1is, addr);
|
__tlbi(vale1is, addr);
|
||||||
__tlbi_user(vale1is, addr);
|
__tlbi_user(vale1is, addr);
|
||||||
}
|
}
|
||||||
@ -283,9 +285,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
|
|||||||
{
|
{
|
||||||
int num = 0;
|
int num = 0;
|
||||||
int scale = 0;
|
int scale = 0;
|
||||||
unsigned long asid = ASID(vma->vm_mm);
|
unsigned long asid, addr, pages;
|
||||||
unsigned long addr;
|
|
||||||
unsigned long pages;
|
|
||||||
|
|
||||||
start = round_down(start, stride);
|
start = round_down(start, stride);
|
||||||
end = round_up(end, stride);
|
end = round_up(end, stride);
|
||||||
@ -305,6 +305,7 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma,
|
|||||||
}
|
}
|
||||||
|
|
||||||
dsb(ishst);
|
dsb(ishst);
|
||||||
|
asid = ASID(vma->vm_mm);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* When the CPU does not support TLB range operations, flush the TLB
|
* When the CPU does not support TLB range operations, flush the TLB
|
||||||
|
|||||||
@ -191,7 +191,7 @@ SYM_CODE_END(preserve_boot_args)
|
|||||||
* to be composed of multiple pages. (This effectively scales the end index).
|
* to be composed of multiple pages. (This effectively scales the end index).
|
||||||
*
|
*
|
||||||
* vstart: virtual address of start of range
|
* vstart: virtual address of start of range
|
||||||
* vend: virtual address of end of range
|
* vend: virtual address of end of range - we map [vstart, vend]
|
||||||
* shift: shift used to transform virtual address into index
|
* shift: shift used to transform virtual address into index
|
||||||
* ptrs: number of entries in page table
|
* ptrs: number of entries in page table
|
||||||
* istart: index in table corresponding to vstart
|
* istart: index in table corresponding to vstart
|
||||||
@ -228,17 +228,18 @@ SYM_CODE_END(preserve_boot_args)
|
|||||||
*
|
*
|
||||||
* tbl: location of page table
|
* tbl: location of page table
|
||||||
* rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
|
* rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
|
||||||
* vstart: start address to map
|
* vstart: virtual address of start of range
|
||||||
* vend: end address to map - we map [vstart, vend]
|
* vend: virtual address of end of range - we map [vstart, vend - 1]
|
||||||
* flags: flags to use to map last level entries
|
* flags: flags to use to map last level entries
|
||||||
* phys: physical address corresponding to vstart - physical memory is contiguous
|
* phys: physical address corresponding to vstart - physical memory is contiguous
|
||||||
* pgds: the number of pgd entries
|
* pgds: the number of pgd entries
|
||||||
*
|
*
|
||||||
* Temporaries: istart, iend, tmp, count, sv - these need to be different registers
|
* Temporaries: istart, iend, tmp, count, sv - these need to be different registers
|
||||||
* Preserves: vstart, vend, flags
|
* Preserves: vstart, flags
|
||||||
* Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
|
* Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv
|
||||||
*/
|
*/
|
||||||
.macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
|
.macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
|
||||||
|
sub \vend, \vend, #1
|
||||||
add \rtbl, \tbl, #PAGE_SIZE
|
add \rtbl, \tbl, #PAGE_SIZE
|
||||||
mov \sv, \rtbl
|
mov \sv, \rtbl
|
||||||
mov \count, #0
|
mov \count, #0
|
||||||
|
|||||||
@ -63,7 +63,7 @@ source "drivers/zorro/Kconfig"
|
|||||||
|
|
||||||
endif
|
endif
|
||||||
|
|
||||||
if !MMU
|
if COLDFIRE
|
||||||
|
|
||||||
config ISA_DMA_API
|
config ISA_DMA_API
|
||||||
def_bool !M5272
|
def_bool !M5272
|
||||||
|
|||||||
@ -22,7 +22,7 @@
|
|||||||
#define ROCIT_CONFIG_GEN1_MEMMAP_SHIFT 8
|
#define ROCIT_CONFIG_GEN1_MEMMAP_SHIFT 8
|
||||||
#define ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
|
#define ROCIT_CONFIG_GEN1_MEMMAP_MASK (0xf << 8)
|
||||||
|
|
||||||
static unsigned char fdt_buf[16 << 10] __initdata;
|
static unsigned char fdt_buf[16 << 10] __initdata __aligned(8);
|
||||||
|
|
||||||
/* determined physical memory size, not overridden by command line args */
|
/* determined physical memory size, not overridden by command line args */
|
||||||
extern unsigned long physical_memsize;
|
extern unsigned long physical_memsize;
|
||||||
|
|||||||
@ -547,6 +547,7 @@ EXCEPTION_ENTRY(_external_irq_handler)
|
|||||||
l.bnf 1f // ext irq enabled, all ok.
|
l.bnf 1f // ext irq enabled, all ok.
|
||||||
l.nop
|
l.nop
|
||||||
|
|
||||||
|
#ifdef CONFIG_PRINTK
|
||||||
l.addi r1,r1,-0x8
|
l.addi r1,r1,-0x8
|
||||||
l.movhi r3,hi(42f)
|
l.movhi r3,hi(42f)
|
||||||
l.ori r3,r3,lo(42f)
|
l.ori r3,r3,lo(42f)
|
||||||
@ -560,6 +561,7 @@ EXCEPTION_ENTRY(_external_irq_handler)
|
|||||||
.string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
|
.string "\n\rESR interrupt bug: in _external_irq_handler (ESR %x)\n\r"
|
||||||
.align 4
|
.align 4
|
||||||
.previous
|
.previous
|
||||||
|
#endif
|
||||||
|
|
||||||
l.ori r4,r4,SPR_SR_IEE // fix the bug
|
l.ori r4,r4,SPR_SR_IEE // fix the bug
|
||||||
// l.sw PT_SR(r1),r4
|
// l.sw PT_SR(r1),r4
|
||||||
|
|||||||
@ -237,6 +237,12 @@ setup_rt_frame(struct ksignal *ksig, sigset_t *set, struct pt_regs *regs,
|
|||||||
#endif
|
#endif
|
||||||
|
|
||||||
usp = (regs->gr[30] & ~(0x01UL));
|
usp = (regs->gr[30] & ~(0x01UL));
|
||||||
|
#ifdef CONFIG_64BIT
|
||||||
|
if (is_compat_task()) {
|
||||||
|
/* The gcc alloca implementation leaves garbage in the upper 32 bits of sp */
|
||||||
|
usp = (compat_uint_t)usp;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
/*FIXME: frame_size parameter is unused, remove it. */
|
/*FIXME: frame_size parameter is unused, remove it. */
|
||||||
frame = get_sigframe(&ksig->ka, usp, sizeof(*frame));
|
frame = get_sigframe(&ksig->ka, usp, sizeof(*frame));
|
||||||
|
|
||||||
|
|||||||
@ -34,6 +34,7 @@ CONFIG_MTD_CFI_GEOMETRY=y
|
|||||||
# CONFIG_MTD_CFI_I2 is not set
|
# CONFIG_MTD_CFI_I2 is not set
|
||||||
CONFIG_MTD_CFI_I4=y
|
CONFIG_MTD_CFI_I4=y
|
||||||
CONFIG_MTD_CFI_AMDSTD=y
|
CONFIG_MTD_CFI_AMDSTD=y
|
||||||
|
CONFIG_MTD_PHYSMAP=y
|
||||||
CONFIG_MTD_PHYSMAP_OF=y
|
CONFIG_MTD_PHYSMAP_OF=y
|
||||||
# CONFIG_BLK_DEV is not set
|
# CONFIG_BLK_DEV is not set
|
||||||
CONFIG_NETDEVICES=y
|
CONFIG_NETDEVICES=y
|
||||||
|
|||||||
@ -34,6 +34,13 @@ static inline void ppc_set_pmu_inuse(int inuse)
|
|||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
|
||||||
|
static inline int ppc_get_pmu_inuse(void)
|
||||||
|
{
|
||||||
|
return get_paca()->pmcregs_in_use;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
extern void power4_enable_pmcs(void);
|
extern void power4_enable_pmcs(void);
|
||||||
|
|
||||||
#else /* CONFIG_PPC64 */
|
#else /* CONFIG_PPC64 */
|
||||||
|
|||||||
@ -1385,6 +1385,7 @@ static void add_cpu_to_masks(int cpu)
|
|||||||
* add it to it's own thread sibling mask.
|
* add it to it's own thread sibling mask.
|
||||||
*/
|
*/
|
||||||
cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
|
cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
|
||||||
|
cpumask_set_cpu(cpu, cpu_core_mask(cpu));
|
||||||
|
|
||||||
for (i = first_thread; i < first_thread + threads_per_core; i++)
|
for (i = first_thread; i < first_thread + threads_per_core; i++)
|
||||||
if (cpu_online(i))
|
if (cpu_online(i))
|
||||||
@ -1399,11 +1400,6 @@ static void add_cpu_to_masks(int cpu)
|
|||||||
if (has_coregroup_support())
|
if (has_coregroup_support())
|
||||||
update_coregroup_mask(cpu, &mask);
|
update_coregroup_mask(cpu, &mask);
|
||||||
|
|
||||||
if (chip_id == -1 || !ret) {
|
|
||||||
cpumask_copy(per_cpu(cpu_core_map, cpu), cpu_cpu_mask(cpu));
|
|
||||||
goto out;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (shared_caches)
|
if (shared_caches)
|
||||||
submask_fn = cpu_l2_cache_mask;
|
submask_fn = cpu_l2_cache_mask;
|
||||||
|
|
||||||
@ -1413,6 +1409,10 @@ static void add_cpu_to_masks(int cpu)
|
|||||||
/* Skip all CPUs already part of current CPU core mask */
|
/* Skip all CPUs already part of current CPU core mask */
|
||||||
cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
|
cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
|
||||||
|
|
||||||
|
/* If chip_id is -1; limit the cpu_core_mask to within DIE*/
|
||||||
|
if (chip_id == -1)
|
||||||
|
cpumask_and(mask, mask, cpu_cpu_mask(cpu));
|
||||||
|
|
||||||
for_each_cpu(i, mask) {
|
for_each_cpu(i, mask) {
|
||||||
if (chip_id == cpu_to_chip_id(i)) {
|
if (chip_id == cpu_to_chip_id(i)) {
|
||||||
or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
|
or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
|
||||||
@ -1422,7 +1422,6 @@ static void add_cpu_to_masks(int cpu)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
out:
|
|
||||||
free_cpumask_var(mask);
|
free_cpumask_var(mask);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -8,6 +8,7 @@
|
|||||||
* Copyright 2018 Nick Piggin, Michael Ellerman, IBM Corp.
|
* Copyright 2018 Nick Piggin, Michael Ellerman, IBM Corp.
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
#include <linux/delay.h>
|
||||||
#include <linux/export.h>
|
#include <linux/export.h>
|
||||||
#include <linux/kallsyms.h>
|
#include <linux/kallsyms.h>
|
||||||
#include <linux/module.h>
|
#include <linux/module.h>
|
||||||
|
|||||||
@ -64,10 +64,12 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid,
|
|||||||
}
|
}
|
||||||
isync();
|
isync();
|
||||||
|
|
||||||
|
pagefault_disable();
|
||||||
if (is_load)
|
if (is_load)
|
||||||
ret = copy_from_user_nofault(to, (const void __user *)from, n);
|
ret = __copy_from_user_inatomic(to, (const void __user *)from, n);
|
||||||
else
|
else
|
||||||
ret = copy_to_user_nofault((void __user *)to, from, n);
|
ret = __copy_to_user_inatomic((void __user *)to, from, n);
|
||||||
|
pagefault_enable();
|
||||||
|
|
||||||
/* switch the pid first to avoid running host with unallocated pid */
|
/* switch the pid first to avoid running host with unallocated pid */
|
||||||
if (quadrant == 1 && pid != old_pid)
|
if (quadrant == 1 && pid != old_pid)
|
||||||
|
|||||||
@ -173,10 +173,13 @@ static void kvmppc_rm_tce_put(struct kvmppc_spapr_tce_table *stt,
|
|||||||
idx -= stt->offset;
|
idx -= stt->offset;
|
||||||
page = stt->pages[idx / TCES_PER_PAGE];
|
page = stt->pages[idx / TCES_PER_PAGE];
|
||||||
/*
|
/*
|
||||||
* page must not be NULL in real mode,
|
* kvmppc_rm_ioba_validate() allows pages not be allocated if TCE is
|
||||||
* kvmppc_rm_ioba_validate() must have taken care of this.
|
* being cleared, otherwise it returns H_TOO_HARD and we skip this.
|
||||||
*/
|
*/
|
||||||
WARN_ON_ONCE_RM(!page);
|
if (!page) {
|
||||||
|
WARN_ON_ONCE_RM(tce != 0);
|
||||||
|
return;
|
||||||
|
}
|
||||||
tbl = kvmppc_page_address(page);
|
tbl = kvmppc_page_address(page);
|
||||||
|
|
||||||
tbl[idx % TCES_PER_PAGE] = tce;
|
tbl[idx % TCES_PER_PAGE] = tce;
|
||||||
|
|||||||
@ -58,6 +58,7 @@
|
|||||||
#include <asm/kvm_book3s.h>
|
#include <asm/kvm_book3s.h>
|
||||||
#include <asm/mmu_context.h>
|
#include <asm/mmu_context.h>
|
||||||
#include <asm/lppaca.h>
|
#include <asm/lppaca.h>
|
||||||
|
#include <asm/pmc.h>
|
||||||
#include <asm/processor.h>
|
#include <asm/processor.h>
|
||||||
#include <asm/cputhreads.h>
|
#include <asm/cputhreads.h>
|
||||||
#include <asm/page.h>
|
#include <asm/page.h>
|
||||||
@ -3619,6 +3620,18 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
|
|||||||
cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
|
cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))
|
||||||
kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
|
kvmppc_restore_tm_hv(vcpu, vcpu->arch.shregs.msr, true);
|
||||||
|
|
||||||
|
#ifdef CONFIG_PPC_PSERIES
|
||||||
|
if (kvmhv_on_pseries()) {
|
||||||
|
barrier();
|
||||||
|
if (vcpu->arch.vpa.pinned_addr) {
|
||||||
|
struct lppaca *lp = vcpu->arch.vpa.pinned_addr;
|
||||||
|
get_lppaca()->pmcregs_in_use = lp->pmcregs_in_use;
|
||||||
|
} else {
|
||||||
|
get_lppaca()->pmcregs_in_use = 1;
|
||||||
|
}
|
||||||
|
barrier();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
kvmhv_load_guest_pmu(vcpu);
|
kvmhv_load_guest_pmu(vcpu);
|
||||||
|
|
||||||
msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
|
msr_check_and_set(MSR_FP | MSR_VEC | MSR_VSX);
|
||||||
@ -3756,6 +3769,13 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,
|
|||||||
save_pmu |= nesting_enabled(vcpu->kvm);
|
save_pmu |= nesting_enabled(vcpu->kvm);
|
||||||
|
|
||||||
kvmhv_save_guest_pmu(vcpu, save_pmu);
|
kvmhv_save_guest_pmu(vcpu, save_pmu);
|
||||||
|
#ifdef CONFIG_PPC_PSERIES
|
||||||
|
if (kvmhv_on_pseries()) {
|
||||||
|
barrier();
|
||||||
|
get_lppaca()->pmcregs_in_use = ppc_get_pmu_inuse();
|
||||||
|
barrier();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
vc->entry_exit_map = 0x101;
|
vc->entry_exit_map = 0x101;
|
||||||
vc->in_guest = 0;
|
vc->in_guest = 0;
|
||||||
|
|||||||
@ -893,7 +893,7 @@ static void __init setup_node_data(int nid, u64 start_pfn, u64 end_pfn)
|
|||||||
static void __init find_possible_nodes(void)
|
static void __init find_possible_nodes(void)
|
||||||
{
|
{
|
||||||
struct device_node *rtas;
|
struct device_node *rtas;
|
||||||
const __be32 *domains;
|
const __be32 *domains = NULL;
|
||||||
int prop_length, max_nodes;
|
int prop_length, max_nodes;
|
||||||
u32 i;
|
u32 i;
|
||||||
|
|
||||||
@ -909,9 +909,14 @@ static void __init find_possible_nodes(void)
|
|||||||
* it doesn't exist, then fallback on ibm,max-associativity-domains.
|
* it doesn't exist, then fallback on ibm,max-associativity-domains.
|
||||||
* Current denotes what the platform can support compared to max
|
* Current denotes what the platform can support compared to max
|
||||||
* which denotes what the Hypervisor can support.
|
* which denotes what the Hypervisor can support.
|
||||||
|
*
|
||||||
|
* If the LPAR is migratable, new nodes might be activated after a LPM,
|
||||||
|
* so we should consider the max number in that case.
|
||||||
*/
|
*/
|
||||||
domains = of_get_property(rtas, "ibm,current-associativity-domains",
|
if (!of_get_property(of_root, "ibm,migratable-partition", NULL))
|
||||||
&prop_length);
|
domains = of_get_property(rtas,
|
||||||
|
"ibm,current-associativity-domains",
|
||||||
|
&prop_length);
|
||||||
if (!domains) {
|
if (!domains) {
|
||||||
domains = of_get_property(rtas, "ibm,max-associativity-domains",
|
domains = of_get_property(rtas, "ibm,max-associativity-domains",
|
||||||
&prop_length);
|
&prop_length);
|
||||||
@ -920,6 +925,8 @@ static void __init find_possible_nodes(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
max_nodes = of_read_number(&domains[min_common_depth], 1);
|
max_nodes = of_read_number(&domains[min_common_depth], 1);
|
||||||
|
pr_info("Partition configured for %d NUMA nodes.\n", max_nodes);
|
||||||
|
|
||||||
for (i = 0; i < max_nodes; i++) {
|
for (i = 0; i < max_nodes; i++) {
|
||||||
if (!node_possible(i))
|
if (!node_possible(i))
|
||||||
node_set(i, node_possible_map);
|
node_set(i, node_possible_map);
|
||||||
|
|||||||
@ -175,7 +175,7 @@ static unsigned long single_gpci_request(u32 req, u32 starting_index,
|
|||||||
*/
|
*/
|
||||||
count = 0;
|
count = 0;
|
||||||
for (i = offset; i < offset + length; i++)
|
for (i = offset; i < offset + length; i++)
|
||||||
count |= arg->bytes[i] << (i - offset);
|
count |= (u64)(arg->bytes[i]) << ((length - 1 - (i - offset)) * 8);
|
||||||
|
|
||||||
*value = count;
|
*value = count;
|
||||||
out:
|
out:
|
||||||
|
|||||||
@ -38,6 +38,7 @@
|
|||||||
#define MACHINE_FLAG_NX BIT(15)
|
#define MACHINE_FLAG_NX BIT(15)
|
||||||
#define MACHINE_FLAG_GS BIT(16)
|
#define MACHINE_FLAG_GS BIT(16)
|
||||||
#define MACHINE_FLAG_SCC BIT(17)
|
#define MACHINE_FLAG_SCC BIT(17)
|
||||||
|
#define MACHINE_FLAG_PCI_MIO BIT(18)
|
||||||
|
|
||||||
#define LPP_MAGIC BIT(31)
|
#define LPP_MAGIC BIT(31)
|
||||||
#define LPP_PID_MASK _AC(0xffffffff, UL)
|
#define LPP_PID_MASK _AC(0xffffffff, UL)
|
||||||
@ -113,6 +114,7 @@ extern unsigned long mio_wb_bit_mask;
|
|||||||
#define MACHINE_HAS_NX (S390_lowcore.machine_flags & MACHINE_FLAG_NX)
|
#define MACHINE_HAS_NX (S390_lowcore.machine_flags & MACHINE_FLAG_NX)
|
||||||
#define MACHINE_HAS_GS (S390_lowcore.machine_flags & MACHINE_FLAG_GS)
|
#define MACHINE_HAS_GS (S390_lowcore.machine_flags & MACHINE_FLAG_GS)
|
||||||
#define MACHINE_HAS_SCC (S390_lowcore.machine_flags & MACHINE_FLAG_SCC)
|
#define MACHINE_HAS_SCC (S390_lowcore.machine_flags & MACHINE_FLAG_SCC)
|
||||||
|
#define MACHINE_HAS_PCI_MIO (S390_lowcore.machine_flags & MACHINE_FLAG_PCI_MIO)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Console mode. Override with conmode=
|
* Console mode. Override with conmode=
|
||||||
|
|||||||
@ -238,6 +238,10 @@ static __init void detect_machine_facilities(void)
|
|||||||
clock_comparator_max = -1ULL >> 1;
|
clock_comparator_max = -1ULL >> 1;
|
||||||
__ctl_set_bit(0, 53);
|
__ctl_set_bit(0, 53);
|
||||||
}
|
}
|
||||||
|
if (IS_ENABLED(CONFIG_PCI) && test_facility(153)) {
|
||||||
|
S390_lowcore.machine_flags |= MACHINE_FLAG_PCI_MIO;
|
||||||
|
/* the control bit is set during PCI initialization */
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void save_vector_registers(void)
|
static inline void save_vector_registers(void)
|
||||||
|
|||||||
@ -36,7 +36,7 @@ static void jump_label_bug(struct jump_entry *entry, struct insn *expected,
|
|||||||
unsigned char *ipe = (unsigned char *)expected;
|
unsigned char *ipe = (unsigned char *)expected;
|
||||||
unsigned char *ipn = (unsigned char *)new;
|
unsigned char *ipn = (unsigned char *)new;
|
||||||
|
|
||||||
pr_emerg("Jump label code mismatch at %pS [%p]\n", ipc, ipc);
|
pr_emerg("Jump label code mismatch at %pS [%px]\n", ipc, ipc);
|
||||||
pr_emerg("Found: %6ph\n", ipc);
|
pr_emerg("Found: %6ph\n", ipc);
|
||||||
pr_emerg("Expected: %6ph\n", ipe);
|
pr_emerg("Expected: %6ph\n", ipe);
|
||||||
pr_emerg("New: %6ph\n", ipn);
|
pr_emerg("New: %6ph\n", ipn);
|
||||||
|
|||||||
@ -180,9 +180,9 @@ static void pv_init(void)
|
|||||||
return;
|
return;
|
||||||
|
|
||||||
/* make sure bounce buffers are shared */
|
/* make sure bounce buffers are shared */
|
||||||
|
swiotlb_force = SWIOTLB_FORCE;
|
||||||
swiotlb_init(1);
|
swiotlb_init(1);
|
||||||
swiotlb_update_mem_attributes();
|
swiotlb_update_mem_attributes();
|
||||||
swiotlb_force = SWIOTLB_FORCE;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void __init mem_init(void)
|
void __init mem_init(void)
|
||||||
|
|||||||
@ -866,7 +866,6 @@ static void zpci_mem_exit(void)
|
|||||||
}
|
}
|
||||||
|
|
||||||
static unsigned int s390_pci_probe __initdata = 1;
|
static unsigned int s390_pci_probe __initdata = 1;
|
||||||
static unsigned int s390_pci_no_mio __initdata;
|
|
||||||
unsigned int s390_pci_force_floating __initdata;
|
unsigned int s390_pci_force_floating __initdata;
|
||||||
static unsigned int s390_pci_initialized;
|
static unsigned int s390_pci_initialized;
|
||||||
|
|
||||||
@ -877,7 +876,7 @@ char * __init pcibios_setup(char *str)
|
|||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
if (!strcmp(str, "nomio")) {
|
if (!strcmp(str, "nomio")) {
|
||||||
s390_pci_no_mio = 1;
|
S390_lowcore.machine_flags &= ~MACHINE_FLAG_PCI_MIO;
|
||||||
return NULL;
|
return NULL;
|
||||||
}
|
}
|
||||||
if (!strcmp(str, "force_floating")) {
|
if (!strcmp(str, "force_floating")) {
|
||||||
@ -906,7 +905,7 @@ static int __init pci_base_init(void)
|
|||||||
if (!test_facility(69) || !test_facility(71))
|
if (!test_facility(69) || !test_facility(71))
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
if (test_facility(153) && !s390_pci_no_mio) {
|
if (MACHINE_HAS_PCI_MIO) {
|
||||||
static_branch_enable(&have_mio);
|
static_branch_enable(&have_mio);
|
||||||
ctl_set_bit(2, 5);
|
ctl_set_bit(2, 5);
|
||||||
}
|
}
|
||||||
|
|||||||
@ -322,8 +322,6 @@ static void __init ms_hyperv_init_platform(void)
|
|||||||
if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
|
if (ms_hyperv.features & HV_ACCESS_TSC_INVARIANT) {
|
||||||
wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
|
wrmsrl(HV_X64_MSR_TSC_INVARIANT_CONTROL, 0x1);
|
||||||
setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
|
setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
|
||||||
} else {
|
|
||||||
mark_tsc_unstable("running on Hyper-V");
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -382,6 +380,13 @@ static void __init ms_hyperv_init_platform(void)
|
|||||||
/* Register Hyper-V specific clocksource */
|
/* Register Hyper-V specific clocksource */
|
||||||
hv_init_clocksource();
|
hv_init_clocksource();
|
||||||
#endif
|
#endif
|
||||||
|
/*
|
||||||
|
* TSC should be marked as unstable only after Hyper-V
|
||||||
|
* clocksource has been initialized. This ensures that the
|
||||||
|
* stability of the sched_clock is not altered.
|
||||||
|
*/
|
||||||
|
if (!(ms_hyperv.features & HV_ACCESS_TSC_INVARIANT))
|
||||||
|
mark_tsc_unstable("running on Hyper-V");
|
||||||
}
|
}
|
||||||
|
|
||||||
const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
|
const __initconst struct hypervisor_x86 x86_hyper_ms_hyperv = {
|
||||||
|
|||||||
@ -618,8 +618,8 @@ int xen_alloc_p2m_entry(unsigned long pfn)
|
|||||||
}
|
}
|
||||||
|
|
||||||
/* Expanded the p2m? */
|
/* Expanded the p2m? */
|
||||||
if (pfn > xen_p2m_last_pfn) {
|
if (pfn >= xen_p2m_last_pfn) {
|
||||||
xen_p2m_last_pfn = pfn;
|
xen_p2m_last_pfn = ALIGN(pfn + 1, P2M_PER_PAGE);
|
||||||
HYPERVISOR_shared_info->arch.max_pfn = xen_p2m_last_pfn;
|
HYPERVISOR_shared_info->arch.max_pfn = xen_p2m_last_pfn;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -168,9 +168,13 @@ static const struct tty_operations serial_ops = {
|
|||||||
|
|
||||||
int __init rs_init(void)
|
int __init rs_init(void)
|
||||||
{
|
{
|
||||||
tty_port_init(&serial_port);
|
int ret;
|
||||||
|
|
||||||
serial_driver = alloc_tty_driver(SERIAL_MAX_NUM_LINES);
|
serial_driver = alloc_tty_driver(SERIAL_MAX_NUM_LINES);
|
||||||
|
if (!serial_driver)
|
||||||
|
return -ENOMEM;
|
||||||
|
|
||||||
|
tty_port_init(&serial_port);
|
||||||
|
|
||||||
pr_info("%s %s\n", serial_name, serial_version);
|
pr_info("%s %s\n", serial_name, serial_version);
|
||||||
|
|
||||||
@ -190,8 +194,15 @@ int __init rs_init(void)
|
|||||||
tty_set_operations(serial_driver, &serial_ops);
|
tty_set_operations(serial_driver, &serial_ops);
|
||||||
tty_port_link_device(&serial_port, serial_driver, 0);
|
tty_port_link_device(&serial_port, serial_driver, 0);
|
||||||
|
|
||||||
if (tty_register_driver(serial_driver))
|
ret = tty_register_driver(serial_driver);
|
||||||
panic("Couldn't register serial driver\n");
|
if (ret) {
|
||||||
|
pr_err("Couldn't register serial driver\n");
|
||||||
|
tty_driver_kref_put(serial_driver);
|
||||||
|
tty_port_destroy(&serial_port);
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -5008,7 +5008,7 @@ bfq_set_next_ioprio_data(struct bfq_queue *bfqq, struct bfq_io_cq *bic)
|
|||||||
if (bfqq->new_ioprio >= IOPRIO_BE_NR) {
|
if (bfqq->new_ioprio >= IOPRIO_BE_NR) {
|
||||||
pr_crit("bfq_set_next_ioprio_data: new_ioprio %d\n",
|
pr_crit("bfq_set_next_ioprio_data: new_ioprio %d\n",
|
||||||
bfqq->new_ioprio);
|
bfqq->new_ioprio);
|
||||||
bfqq->new_ioprio = IOPRIO_BE_NR;
|
bfqq->new_ioprio = IOPRIO_BE_NR - 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->new_ioprio);
|
bfqq->entity.new_weight = bfq_ioprio_to_weight(bfqq->new_ioprio);
|
||||||
|
|||||||
@ -296,9 +296,6 @@ int blkdev_report_zones_ioctl(struct block_device *bdev, fmode_t mode,
|
|||||||
if (!blk_queue_is_zoned(q))
|
if (!blk_queue_is_zoned(q))
|
||||||
return -ENOTTY;
|
return -ENOTTY;
|
||||||
|
|
||||||
if (!capable(CAP_SYS_ADMIN))
|
|
||||||
return -EACCES;
|
|
||||||
|
|
||||||
if (copy_from_user(&rep, argp, sizeof(struct blk_zone_report)))
|
if (copy_from_user(&rep, argp, sizeof(struct blk_zone_report)))
|
||||||
return -EFAULT;
|
return -EFAULT;
|
||||||
|
|
||||||
@ -357,9 +354,6 @@ int blkdev_zone_mgmt_ioctl(struct block_device *bdev, fmode_t mode,
|
|||||||
if (!blk_queue_is_zoned(q))
|
if (!blk_queue_is_zoned(q))
|
||||||
return -ENOTTY;
|
return -ENOTTY;
|
||||||
|
|
||||||
if (!capable(CAP_SYS_ADMIN))
|
|
||||||
return -EACCES;
|
|
||||||
|
|
||||||
if (!(mode & FMODE_WRITE))
|
if (!(mode & FMODE_WRITE))
|
||||||
return -EBADF;
|
return -EBADF;
|
||||||
|
|
||||||
|
|||||||
@ -379,10 +379,13 @@ static long bsg_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
|
|||||||
case SG_GET_RESERVED_SIZE:
|
case SG_GET_RESERVED_SIZE:
|
||||||
case SG_SET_RESERVED_SIZE:
|
case SG_SET_RESERVED_SIZE:
|
||||||
case SG_EMULATED_HOST:
|
case SG_EMULATED_HOST:
|
||||||
case SCSI_IOCTL_SEND_COMMAND:
|
|
||||||
return scsi_cmd_ioctl(bd->queue, NULL, file->f_mode, cmd, uarg);
|
return scsi_cmd_ioctl(bd->queue, NULL, file->f_mode, cmd, uarg);
|
||||||
case SG_IO:
|
case SG_IO:
|
||||||
return bsg_sg_io(bd->queue, file->f_mode, uarg);
|
return bsg_sg_io(bd->queue, file->f_mode, uarg);
|
||||||
|
case SCSI_IOCTL_SEND_COMMAND:
|
||||||
|
pr_warn_ratelimited("%s: calling unsupported SCSI_IOCTL_SEND_COMMAND\n",
|
||||||
|
current->comm);
|
||||||
|
return -EINVAL;
|
||||||
default:
|
default:
|
||||||
return -ENOTTY;
|
return -ENOTTY;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -3950,6 +3950,10 @@ static const struct ata_blacklist_entry ata_device_blacklist [] = {
|
|||||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||||
{ "Samsung SSD 850*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
{ "Samsung SSD 850*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||||
|
{ "Samsung SSD 860*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||||
|
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||||
|
{ "Samsung SSD 870*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||||
|
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||||
{ "FCCT*M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
{ "FCCT*M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM |
|
||||||
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
ATA_HORKAGE_ZERO_AFTER_TRIM, },
|
||||||
|
|
||||||
|
|||||||
@ -1249,24 +1249,20 @@ static int sata_dwc_probe(struct platform_device *ofdev)
|
|||||||
irq = irq_of_parse_and_map(np, 0);
|
irq = irq_of_parse_and_map(np, 0);
|
||||||
if (irq == NO_IRQ) {
|
if (irq == NO_IRQ) {
|
||||||
dev_err(&ofdev->dev, "no SATA DMA irq\n");
|
dev_err(&ofdev->dev, "no SATA DMA irq\n");
|
||||||
err = -ENODEV;
|
return -ENODEV;
|
||||||
goto error_out;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#ifdef CONFIG_SATA_DWC_OLD_DMA
|
#ifdef CONFIG_SATA_DWC_OLD_DMA
|
||||||
if (!of_find_property(np, "dmas", NULL)) {
|
if (!of_find_property(np, "dmas", NULL)) {
|
||||||
err = sata_dwc_dma_init_old(ofdev, hsdev);
|
err = sata_dwc_dma_init_old(ofdev, hsdev);
|
||||||
if (err)
|
if (err)
|
||||||
goto error_out;
|
return err;
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
|
hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
|
||||||
if (IS_ERR(hsdev->phy)) {
|
if (IS_ERR(hsdev->phy))
|
||||||
err = PTR_ERR(hsdev->phy);
|
return PTR_ERR(hsdev->phy);
|
||||||
hsdev->phy = NULL;
|
|
||||||
goto error_out;
|
|
||||||
}
|
|
||||||
|
|
||||||
err = phy_init(hsdev->phy);
|
err = phy_init(hsdev->phy);
|
||||||
if (err)
|
if (err)
|
||||||
|
|||||||
@ -64,6 +64,8 @@ struct fsl_mc_addr_translation_range {
|
|||||||
#define MC_FAPR_PL BIT(18)
|
#define MC_FAPR_PL BIT(18)
|
||||||
#define MC_FAPR_BMT BIT(17)
|
#define MC_FAPR_BMT BIT(17)
|
||||||
|
|
||||||
|
static phys_addr_t mc_portal_base_phys_addr;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* fsl_mc_bus_match - device to driver matching callback
|
* fsl_mc_bus_match - device to driver matching callback
|
||||||
* @dev: the fsl-mc device to match against
|
* @dev: the fsl-mc device to match against
|
||||||
@ -597,14 +599,30 @@ static int fsl_mc_device_get_mmio_regions(struct fsl_mc_device *mc_dev,
|
|||||||
* If base address is in the region_desc use it otherwise
|
* If base address is in the region_desc use it otherwise
|
||||||
* revert to old mechanism
|
* revert to old mechanism
|
||||||
*/
|
*/
|
||||||
if (region_desc.base_address)
|
if (region_desc.base_address) {
|
||||||
regions[i].start = region_desc.base_address +
|
regions[i].start = region_desc.base_address +
|
||||||
region_desc.base_offset;
|
region_desc.base_offset;
|
||||||
else
|
} else {
|
||||||
error = translate_mc_addr(mc_dev, mc_region_type,
|
error = translate_mc_addr(mc_dev, mc_region_type,
|
||||||
region_desc.base_offset,
|
region_desc.base_offset,
|
||||||
®ions[i].start);
|
®ions[i].start);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some versions of the MC firmware wrongly report
|
||||||
|
* 0 for register base address of the DPMCP associated
|
||||||
|
* with child DPRC objects thus rendering them unusable.
|
||||||
|
* This is particularly troublesome in ACPI boot
|
||||||
|
* scenarios where the legacy way of extracting this
|
||||||
|
* base address from the device tree does not apply.
|
||||||
|
* Given that DPMCPs share the same base address,
|
||||||
|
* workaround this by using the base address extracted
|
||||||
|
* from the root DPRC container.
|
||||||
|
*/
|
||||||
|
if (is_fsl_mc_bus_dprc(mc_dev) &&
|
||||||
|
regions[i].start == region_desc.base_offset)
|
||||||
|
regions[i].start += mc_portal_base_phys_addr;
|
||||||
|
}
|
||||||
|
|
||||||
if (error < 0) {
|
if (error < 0) {
|
||||||
dev_err(parent_dev,
|
dev_err(parent_dev,
|
||||||
"Invalid MC offset: %#x (for %s.%d\'s region %d)\n",
|
"Invalid MC offset: %#x (for %s.%d\'s region %d)\n",
|
||||||
@ -996,6 +1014,8 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
|
|||||||
plat_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
plat_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||||
mc_portal_phys_addr = plat_res->start;
|
mc_portal_phys_addr = plat_res->start;
|
||||||
mc_portal_size = resource_size(plat_res);
|
mc_portal_size = resource_size(plat_res);
|
||||||
|
mc_portal_base_phys_addr = mc_portal_phys_addr & ~0x3ffffff;
|
||||||
|
|
||||||
error = fsl_create_mc_io(&pdev->dev, mc_portal_phys_addr,
|
error = fsl_create_mc_io(&pdev->dev, mc_portal_phys_addr,
|
||||||
mc_portal_size, NULL,
|
mc_portal_size, NULL,
|
||||||
FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &mc_io);
|
FSL_MC_IO_ATOMIC_CONTEXT_PORTAL, &mc_io);
|
||||||
|
|||||||
@ -128,6 +128,12 @@ static int clk_generated_determine_rate(struct clk_hw *hw,
|
|||||||
int i;
|
int i;
|
||||||
u32 div;
|
u32 div;
|
||||||
|
|
||||||
|
/* do not look for a rate that is outside of our range */
|
||||||
|
if (gck->range.max && req->rate > gck->range.max)
|
||||||
|
req->rate = gck->range.max;
|
||||||
|
if (gck->range.min && req->rate < gck->range.min)
|
||||||
|
req->rate = gck->range.min;
|
||||||
|
|
||||||
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
|
||||||
if (gck->chg_pid == i)
|
if (gck->chg_pid == i)
|
||||||
continue;
|
continue;
|
||||||
|
|||||||
@ -216,7 +216,8 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||||||
div->width = PCG_PREDIV_WIDTH;
|
div->width = PCG_PREDIV_WIDTH;
|
||||||
divider_ops = &imx8m_clk_composite_divider_ops;
|
divider_ops = &imx8m_clk_composite_divider_ops;
|
||||||
mux_ops = &clk_mux_ops;
|
mux_ops = &clk_mux_ops;
|
||||||
flags |= CLK_SET_PARENT_GATE;
|
if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
|
||||||
|
flags |= CLK_SET_PARENT_GATE;
|
||||||
}
|
}
|
||||||
|
|
||||||
div->lock = &imx_ccm_lock;
|
div->lock = &imx_ccm_lock;
|
||||||
|
|||||||
@ -458,10 +458,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* DRAM clocks are manipulated from TF-A outside clock framework.
|
* DRAM clocks are manipulated from TF-A outside clock framework.
|
||||||
* Mark with GET_RATE_NOCACHE to always read div value from hardware
|
* The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
|
||||||
|
* as div value should always be read from hardware
|
||||||
*/
|
*/
|
||||||
hws[IMX8MM_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
|
hws[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000);
|
||||||
hws[IMX8MM_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mm_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
|
hws[IMX8MM_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mm_dram_apb_sels, base + 0xa080);
|
||||||
|
|
||||||
/* IP */
|
/* IP */
|
||||||
hws[IMX8MM_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100);
|
hws[IMX8MM_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100);
|
||||||
|
|||||||
@ -441,10 +441,11 @@ static int imx8mn_clocks_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* DRAM clocks are manipulated from TF-A outside clock framework.
|
* DRAM clocks are manipulated from TF-A outside clock framework.
|
||||||
* Mark with GET_RATE_NOCACHE to always read div value from hardware
|
* The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
|
||||||
|
* as div value should always be read from hardware
|
||||||
*/
|
*/
|
||||||
hws[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
|
hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);
|
||||||
hws[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
|
hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);
|
||||||
|
|
||||||
hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
|
hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);
|
||||||
hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
|
hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);
|
||||||
|
|||||||
@ -427,11 +427,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev)
|
|||||||
|
|
||||||
/*
|
/*
|
||||||
* DRAM clocks are manipulated from TF-A outside clock framework.
|
* DRAM clocks are manipulated from TF-A outside clock framework.
|
||||||
* Mark with GET_RATE_NOCACHE to always read div value from hardware
|
* The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE
|
||||||
|
* as div value should always be read from hardware
|
||||||
*/
|
*/
|
||||||
hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);
|
hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);
|
||||||
hws[IMX8MQ_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);
|
hws[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);
|
||||||
hws[IMX8MQ_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mq_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);
|
hws[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);
|
||||||
|
|
||||||
/* IP */
|
/* IP */
|
||||||
hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
|
hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);
|
||||||
|
|||||||
@ -533,8 +533,9 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
|
|||||||
struct clk *div, struct clk *mux, struct clk *pll,
|
struct clk *div, struct clk *mux, struct clk *pll,
|
||||||
struct clk *step);
|
struct clk *step);
|
||||||
|
|
||||||
#define IMX_COMPOSITE_CORE BIT(0)
|
#define IMX_COMPOSITE_CORE BIT(0)
|
||||||
#define IMX_COMPOSITE_BUS BIT(1)
|
#define IMX_COMPOSITE_BUS BIT(1)
|
||||||
|
#define IMX_COMPOSITE_FW_MANAGED BIT(2)
|
||||||
|
|
||||||
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
||||||
const char * const *parent_names,
|
const char * const *parent_names,
|
||||||
@ -570,6 +571,17 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
|
|||||||
ARRAY_SIZE(parent_names), reg, 0, \
|
ARRAY_SIZE(parent_names), reg, 0, \
|
||||||
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||||
|
|
||||||
|
#define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \
|
||||||
|
imx8m_clk_hw_composite_flags(name, parent_names, \
|
||||||
|
ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_FW_MANAGED, \
|
||||||
|
flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
|
||||||
|
|
||||||
|
#define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \
|
||||||
|
__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)
|
||||||
|
|
||||||
|
#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \
|
||||||
|
__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)
|
||||||
|
|
||||||
#define __imx8m_clk_composite(name, parent_names, reg, flags) \
|
#define __imx8m_clk_composite(name, parent_names, reg, flags) \
|
||||||
to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
|
to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
|
||||||
|
|
||||||
|
|||||||
@ -940,7 +940,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
|
|||||||
switch (pll_type) {
|
switch (pll_type) {
|
||||||
case pll_rk3036:
|
case pll_rk3036:
|
||||||
case pll_rk3328:
|
case pll_rk3328:
|
||||||
if (!pll->rate_table || IS_ERR(ctx->grf))
|
if (!pll->rate_table)
|
||||||
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
|
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
|
||||||
else
|
else
|
||||||
init.ops = &rockchip_rk3036_pll_clk_ops;
|
init.ops = &rockchip_rk3036_pll_clk_ops;
|
||||||
|
|||||||
@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = {
|
|||||||
};
|
};
|
||||||
|
|
||||||
static const struct clk_parent_data psi_ref_free_mux[] = {
|
static const struct clk_parent_data psi_ref_free_mux[] = {
|
||||||
{ .fw_name = "main_pll_c3",
|
{ .fw_name = "main_pll_c2",
|
||||||
.name = "main_pll_c3", },
|
.name = "main_pll_c2", },
|
||||||
{ .fw_name = "peri_pll_c3",
|
{ .fw_name = "peri_pll_c2",
|
||||||
.name = "peri_pll_c3", },
|
.name = "peri_pll_c2", },
|
||||||
{ .fw_name = "osc1",
|
{ .fw_name = "osc1",
|
||||||
.name = "osc1", },
|
.name = "osc1", },
|
||||||
{ .fw_name = "cb-intosc-hs-div2-clk",
|
{ .fw_name = "cb-intosc-hs-div2-clk",
|
||||||
@ -193,6 +193,13 @@ static const struct clk_parent_data sdmmc_mux[] = {
|
|||||||
.name = "boot_clk", },
|
.name = "boot_clk", },
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static const struct clk_parent_data s2f_user0_mux[] = {
|
||||||
|
{ .fw_name = "s2f_user0_free_clk",
|
||||||
|
.name = "s2f_user0_free_clk", },
|
||||||
|
{ .fw_name = "boot_clk",
|
||||||
|
.name = "boot_clk", },
|
||||||
|
};
|
||||||
|
|
||||||
static const struct clk_parent_data s2f_user1_mux[] = {
|
static const struct clk_parent_data s2f_user1_mux[] = {
|
||||||
{ .fw_name = "s2f_user1_free_clk",
|
{ .fw_name = "s2f_user1_free_clk",
|
||||||
.name = "s2f_user1_free_clk", },
|
.name = "s2f_user1_free_clk", },
|
||||||
@ -260,7 +267,7 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
|
|||||||
{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
|
{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
|
||||||
ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
|
ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0},
|
||||||
{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
|
{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
|
||||||
ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
|
ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2},
|
||||||
{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
|
{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
|
||||||
ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
|
ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
|
||||||
{ AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
|
{ AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
|
||||||
@ -306,6 +313,8 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = {
|
|||||||
4, 0x98, 0, 16, 0x88, 3, 0},
|
4, 0x98, 0, 16, 0x88, 3, 0},
|
||||||
{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
|
{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,
|
||||||
5, 0, 0, 0, 0x88, 4, 4},
|
5, 0, 0, 0, 0x88, 4, 4},
|
||||||
|
{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,
|
||||||
|
6, 0, 0, 0, 0x30, 2, 0},
|
||||||
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
|
{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,
|
||||||
6, 0, 0, 0, 0x88, 5, 0},
|
6, 0, 0, 0, 0x88, 5, 0},
|
||||||
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
|
{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,
|
||||||
|
|||||||
@ -36,6 +36,7 @@
|
|||||||
#define MAX_PSTATE_SHIFT 32
|
#define MAX_PSTATE_SHIFT 32
|
||||||
#define LPSTATE_SHIFT 48
|
#define LPSTATE_SHIFT 48
|
||||||
#define GPSTATE_SHIFT 56
|
#define GPSTATE_SHIFT 56
|
||||||
|
#define MAX_NR_CHIPS 32
|
||||||
|
|
||||||
#define MAX_RAMP_DOWN_TIME 5120
|
#define MAX_RAMP_DOWN_TIME 5120
|
||||||
/*
|
/*
|
||||||
@ -1051,12 +1052,20 @@ static int init_chip_info(void)
|
|||||||
unsigned int *chip;
|
unsigned int *chip;
|
||||||
unsigned int cpu, i;
|
unsigned int cpu, i;
|
||||||
unsigned int prev_chip_id = UINT_MAX;
|
unsigned int prev_chip_id = UINT_MAX;
|
||||||
|
cpumask_t *chip_cpu_mask;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
chip = kcalloc(num_possible_cpus(), sizeof(*chip), GFP_KERNEL);
|
chip = kcalloc(num_possible_cpus(), sizeof(*chip), GFP_KERNEL);
|
||||||
if (!chip)
|
if (!chip)
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
|
|
||||||
|
/* Allocate a chip cpu mask large enough to fit mask for all chips */
|
||||||
|
chip_cpu_mask = kcalloc(MAX_NR_CHIPS, sizeof(cpumask_t), GFP_KERNEL);
|
||||||
|
if (!chip_cpu_mask) {
|
||||||
|
ret = -ENOMEM;
|
||||||
|
goto free_and_return;
|
||||||
|
}
|
||||||
|
|
||||||
for_each_possible_cpu(cpu) {
|
for_each_possible_cpu(cpu) {
|
||||||
unsigned int id = cpu_to_chip_id(cpu);
|
unsigned int id = cpu_to_chip_id(cpu);
|
||||||
|
|
||||||
@ -1064,22 +1073,25 @@ static int init_chip_info(void)
|
|||||||
prev_chip_id = id;
|
prev_chip_id = id;
|
||||||
chip[nr_chips++] = id;
|
chip[nr_chips++] = id;
|
||||||
}
|
}
|
||||||
|
cpumask_set_cpu(cpu, &chip_cpu_mask[nr_chips-1]);
|
||||||
}
|
}
|
||||||
|
|
||||||
chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
|
chips = kcalloc(nr_chips, sizeof(struct chip), GFP_KERNEL);
|
||||||
if (!chips) {
|
if (!chips) {
|
||||||
ret = -ENOMEM;
|
ret = -ENOMEM;
|
||||||
goto free_and_return;
|
goto out_free_chip_cpu_mask;
|
||||||
}
|
}
|
||||||
|
|
||||||
for (i = 0; i < nr_chips; i++) {
|
for (i = 0; i < nr_chips; i++) {
|
||||||
chips[i].id = chip[i];
|
chips[i].id = chip[i];
|
||||||
cpumask_copy(&chips[i].mask, cpumask_of_node(chip[i]));
|
cpumask_copy(&chips[i].mask, &chip_cpu_mask[i]);
|
||||||
INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
|
INIT_WORK(&chips[i].throttle, powernv_cpufreq_work_fn);
|
||||||
for_each_cpu(cpu, &chips[i].mask)
|
for_each_cpu(cpu, &chips[i].mask)
|
||||||
per_cpu(chip_info, cpu) = &chips[i];
|
per_cpu(chip_info, cpu) = &chips[i];
|
||||||
}
|
}
|
||||||
|
|
||||||
|
out_free_chip_cpu_mask:
|
||||||
|
kfree(chip_cpu_mask);
|
||||||
free_and_return:
|
free_and_return:
|
||||||
kfree(chip);
|
kfree(chip);
|
||||||
return ret;
|
return ret;
|
||||||
|
|||||||
@ -402,7 +402,7 @@ static void __init fixup_cede0_latency(void)
|
|||||||
* pseries_idle_probe()
|
* pseries_idle_probe()
|
||||||
* Choose state table for shared versus dedicated partition
|
* Choose state table for shared versus dedicated partition
|
||||||
*/
|
*/
|
||||||
static int pseries_idle_probe(void)
|
static int __init pseries_idle_probe(void)
|
||||||
{
|
{
|
||||||
|
|
||||||
if (cpuidle_disable != IDLE_NO_OVERRIDE)
|
if (cpuidle_disable != IDLE_NO_OVERRIDE)
|
||||||
@ -419,7 +419,21 @@ static int pseries_idle_probe(void)
|
|||||||
cpuidle_state_table = shared_states;
|
cpuidle_state_table = shared_states;
|
||||||
max_idle_state = ARRAY_SIZE(shared_states);
|
max_idle_state = ARRAY_SIZE(shared_states);
|
||||||
} else {
|
} else {
|
||||||
fixup_cede0_latency();
|
/*
|
||||||
|
* Use firmware provided latency values
|
||||||
|
* starting with POWER10 platforms. In the
|
||||||
|
* case that we are running on a POWER10
|
||||||
|
* platform but in an earlier compat mode, we
|
||||||
|
* can still use the firmware provided values.
|
||||||
|
*
|
||||||
|
* However, on platforms prior to POWER10, we
|
||||||
|
* cannot rely on the accuracy of the firmware
|
||||||
|
* provided latency values. On such platforms,
|
||||||
|
* go with the conservative default estimate
|
||||||
|
* of 10us.
|
||||||
|
*/
|
||||||
|
if (cpu_has_feature(CPU_FTR_ARCH_31) || pvr_version_is(PVR_POWER10))
|
||||||
|
fixup_cede0_latency();
|
||||||
cpuidle_state_table = dedicated_states;
|
cpuidle_state_table = dedicated_states;
|
||||||
max_idle_state = NR_DEDICATED_STATES;
|
max_idle_state = NR_DEDICATED_STATES;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -278,6 +278,9 @@ static int __sev_platform_shutdown_locked(int *error)
|
|||||||
struct sev_device *sev = psp_master->sev_data;
|
struct sev_device *sev = psp_master->sev_data;
|
||||||
int ret;
|
int ret;
|
||||||
|
|
||||||
|
if (sev->state == SEV_STATE_UNINIT)
|
||||||
|
return 0;
|
||||||
|
|
||||||
ret = __sev_do_cmd_locked(SEV_CMD_SHUTDOWN, NULL, error);
|
ret = __sev_do_cmd_locked(SEV_CMD_SHUTDOWN, NULL, error);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
@ -1018,6 +1021,20 @@ int sev_dev_init(struct psp_device *psp)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void sev_firmware_shutdown(struct sev_device *sev)
|
||||||
|
{
|
||||||
|
sev_platform_shutdown(NULL);
|
||||||
|
|
||||||
|
if (sev_es_tmr) {
|
||||||
|
/* The TMR area was encrypted, flush it from the cache */
|
||||||
|
wbinvd_on_all_cpus();
|
||||||
|
|
||||||
|
free_pages((unsigned long)sev_es_tmr,
|
||||||
|
get_order(SEV_ES_TMR_SIZE));
|
||||||
|
sev_es_tmr = NULL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
void sev_dev_destroy(struct psp_device *psp)
|
void sev_dev_destroy(struct psp_device *psp)
|
||||||
{
|
{
|
||||||
struct sev_device *sev = psp->sev_data;
|
struct sev_device *sev = psp->sev_data;
|
||||||
@ -1025,6 +1042,8 @@ void sev_dev_destroy(struct psp_device *psp)
|
|||||||
if (!sev)
|
if (!sev)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
sev_firmware_shutdown(sev);
|
||||||
|
|
||||||
if (sev->misc)
|
if (sev->misc)
|
||||||
kref_put(&misc_dev->refcount, sev_exit);
|
kref_put(&misc_dev->refcount, sev_exit);
|
||||||
|
|
||||||
@ -1055,21 +1074,6 @@ void sev_pci_init(void)
|
|||||||
if (sev_get_api_version())
|
if (sev_get_api_version())
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
/*
|
|
||||||
* If platform is not in UNINIT state then firmware upgrade and/or
|
|
||||||
* platform INIT command will fail. These command require UNINIT state.
|
|
||||||
*
|
|
||||||
* In a normal boot we should never run into case where the firmware
|
|
||||||
* is not in UNINIT state on boot. But in case of kexec boot, a reboot
|
|
||||||
* may not go through a typical shutdown sequence and may leave the
|
|
||||||
* firmware in INIT or WORKING state.
|
|
||||||
*/
|
|
||||||
|
|
||||||
if (sev->state != SEV_STATE_UNINIT) {
|
|
||||||
sev_platform_shutdown(NULL);
|
|
||||||
sev->state = SEV_STATE_UNINIT;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (sev_version_greater_or_equal(0, 15) &&
|
if (sev_version_greater_or_equal(0, 15) &&
|
||||||
sev_update_firmware(sev->dev) == 0)
|
sev_update_firmware(sev->dev) == 0)
|
||||||
sev_get_api_version();
|
sev_get_api_version();
|
||||||
@ -1114,17 +1118,10 @@ void sev_pci_init(void)
|
|||||||
|
|
||||||
void sev_pci_exit(void)
|
void sev_pci_exit(void)
|
||||||
{
|
{
|
||||||
if (!psp_master->sev_data)
|
struct sev_device *sev = psp_master->sev_data;
|
||||||
|
|
||||||
|
if (!sev)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
sev_platform_shutdown(NULL);
|
sev_firmware_shutdown(sev);
|
||||||
|
|
||||||
if (sev_es_tmr) {
|
|
||||||
/* The TMR area was encrypted, flush it from the cache */
|
|
||||||
wbinvd_on_all_cpus();
|
|
||||||
|
|
||||||
free_pages((unsigned long)sev_es_tmr,
|
|
||||||
get_order(SEV_ES_TMR_SIZE));
|
|
||||||
sev_es_tmr = NULL;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|||||||
@ -241,6 +241,17 @@ static int sp_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static void sp_pci_shutdown(struct pci_dev *pdev)
|
||||||
|
{
|
||||||
|
struct device *dev = &pdev->dev;
|
||||||
|
struct sp_device *sp = dev_get_drvdata(dev);
|
||||||
|
|
||||||
|
if (!sp)
|
||||||
|
return;
|
||||||
|
|
||||||
|
sp_destroy(sp);
|
||||||
|
}
|
||||||
|
|
||||||
static void sp_pci_remove(struct pci_dev *pdev)
|
static void sp_pci_remove(struct pci_dev *pdev)
|
||||||
{
|
{
|
||||||
struct device *dev = &pdev->dev;
|
struct device *dev = &pdev->dev;
|
||||||
@ -370,6 +381,7 @@ static struct pci_driver sp_pci_driver = {
|
|||||||
.id_table = sp_pci_table,
|
.id_table = sp_pci_table,
|
||||||
.probe = sp_pci_probe,
|
.probe = sp_pci_probe,
|
||||||
.remove = sp_pci_remove,
|
.remove = sp_pci_remove,
|
||||||
|
.shutdown = sp_pci_shutdown,
|
||||||
.driver.pm = &sp_pci_pm_ops,
|
.driver.pm = &sp_pci_pm_ops,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|||||||
@ -299,21 +299,20 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
|
|||||||
|
|
||||||
struct scatterlist *dst = req->dst;
|
struct scatterlist *dst = req->dst;
|
||||||
struct scatterlist *src = req->src;
|
struct scatterlist *src = req->src;
|
||||||
const int nents = sg_nents(req->src);
|
int dst_nents = sg_nents(dst);
|
||||||
|
|
||||||
const int out_off = DCP_BUF_SZ;
|
const int out_off = DCP_BUF_SZ;
|
||||||
uint8_t *in_buf = sdcp->coh->aes_in_buf;
|
uint8_t *in_buf = sdcp->coh->aes_in_buf;
|
||||||
uint8_t *out_buf = sdcp->coh->aes_out_buf;
|
uint8_t *out_buf = sdcp->coh->aes_out_buf;
|
||||||
|
|
||||||
uint8_t *out_tmp, *src_buf, *dst_buf = NULL;
|
|
||||||
uint32_t dst_off = 0;
|
uint32_t dst_off = 0;
|
||||||
|
uint8_t *src_buf = NULL;
|
||||||
uint32_t last_out_len = 0;
|
uint32_t last_out_len = 0;
|
||||||
|
|
||||||
uint8_t *key = sdcp->coh->aes_key;
|
uint8_t *key = sdcp->coh->aes_key;
|
||||||
|
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
int split = 0;
|
unsigned int i, len, clen, tlen = 0;
|
||||||
unsigned int i, len, clen, rem = 0, tlen = 0;
|
|
||||||
int init = 0;
|
int init = 0;
|
||||||
bool limit_hit = false;
|
bool limit_hit = false;
|
||||||
|
|
||||||
@ -331,7 +330,7 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
|
|||||||
memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
|
memset(key + AES_KEYSIZE_128, 0, AES_KEYSIZE_128);
|
||||||
}
|
}
|
||||||
|
|
||||||
for_each_sg(req->src, src, nents, i) {
|
for_each_sg(req->src, src, sg_nents(src), i) {
|
||||||
src_buf = sg_virt(src);
|
src_buf = sg_virt(src);
|
||||||
len = sg_dma_len(src);
|
len = sg_dma_len(src);
|
||||||
tlen += len;
|
tlen += len;
|
||||||
@ -356,34 +355,17 @@ static int mxs_dcp_aes_block_crypt(struct crypto_async_request *arq)
|
|||||||
* submit the buffer.
|
* submit the buffer.
|
||||||
*/
|
*/
|
||||||
if (actx->fill == out_off || sg_is_last(src) ||
|
if (actx->fill == out_off || sg_is_last(src) ||
|
||||||
limit_hit) {
|
limit_hit) {
|
||||||
ret = mxs_dcp_run_aes(actx, req, init);
|
ret = mxs_dcp_run_aes(actx, req, init);
|
||||||
if (ret)
|
if (ret)
|
||||||
return ret;
|
return ret;
|
||||||
init = 0;
|
init = 0;
|
||||||
|
|
||||||
out_tmp = out_buf;
|
sg_pcopy_from_buffer(dst, dst_nents, out_buf,
|
||||||
|
actx->fill, dst_off);
|
||||||
|
dst_off += actx->fill;
|
||||||
last_out_len = actx->fill;
|
last_out_len = actx->fill;
|
||||||
while (dst && actx->fill) {
|
actx->fill = 0;
|
||||||
if (!split) {
|
|
||||||
dst_buf = sg_virt(dst);
|
|
||||||
dst_off = 0;
|
|
||||||
}
|
|
||||||
rem = min(sg_dma_len(dst) - dst_off,
|
|
||||||
actx->fill);
|
|
||||||
|
|
||||||
memcpy(dst_buf + dst_off, out_tmp, rem);
|
|
||||||
out_tmp += rem;
|
|
||||||
dst_off += rem;
|
|
||||||
actx->fill -= rem;
|
|
||||||
|
|
||||||
if (dst_off == sg_dma_len(dst)) {
|
|
||||||
dst = sg_next(dst);
|
|
||||||
split = 0;
|
|
||||||
} else {
|
|
||||||
split = 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
} while (len);
|
} while (len);
|
||||||
|
|
||||||
|
|||||||
@ -379,7 +379,6 @@ struct sdma_channel {
|
|||||||
unsigned long watermark_level;
|
unsigned long watermark_level;
|
||||||
u32 shp_addr, per_addr;
|
u32 shp_addr, per_addr;
|
||||||
enum dma_status status;
|
enum dma_status status;
|
||||||
bool context_loaded;
|
|
||||||
struct imx_dma_data data;
|
struct imx_dma_data data;
|
||||||
struct work_struct terminate_worker;
|
struct work_struct terminate_worker;
|
||||||
};
|
};
|
||||||
@ -985,9 +984,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
|
|||||||
int ret;
|
int ret;
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
if (sdmac->context_loaded)
|
|
||||||
return 0;
|
|
||||||
|
|
||||||
if (sdmac->direction == DMA_DEV_TO_MEM)
|
if (sdmac->direction == DMA_DEV_TO_MEM)
|
||||||
load_address = sdmac->pc_from_device;
|
load_address = sdmac->pc_from_device;
|
||||||
else if (sdmac->direction == DMA_DEV_TO_DEV)
|
else if (sdmac->direction == DMA_DEV_TO_DEV)
|
||||||
@ -1030,8 +1026,6 @@ static int sdma_load_context(struct sdma_channel *sdmac)
|
|||||||
|
|
||||||
spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
|
spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
|
||||||
|
|
||||||
sdmac->context_loaded = true;
|
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1070,7 +1064,6 @@ static void sdma_channel_terminate_work(struct work_struct *work)
|
|||||||
vchan_get_all_descriptors(&sdmac->vc, &head);
|
vchan_get_all_descriptors(&sdmac->vc, &head);
|
||||||
spin_unlock_irqrestore(&sdmac->vc.lock, flags);
|
spin_unlock_irqrestore(&sdmac->vc.lock, flags);
|
||||||
vchan_dma_desc_free_list(&sdmac->vc, &head);
|
vchan_dma_desc_free_list(&sdmac->vc, &head);
|
||||||
sdmac->context_loaded = false;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int sdma_terminate_all(struct dma_chan *chan)
|
static int sdma_terminate_all(struct dma_chan *chan)
|
||||||
@ -1145,7 +1138,6 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
|
|||||||
static int sdma_config_channel(struct dma_chan *chan)
|
static int sdma_config_channel(struct dma_chan *chan)
|
||||||
{
|
{
|
||||||
struct sdma_channel *sdmac = to_sdma_chan(chan);
|
struct sdma_channel *sdmac = to_sdma_chan(chan);
|
||||||
int ret;
|
|
||||||
|
|
||||||
sdma_disable_channel(chan);
|
sdma_disable_channel(chan);
|
||||||
|
|
||||||
@ -1185,9 +1177,7 @@ static int sdma_config_channel(struct dma_chan *chan)
|
|||||||
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
|
sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
|
||||||
}
|
}
|
||||||
|
|
||||||
ret = sdma_load_context(sdmac);
|
return 0;
|
||||||
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
|
static int sdma_set_channel_priority(struct sdma_channel *sdmac,
|
||||||
@ -1338,7 +1328,6 @@ static void sdma_free_chan_resources(struct dma_chan *chan)
|
|||||||
|
|
||||||
sdmac->event_id0 = 0;
|
sdmac->event_id0 = 0;
|
||||||
sdmac->event_id1 = 0;
|
sdmac->event_id1 = 0;
|
||||||
sdmac->context_loaded = false;
|
|
||||||
|
|
||||||
sdma_set_channel_priority(sdmac, 0);
|
sdma_set_channel_priority(sdmac, 0);
|
||||||
|
|
||||||
|
|||||||
@ -339,7 +339,7 @@ static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus,
|
|||||||
void
|
void
|
||||||
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
|
amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector)
|
||||||
{
|
{
|
||||||
u8 val;
|
u8 val = 0;
|
||||||
|
|
||||||
if (!amdgpu_connector->router.ddc_valid)
|
if (!amdgpu_connector->router.ddc_valid)
|
||||||
return;
|
return;
|
||||||
|
|||||||
@ -207,7 +207,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
|
|||||||
c++;
|
c++;
|
||||||
}
|
}
|
||||||
|
|
||||||
BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS);
|
BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS);
|
||||||
|
|
||||||
placement->num_placement = c;
|
placement->num_placement = c;
|
||||||
placement->placement = places;
|
placement->placement = places;
|
||||||
|
|||||||
@ -305,7 +305,7 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control,
|
|||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
__decode_table_header_from_buff(hdr, &buff[2]);
|
__decode_table_header_from_buff(hdr, buff);
|
||||||
|
|
||||||
if (hdr->header == EEPROM_TABLE_HDR_VAL) {
|
if (hdr->header == EEPROM_TABLE_HDR_VAL) {
|
||||||
control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
|
control->num_recs = (hdr->tbl_size - EEPROM_TABLE_HEADER_SIZE) /
|
||||||
|
|||||||
@ -120,7 +120,7 @@ static int vcn_v1_0_sw_init(void *handle)
|
|||||||
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
|
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
|
||||||
adev->firmware.fw_size +=
|
adev->firmware.fw_size +=
|
||||||
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
||||||
DRM_INFO("PSP loading VCN firmware\n");
|
dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
r = amdgpu_vcn_resume(adev);
|
r = amdgpu_vcn_resume(adev);
|
||||||
|
|||||||
@ -122,7 +122,7 @@ static int vcn_v2_0_sw_init(void *handle)
|
|||||||
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
|
adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
|
||||||
adev->firmware.fw_size +=
|
adev->firmware.fw_size +=
|
||||||
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
||||||
DRM_INFO("PSP loading VCN firmware\n");
|
dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
r = amdgpu_vcn_resume(adev);
|
r = amdgpu_vcn_resume(adev);
|
||||||
|
|||||||
@ -152,7 +152,7 @@ static int vcn_v2_5_sw_init(void *handle)
|
|||||||
adev->firmware.fw_size +=
|
adev->firmware.fw_size +=
|
||||||
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
||||||
}
|
}
|
||||||
DRM_INFO("PSP loading VCN firmware\n");
|
dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
r = amdgpu_vcn_resume(adev);
|
r = amdgpu_vcn_resume(adev);
|
||||||
|
|||||||
@ -148,7 +148,7 @@ static int vcn_v3_0_sw_init(void *handle)
|
|||||||
adev->firmware.fw_size +=
|
adev->firmware.fw_size +=
|
||||||
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
|
||||||
}
|
}
|
||||||
DRM_INFO("PSP loading VCN firmware\n");
|
dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
|
||||||
}
|
}
|
||||||
|
|
||||||
r = amdgpu_vcn_resume(adev);
|
r = amdgpu_vcn_resume(adev);
|
||||||
|
|||||||
@ -98,36 +98,78 @@ void mqd_symmetrically_map_cu_mask(struct mqd_manager *mm,
|
|||||||
uint32_t *se_mask)
|
uint32_t *se_mask)
|
||||||
{
|
{
|
||||||
struct kfd_cu_info cu_info;
|
struct kfd_cu_info cu_info;
|
||||||
uint32_t cu_per_se[KFD_MAX_NUM_SE] = {0};
|
uint32_t cu_per_sh[KFD_MAX_NUM_SE][KFD_MAX_NUM_SH_PER_SE] = {0};
|
||||||
int i, se, sh, cu = 0;
|
int i, se, sh, cu;
|
||||||
|
|
||||||
amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
|
amdgpu_amdkfd_get_cu_info(mm->dev->kgd, &cu_info);
|
||||||
|
|
||||||
if (cu_mask_count > cu_info.cu_active_number)
|
if (cu_mask_count > cu_info.cu_active_number)
|
||||||
cu_mask_count = cu_info.cu_active_number;
|
cu_mask_count = cu_info.cu_active_number;
|
||||||
|
|
||||||
|
/* Exceeding these bounds corrupts the stack and indicates a coding error.
|
||||||
|
* Returning with no CU's enabled will hang the queue, which should be
|
||||||
|
* attention grabbing.
|
||||||
|
*/
|
||||||
|
if (cu_info.num_shader_engines > KFD_MAX_NUM_SE) {
|
||||||
|
pr_err("Exceeded KFD_MAX_NUM_SE, chip reports %d\n", cu_info.num_shader_engines);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (cu_info.num_shader_arrays_per_engine > KFD_MAX_NUM_SH_PER_SE) {
|
||||||
|
pr_err("Exceeded KFD_MAX_NUM_SH, chip reports %d\n",
|
||||||
|
cu_info.num_shader_arrays_per_engine * cu_info.num_shader_engines);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
/* Count active CUs per SH.
|
||||||
|
*
|
||||||
|
* Some CUs in an SH may be disabled. HW expects disabled CUs to be
|
||||||
|
* represented in the high bits of each SH's enable mask (the upper and lower
|
||||||
|
* 16 bits of se_mask) and will take care of the actual distribution of
|
||||||
|
* disabled CUs within each SH automatically.
|
||||||
|
* Each half of se_mask must be filled only on bits 0-cu_per_sh[se][sh]-1.
|
||||||
|
*
|
||||||
|
* See note on Arcturus cu_bitmap layout in gfx_v9_0_get_cu_info.
|
||||||
|
*/
|
||||||
for (se = 0; se < cu_info.num_shader_engines; se++)
|
for (se = 0; se < cu_info.num_shader_engines; se++)
|
||||||
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
|
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++)
|
||||||
cu_per_se[se] += hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
|
cu_per_sh[se][sh] = hweight32(cu_info.cu_bitmap[se % 4][sh + (se / 4)]);
|
||||||
|
|
||||||
/* Symmetrically map cu_mask to all SEs:
|
/* Symmetrically map cu_mask to all SEs & SHs:
|
||||||
* cu_mask[0] bit0 -> se_mask[0] bit0;
|
* se_mask programs up to 2 SH in the upper and lower 16 bits.
|
||||||
* cu_mask[0] bit1 -> se_mask[1] bit0;
|
*
|
||||||
* ... (if # SE is 4)
|
* Examples
|
||||||
* cu_mask[0] bit4 -> se_mask[0] bit1;
|
* Assuming 1 SH/SE, 4 SEs:
|
||||||
|
* cu_mask[0] bit0 -> se_mask[0] bit0
|
||||||
|
* cu_mask[0] bit1 -> se_mask[1] bit0
|
||||||
* ...
|
* ...
|
||||||
|
* cu_mask[0] bit4 -> se_mask[0] bit1
|
||||||
|
* ...
|
||||||
|
*
|
||||||
|
* Assuming 2 SH/SE, 4 SEs
|
||||||
|
* cu_mask[0] bit0 -> se_mask[0] bit0 (SE0,SH0,CU0)
|
||||||
|
* cu_mask[0] bit1 -> se_mask[1] bit0 (SE1,SH0,CU0)
|
||||||
|
* ...
|
||||||
|
* cu_mask[0] bit4 -> se_mask[0] bit16 (SE0,SH1,CU0)
|
||||||
|
* cu_mask[0] bit5 -> se_mask[1] bit16 (SE1,SH1,CU0)
|
||||||
|
* ...
|
||||||
|
* cu_mask[0] bit8 -> se_mask[0] bit1 (SE0,SH0,CU1)
|
||||||
|
* ...
|
||||||
|
*
|
||||||
|
* First ensure all CUs are disabled, then enable user specified CUs.
|
||||||
*/
|
*/
|
||||||
se = 0;
|
for (i = 0; i < cu_info.num_shader_engines; i++)
|
||||||
for (i = 0; i < cu_mask_count; i++) {
|
se_mask[i] = 0;
|
||||||
if (cu_mask[i / 32] & (1 << (i % 32)))
|
|
||||||
se_mask[se] |= 1 << cu;
|
|
||||||
|
|
||||||
do {
|
i = 0;
|
||||||
se++;
|
for (cu = 0; cu < 16; cu++) {
|
||||||
if (se == cu_info.num_shader_engines) {
|
for (sh = 0; sh < cu_info.num_shader_arrays_per_engine; sh++) {
|
||||||
se = 0;
|
for (se = 0; se < cu_info.num_shader_engines; se++) {
|
||||||
cu++;
|
if (cu_per_sh[se][sh] > cu) {
|
||||||
|
if (cu_mask[i / 32] & (1 << (i % 32)))
|
||||||
|
se_mask[se] |= 1 << (cu + sh * 16);
|
||||||
|
i++;
|
||||||
|
if (i == cu_mask_count)
|
||||||
|
return;
|
||||||
|
}
|
||||||
}
|
}
|
||||||
} while (cu >= cu_per_se[se] && cu < 32);
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|||||||
@ -27,6 +27,7 @@
|
|||||||
#include "kfd_priv.h"
|
#include "kfd_priv.h"
|
||||||
|
|
||||||
#define KFD_MAX_NUM_SE 8
|
#define KFD_MAX_NUM_SE 8
|
||||||
|
#define KFD_MAX_NUM_SH_PER_SE 2
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* struct mqd_manager
|
* struct mqd_manager
|
||||||
|
|||||||
@ -197,29 +197,29 @@ static ssize_t dp_link_settings_read(struct file *f, char __user *buf,
|
|||||||
|
|
||||||
rd_buf_ptr = rd_buf;
|
rd_buf_ptr = rd_buf;
|
||||||
|
|
||||||
str_len = strlen("Current: %d %d %d ");
|
str_len = strlen("Current: %d 0x%x %d ");
|
||||||
snprintf(rd_buf_ptr, str_len, "Current: %d %d %d ",
|
snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ",
|
||||||
link->cur_link_settings.lane_count,
|
link->cur_link_settings.lane_count,
|
||||||
link->cur_link_settings.link_rate,
|
link->cur_link_settings.link_rate,
|
||||||
link->cur_link_settings.link_spread);
|
link->cur_link_settings.link_spread);
|
||||||
rd_buf_ptr += str_len;
|
rd_buf_ptr += str_len;
|
||||||
|
|
||||||
str_len = strlen("Verified: %d %d %d ");
|
str_len = strlen("Verified: %d 0x%x %d ");
|
||||||
snprintf(rd_buf_ptr, str_len, "Verified: %d %d %d ",
|
snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ",
|
||||||
link->verified_link_cap.lane_count,
|
link->verified_link_cap.lane_count,
|
||||||
link->verified_link_cap.link_rate,
|
link->verified_link_cap.link_rate,
|
||||||
link->verified_link_cap.link_spread);
|
link->verified_link_cap.link_spread);
|
||||||
rd_buf_ptr += str_len;
|
rd_buf_ptr += str_len;
|
||||||
|
|
||||||
str_len = strlen("Reported: %d %d %d ");
|
str_len = strlen("Reported: %d 0x%x %d ");
|
||||||
snprintf(rd_buf_ptr, str_len, "Reported: %d %d %d ",
|
snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ",
|
||||||
link->reported_link_cap.lane_count,
|
link->reported_link_cap.lane_count,
|
||||||
link->reported_link_cap.link_rate,
|
link->reported_link_cap.link_rate,
|
||||||
link->reported_link_cap.link_spread);
|
link->reported_link_cap.link_spread);
|
||||||
rd_buf_ptr += str_len;
|
rd_buf_ptr += str_len;
|
||||||
|
|
||||||
str_len = strlen("Preferred: %d %d %d ");
|
str_len = strlen("Preferred: %d 0x%x %d ");
|
||||||
snprintf(rd_buf_ptr, str_len, "Preferred: %d %d %d\n",
|
snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n",
|
||||||
link->preferred_link_setting.lane_count,
|
link->preferred_link_setting.lane_count,
|
||||||
link->preferred_link_setting.link_rate,
|
link->preferred_link_setting.link_rate,
|
||||||
link->preferred_link_setting.link_spread);
|
link->preferred_link_setting.link_spread);
|
||||||
|
|||||||
@ -3740,13 +3740,12 @@ enum dc_status dcn10_set_clock(struct dc *dc,
|
|||||||
struct dc_clock_config clock_cfg = {0};
|
struct dc_clock_config clock_cfg = {0};
|
||||||
struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
|
struct dc_clocks *current_clocks = &context->bw_ctx.bw.dcn.clk;
|
||||||
|
|
||||||
if (dc->clk_mgr && dc->clk_mgr->funcs->get_clock)
|
if (!dc->clk_mgr || !dc->clk_mgr->funcs->get_clock)
|
||||||
dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
|
|
||||||
context, clock_type, &clock_cfg);
|
|
||||||
|
|
||||||
if (!dc->clk_mgr->funcs->get_clock)
|
|
||||||
return DC_FAIL_UNSUPPORTED_1;
|
return DC_FAIL_UNSUPPORTED_1;
|
||||||
|
|
||||||
|
dc->clk_mgr->funcs->get_clock(dc->clk_mgr,
|
||||||
|
context, clock_type, &clock_cfg);
|
||||||
|
|
||||||
if (clk_khz > clock_cfg.max_clock_khz)
|
if (clk_khz > clock_cfg.max_clock_khz)
|
||||||
return DC_FAIL_CLK_EXCEED_MAX;
|
return DC_FAIL_CLK_EXCEED_MAX;
|
||||||
|
|
||||||
@ -3764,7 +3763,7 @@ enum dc_status dcn10_set_clock(struct dc *dc,
|
|||||||
else
|
else
|
||||||
return DC_ERROR_UNEXPECTED;
|
return DC_ERROR_UNEXPECTED;
|
||||||
|
|
||||||
if (dc->clk_mgr && dc->clk_mgr->funcs->update_clocks)
|
if (dc->clk_mgr->funcs->update_clocks)
|
||||||
dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
|
dc->clk_mgr->funcs->update_clocks(dc->clk_mgr,
|
||||||
context, true);
|
context, true);
|
||||||
return DC_OK;
|
return DC_OK;
|
||||||
|
|||||||
@ -1704,13 +1704,15 @@ void dcn20_program_front_end_for_ctx(
|
|||||||
dcn20_program_pipe(dc, pipe, context);
|
dcn20_program_pipe(dc, pipe, context);
|
||||||
pipe = pipe->bottom_pipe;
|
pipe = pipe->bottom_pipe;
|
||||||
}
|
}
|
||||||
/* Program secondary blending tree and writeback pipes */
|
|
||||||
pipe = &context->res_ctx.pipe_ctx[i];
|
|
||||||
if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
|
|
||||||
&& (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
|
|
||||||
&& hws->funcs.program_all_writeback_pipes_in_tree)
|
|
||||||
hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
|
|
||||||
}
|
}
|
||||||
|
/* Program secondary blending tree and writeback pipes */
|
||||||
|
pipe = &context->res_ctx.pipe_ctx[i];
|
||||||
|
if (!pipe->top_pipe && !pipe->prev_odm_pipe
|
||||||
|
&& pipe->stream && pipe->stream->num_wb_info > 0
|
||||||
|
&& (pipe->update_flags.raw || (pipe->plane_state && pipe->plane_state->update_flags.raw)
|
||||||
|
|| pipe->stream->update_flags.raw)
|
||||||
|
&& hws->funcs.program_all_writeback_pipes_in_tree)
|
||||||
|
hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -2455,7 +2455,7 @@ void dcn20_set_mcif_arb_params(
|
|||||||
wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||||
wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
|
||||||
}
|
}
|
||||||
wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
|
wb_arb_params->time_per_pixel = 16.0 * 1000 / (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk / 1000); /* 4 bit fraction, ms */
|
||||||
wb_arb_params->slice_lines = 32;
|
wb_arb_params->slice_lines = 32;
|
||||||
wb_arb_params->arbitration_slice = 2;
|
wb_arb_params->arbitration_slice = 2;
|
||||||
wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
|
wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
|
||||||
|
|||||||
@ -49,6 +49,11 @@
|
|||||||
static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
|
static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
|
||||||
struct dcn3_xfer_func_reg *reg)
|
struct dcn3_xfer_func_reg *reg)
|
||||||
{
|
{
|
||||||
|
reg->shifts.field_region_start_base = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
|
||||||
|
reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B;
|
||||||
|
reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
|
||||||
|
reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
|
||||||
|
|
||||||
reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
|
reg->shifts.exp_region0_lut_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
|
||||||
reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
|
reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET;
|
||||||
reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
|
reg->shifts.exp_region0_num_segments = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
|
||||||
@ -66,8 +71,6 @@ static void dwb3_get_reg_field_ogam(struct dcn30_dwbc *dwbc30,
|
|||||||
reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
|
reg->masks.field_region_end_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_BASE_B;
|
||||||
reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
|
reg->shifts.field_region_linear_slope = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
|
||||||
reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
|
reg->masks.field_region_linear_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_SLOPE_B;
|
||||||
reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B;
|
|
||||||
reg->shifts.field_offset = dwbc30->dwbc_shift->DWB_OGAM_RAMA_OFFSET_B;
|
|
||||||
reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
|
reg->shifts.exp_region_start = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_B;
|
||||||
reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
|
reg->masks.exp_region_start = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_B;
|
||||||
reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
|
reg->shifts.exp_resion_start_segment = dwbc30->dwbc_shift->DWB_OGAM_RAMA_EXP_REGION_START_SEGMENT_B;
|
||||||
@ -147,18 +150,19 @@ static enum dc_lut_mode dwb3_get_ogam_current(
|
|||||||
uint32_t state_mode;
|
uint32_t state_mode;
|
||||||
uint32_t ram_select;
|
uint32_t ram_select;
|
||||||
|
|
||||||
REG_GET(DWB_OGAM_CONTROL,
|
REG_GET_2(DWB_OGAM_CONTROL,
|
||||||
DWB_OGAM_MODE, &state_mode);
|
DWB_OGAM_MODE_CURRENT, &state_mode,
|
||||||
REG_GET(DWB_OGAM_CONTROL,
|
DWB_OGAM_SELECT_CURRENT, &ram_select);
|
||||||
DWB_OGAM_SELECT, &ram_select);
|
|
||||||
|
|
||||||
if (state_mode == 0) {
|
if (state_mode == 0) {
|
||||||
mode = LUT_BYPASS;
|
mode = LUT_BYPASS;
|
||||||
} else if (state_mode == 2) {
|
} else if (state_mode == 2) {
|
||||||
if (ram_select == 0)
|
if (ram_select == 0)
|
||||||
mode = LUT_RAM_A;
|
mode = LUT_RAM_A;
|
||||||
else
|
else if (ram_select == 1)
|
||||||
mode = LUT_RAM_B;
|
mode = LUT_RAM_B;
|
||||||
|
else
|
||||||
|
mode = LUT_BYPASS;
|
||||||
} else {
|
} else {
|
||||||
// Reserved value
|
// Reserved value
|
||||||
mode = LUT_BYPASS;
|
mode = LUT_BYPASS;
|
||||||
@ -172,10 +176,10 @@ static void dwb3_configure_ogam_lut(
|
|||||||
struct dcn30_dwbc *dwbc30,
|
struct dcn30_dwbc *dwbc30,
|
||||||
bool is_ram_a)
|
bool is_ram_a)
|
||||||
{
|
{
|
||||||
REG_UPDATE(DWB_OGAM_LUT_CONTROL,
|
REG_UPDATE_2(DWB_OGAM_LUT_CONTROL,
|
||||||
DWB_OGAM_LUT_READ_COLOR_SEL, 7);
|
DWB_OGAM_LUT_WRITE_COLOR_MASK, 7,
|
||||||
REG_UPDATE(DWB_OGAM_CONTROL,
|
DWB_OGAM_LUT_HOST_SEL, (is_ram_a == true) ? 0 : 1);
|
||||||
DWB_OGAM_SELECT, is_ram_a == true ? 0 : 1);
|
|
||||||
REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
|
REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -185,17 +189,45 @@ static void dwb3_program_ogam_pwl(struct dcn30_dwbc *dwbc30,
|
|||||||
{
|
{
|
||||||
uint32_t i;
|
uint32_t i;
|
||||||
|
|
||||||
// triple base implementation
|
uint32_t last_base_value_red = rgb[num-1].red_reg + rgb[num-1].delta_red_reg;
|
||||||
for (i = 0; i < num/2; i++) {
|
uint32_t last_base_value_green = rgb[num-1].green_reg + rgb[num-1].delta_green_reg;
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].red_reg);
|
uint32_t last_base_value_blue = rgb[num-1].blue_reg + rgb[num-1].delta_blue_reg;
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].green_reg);
|
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+0].blue_reg);
|
if (is_rgb_equal(rgb, num)) {
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].red_reg);
|
for (i = 0 ; i < num; i++)
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].green_reg);
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+1].blue_reg);
|
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].red_reg);
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].green_reg);
|
|
||||||
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[2*i+2].blue_reg);
|
} else {
|
||||||
|
|
||||||
|
REG_UPDATE(DWB_OGAM_LUT_CONTROL,
|
||||||
|
DWB_OGAM_LUT_WRITE_COLOR_MASK, 4);
|
||||||
|
|
||||||
|
for (i = 0 ; i < num; i++)
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].red_reg);
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_red);
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
|
||||||
|
|
||||||
|
REG_UPDATE(DWB_OGAM_LUT_CONTROL,
|
||||||
|
DWB_OGAM_LUT_WRITE_COLOR_MASK, 2);
|
||||||
|
|
||||||
|
for (i = 0 ; i < num; i++)
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].green_reg);
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_green);
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_LUT_INDEX, 0, DWB_OGAM_LUT_INDEX, 0);
|
||||||
|
|
||||||
|
REG_UPDATE(DWB_OGAM_LUT_CONTROL,
|
||||||
|
DWB_OGAM_LUT_WRITE_COLOR_MASK, 1);
|
||||||
|
|
||||||
|
for (i = 0 ; i < num; i++)
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, rgb[i].blue_reg);
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_LUT_DATA, 0, DWB_OGAM_LUT_DATA, last_base_value_blue);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -211,6 +243,8 @@ static bool dwb3_program_ogam_lut(
|
|||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);
|
||||||
|
|
||||||
current_mode = dwb3_get_ogam_current(dwbc30);
|
current_mode = dwb3_get_ogam_current(dwbc30);
|
||||||
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
|
if (current_mode == LUT_BYPASS || current_mode == LUT_RAM_A)
|
||||||
next_mode = LUT_RAM_B;
|
next_mode = LUT_RAM_B;
|
||||||
@ -227,8 +261,7 @@ static bool dwb3_program_ogam_lut(
|
|||||||
dwb3_program_ogam_pwl(
|
dwb3_program_ogam_pwl(
|
||||||
dwbc30, params->rgb_resulted, params->hw_points_num);
|
dwbc30, params->rgb_resulted, params->hw_points_num);
|
||||||
|
|
||||||
REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_MODE, 2);
|
REG_UPDATE(DWB_OGAM_CONTROL, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
|
||||||
REG_SET(DWB_OGAM_CONTROL, 0, DWB_OGAM_SELECT, next_mode == LUT_RAM_A ? 0 : 1);
|
|
||||||
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
@ -271,14 +304,19 @@ static void dwb3_program_gamut_remap(
|
|||||||
|
|
||||||
struct color_matrices_reg gam_regs;
|
struct color_matrices_reg gam_regs;
|
||||||
|
|
||||||
REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);
|
|
||||||
|
|
||||||
if (regval == NULL || select == CM_GAMUT_REMAP_MODE_BYPASS) {
|
if (regval == NULL || select == CM_GAMUT_REMAP_MODE_BYPASS) {
|
||||||
REG_SET(DWB_GAMUT_REMAP_MODE, 0,
|
REG_SET(DWB_GAMUT_REMAP_MODE, 0,
|
||||||
DWB_GAMUT_REMAP_MODE, 0);
|
DWB_GAMUT_REMAP_MODE, 0);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
REG_UPDATE(DWB_GAMUT_REMAP_COEF_FORMAT, DWB_GAMUT_REMAP_COEF_FORMAT, coef_format);
|
||||||
|
|
||||||
|
gam_regs.shifts.csc_c11 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C11;
|
||||||
|
gam_regs.masks.csc_c11 = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C11;
|
||||||
|
gam_regs.shifts.csc_c12 = dwbc30->dwbc_shift->DWB_GAMUT_REMAPA_C12;
|
||||||
|
gam_regs.masks.csc_c12 = dwbc30->dwbc_mask->DWB_GAMUT_REMAPA_C12;
|
||||||
|
|
||||||
switch (select) {
|
switch (select) {
|
||||||
case CM_GAMUT_REMAP_MODE_RAMA_COEFF:
|
case CM_GAMUT_REMAP_MODE_RAMA_COEFF:
|
||||||
gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
|
gam_regs.csc_c11_c12 = REG(DWB_GAMUT_REMAPA_C11_C12);
|
||||||
|
|||||||
@ -396,12 +396,22 @@ void dcn30_program_all_writeback_pipes_in_tree(
|
|||||||
for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
|
for (i_pipe = 0; i_pipe < dc->res_pool->pipe_count; i_pipe++) {
|
||||||
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
|
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i_pipe];
|
||||||
|
|
||||||
|
if (!pipe_ctx->plane_state)
|
||||||
|
continue;
|
||||||
|
|
||||||
if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
|
if (pipe_ctx->plane_state == wb_info.writeback_source_plane) {
|
||||||
wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
|
wb_info.mpcc_inst = pipe_ctx->plane_res.mpcc_inst;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
ASSERT(wb_info.mpcc_inst != -1);
|
|
||||||
|
if (wb_info.mpcc_inst == -1) {
|
||||||
|
/* Disable writeback pipe and disconnect from MPCC
|
||||||
|
* if source plane has been removed
|
||||||
|
*/
|
||||||
|
dc->hwss.disable_writeback(dc, wb_info.dwb_pipe_inst);
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
|
ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb);
|
||||||
dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
|
dwb = dc->res_pool->dwbc[wb_info.dwb_pipe_inst];
|
||||||
|
|||||||
@ -2455,16 +2455,37 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
|
|||||||
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
|
dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
|
||||||
|
|
||||||
if (bw_params->clk_table.entries[0].memclk_mhz) {
|
if (bw_params->clk_table.entries[0].memclk_mhz) {
|
||||||
|
int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
|
||||||
|
|
||||||
if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
|
for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
|
||||||
|
if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
|
||||||
|
max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
|
||||||
|
if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
|
||||||
|
max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
|
||||||
|
if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
|
||||||
|
max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
|
||||||
|
if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
|
||||||
|
max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!max_dcfclk_mhz)
|
||||||
|
max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
|
||||||
|
if (!max_dispclk_mhz)
|
||||||
|
max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
|
||||||
|
if (!max_dppclk_mhz)
|
||||||
|
max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
|
||||||
|
if (!max_phyclk_mhz)
|
||||||
|
max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
|
||||||
|
|
||||||
|
if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
|
||||||
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
|
// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
|
||||||
dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
|
dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
|
||||||
num_dcfclk_sta_targets++;
|
num_dcfclk_sta_targets++;
|
||||||
} else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
|
} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
|
||||||
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
|
// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
|
||||||
for (i = 0; i < num_dcfclk_sta_targets; i++) {
|
for (i = 0; i < num_dcfclk_sta_targets; i++) {
|
||||||
if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
|
if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
|
||||||
dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
|
dcfclk_sta_targets[i] = max_dcfclk_mhz;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -2502,7 +2523,7 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
|
|||||||
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
|
dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
|
||||||
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
|
dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
|
||||||
} else {
|
} else {
|
||||||
if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
|
if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
|
||||||
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
|
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
|
||||||
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
|
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
|
||||||
} else {
|
} else {
|
||||||
@ -2517,11 +2538,12 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
|
|||||||
}
|
}
|
||||||
|
|
||||||
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
|
while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
|
||||||
optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
|
optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
|
||||||
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
|
dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
|
||||||
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
|
dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
dcn3_0_soc.num_states = num_states;
|
||||||
for (i = 0; i < dcn3_0_soc.num_states; i++) {
|
for (i = 0; i < dcn3_0_soc.num_states; i++) {
|
||||||
dcn3_0_soc.clock_limits[i].state = i;
|
dcn3_0_soc.clock_limits[i].state = i;
|
||||||
dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
|
dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
|
||||||
@ -2529,9 +2551,9 @@ void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
|
|||||||
dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
|
dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
|
||||||
|
|
||||||
/* Fill all states with max values of all other clocks */
|
/* Fill all states with max values of all other clocks */
|
||||||
dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
|
dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
|
||||||
dcn3_0_soc.clock_limits[i].dppclk_mhz = bw_params->clk_table.entries[1].dppclk_mhz;
|
dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
|
||||||
dcn3_0_soc.clock_limits[i].phyclk_mhz = bw_params->clk_table.entries[1].phyclk_mhz;
|
dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
|
||||||
dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
|
dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
|
||||||
/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
|
/* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
|
||||||
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
|
/* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
|
||||||
|
|||||||
@ -196,7 +196,7 @@ static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
|
|||||||
u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
|
||||||
|
|
||||||
return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
|
return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
|
||||||
dsi->lanes * 8 * NSEC_PER_SEC);
|
dsi->lanes * 8ULL * NSEC_PER_SEC);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|||||||
@ -135,16 +135,18 @@ static void drm_set_master(struct drm_device *dev, struct drm_file *fpriv,
|
|||||||
static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv)
|
static int drm_new_set_master(struct drm_device *dev, struct drm_file *fpriv)
|
||||||
{
|
{
|
||||||
struct drm_master *old_master;
|
struct drm_master *old_master;
|
||||||
|
struct drm_master *new_master;
|
||||||
|
|
||||||
lockdep_assert_held_once(&dev->master_mutex);
|
lockdep_assert_held_once(&dev->master_mutex);
|
||||||
|
|
||||||
WARN_ON(fpriv->is_master);
|
WARN_ON(fpriv->is_master);
|
||||||
old_master = fpriv->master;
|
old_master = fpriv->master;
|
||||||
fpriv->master = drm_master_create(dev);
|
new_master = drm_master_create(dev);
|
||||||
if (!fpriv->master) {
|
if (!new_master)
|
||||||
fpriv->master = old_master;
|
|
||||||
return -ENOMEM;
|
return -ENOMEM;
|
||||||
}
|
spin_lock(&fpriv->master_lookup_lock);
|
||||||
|
fpriv->master = new_master;
|
||||||
|
spin_unlock(&fpriv->master_lookup_lock);
|
||||||
|
|
||||||
fpriv->is_master = 1;
|
fpriv->is_master = 1;
|
||||||
fpriv->authenticated = 1;
|
fpriv->authenticated = 1;
|
||||||
@ -302,10 +304,13 @@ int drm_master_open(struct drm_file *file_priv)
|
|||||||
/* if there is no current master make this fd it, but do not create
|
/* if there is no current master make this fd it, but do not create
|
||||||
* any master object for render clients */
|
* any master object for render clients */
|
||||||
mutex_lock(&dev->master_mutex);
|
mutex_lock(&dev->master_mutex);
|
||||||
if (!dev->master)
|
if (!dev->master) {
|
||||||
ret = drm_new_set_master(dev, file_priv);
|
ret = drm_new_set_master(dev, file_priv);
|
||||||
else
|
} else {
|
||||||
|
spin_lock(&file_priv->master_lookup_lock);
|
||||||
file_priv->master = drm_master_get(dev->master);
|
file_priv->master = drm_master_get(dev->master);
|
||||||
|
spin_unlock(&file_priv->master_lookup_lock);
|
||||||
|
}
|
||||||
mutex_unlock(&dev->master_mutex);
|
mutex_unlock(&dev->master_mutex);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
@ -371,6 +376,31 @@ struct drm_master *drm_master_get(struct drm_master *master)
|
|||||||
}
|
}
|
||||||
EXPORT_SYMBOL(drm_master_get);
|
EXPORT_SYMBOL(drm_master_get);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* drm_file_get_master - reference &drm_file.master of @file_priv
|
||||||
|
* @file_priv: DRM file private
|
||||||
|
*
|
||||||
|
* Increments the reference count of @file_priv's &drm_file.master and returns
|
||||||
|
* the &drm_file.master. If @file_priv has no &drm_file.master, returns NULL.
|
||||||
|
*
|
||||||
|
* Master pointers returned from this function should be unreferenced using
|
||||||
|
* drm_master_put().
|
||||||
|
*/
|
||||||
|
struct drm_master *drm_file_get_master(struct drm_file *file_priv)
|
||||||
|
{
|
||||||
|
struct drm_master *master = NULL;
|
||||||
|
|
||||||
|
spin_lock(&file_priv->master_lookup_lock);
|
||||||
|
if (!file_priv->master)
|
||||||
|
goto unlock;
|
||||||
|
master = drm_master_get(file_priv->master);
|
||||||
|
|
||||||
|
unlock:
|
||||||
|
spin_unlock(&file_priv->master_lookup_lock);
|
||||||
|
return master;
|
||||||
|
}
|
||||||
|
EXPORT_SYMBOL(drm_file_get_master);
|
||||||
|
|
||||||
static void drm_master_destroy(struct kref *kref)
|
static void drm_master_destroy(struct kref *kref)
|
||||||
{
|
{
|
||||||
struct drm_master *master = container_of(kref, struct drm_master, refcount);
|
struct drm_master *master = container_of(kref, struct drm_master, refcount);
|
||||||
|
|||||||
@ -91,6 +91,7 @@ static int drm_clients_info(struct seq_file *m, void *data)
|
|||||||
mutex_lock(&dev->filelist_mutex);
|
mutex_lock(&dev->filelist_mutex);
|
||||||
list_for_each_entry_reverse(priv, &dev->filelist, lhead) {
|
list_for_each_entry_reverse(priv, &dev->filelist, lhead) {
|
||||||
struct task_struct *task;
|
struct task_struct *task;
|
||||||
|
bool is_current_master = drm_is_current_master(priv);
|
||||||
|
|
||||||
rcu_read_lock(); /* locks pid_task()->comm */
|
rcu_read_lock(); /* locks pid_task()->comm */
|
||||||
task = pid_task(priv->pid, PIDTYPE_PID);
|
task = pid_task(priv->pid, PIDTYPE_PID);
|
||||||
@ -99,7 +100,7 @@ static int drm_clients_info(struct seq_file *m, void *data)
|
|||||||
task ? task->comm : "<unknown>",
|
task ? task->comm : "<unknown>",
|
||||||
pid_vnr(priv->pid),
|
pid_vnr(priv->pid),
|
||||||
priv->minor->index,
|
priv->minor->index,
|
||||||
drm_is_current_master(priv) ? 'y' : 'n',
|
is_current_master ? 'y' : 'n',
|
||||||
priv->authenticated ? 'y' : 'n',
|
priv->authenticated ? 'y' : 'n',
|
||||||
from_kuid_munged(seq_user_ns(m), uid),
|
from_kuid_munged(seq_user_ns(m), uid),
|
||||||
priv->magic);
|
priv->magic);
|
||||||
|
|||||||
@ -2869,11 +2869,13 @@ static int process_single_tx_qlock(struct drm_dp_mst_topology_mgr *mgr,
|
|||||||
idx += tosend + 1;
|
idx += tosend + 1;
|
||||||
|
|
||||||
ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
|
ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
|
||||||
if (unlikely(ret) && drm_debug_enabled(DRM_UT_DP)) {
|
if (ret) {
|
||||||
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
|
if (drm_debug_enabled(DRM_UT_DP)) {
|
||||||
|
struct drm_printer p = drm_debug_printer(DBG_PREFIX);
|
||||||
|
|
||||||
drm_printf(&p, "sideband msg failed to send\n");
|
drm_printf(&p, "sideband msg failed to send\n");
|
||||||
drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
|
drm_dp_mst_dump_sideband_msg_tx(&p, txmsg);
|
||||||
|
}
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -177,6 +177,7 @@ struct drm_file *drm_file_alloc(struct drm_minor *minor)
|
|||||||
init_waitqueue_head(&file->event_wait);
|
init_waitqueue_head(&file->event_wait);
|
||||||
file->event_space = 4096; /* set aside 4k for event buffer */
|
file->event_space = 4096; /* set aside 4k for event buffer */
|
||||||
|
|
||||||
|
spin_lock_init(&file->master_lookup_lock);
|
||||||
mutex_init(&file->event_read_lock);
|
mutex_init(&file->event_read_lock);
|
||||||
|
|
||||||
if (drm_core_check_feature(dev, DRIVER_GEM))
|
if (drm_core_check_feature(dev, DRIVER_GEM))
|
||||||
|
|||||||
@ -107,10 +107,19 @@ static bool _drm_has_leased(struct drm_master *master, int id)
|
|||||||
*/
|
*/
|
||||||
bool _drm_lease_held(struct drm_file *file_priv, int id)
|
bool _drm_lease_held(struct drm_file *file_priv, int id)
|
||||||
{
|
{
|
||||||
if (!file_priv || !file_priv->master)
|
bool ret;
|
||||||
|
struct drm_master *master;
|
||||||
|
|
||||||
|
if (!file_priv)
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
return _drm_lease_held_master(file_priv->master, id);
|
master = drm_file_get_master(file_priv);
|
||||||
|
if (!master)
|
||||||
|
return true;
|
||||||
|
ret = _drm_lease_held_master(master, id);
|
||||||
|
drm_master_put(&master);
|
||||||
|
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
/**
|
/**
|
||||||
@ -129,13 +138,22 @@ bool drm_lease_held(struct drm_file *file_priv, int id)
|
|||||||
struct drm_master *master;
|
struct drm_master *master;
|
||||||
bool ret;
|
bool ret;
|
||||||
|
|
||||||
if (!file_priv || !file_priv->master || !file_priv->master->lessor)
|
if (!file_priv)
|
||||||
return true;
|
return true;
|
||||||
|
|
||||||
master = file_priv->master;
|
master = drm_file_get_master(file_priv);
|
||||||
|
if (!master)
|
||||||
|
return true;
|
||||||
|
if (!master->lessor) {
|
||||||
|
ret = true;
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
mutex_lock(&master->dev->mode_config.idr_mutex);
|
mutex_lock(&master->dev->mode_config.idr_mutex);
|
||||||
ret = _drm_lease_held_master(master, id);
|
ret = _drm_lease_held_master(master, id);
|
||||||
mutex_unlock(&master->dev->mode_config.idr_mutex);
|
mutex_unlock(&master->dev->mode_config.idr_mutex);
|
||||||
|
|
||||||
|
out:
|
||||||
|
drm_master_put(&master);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -155,10 +173,16 @@ uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs_in)
|
|||||||
int count_in, count_out;
|
int count_in, count_out;
|
||||||
uint32_t crtcs_out = 0;
|
uint32_t crtcs_out = 0;
|
||||||
|
|
||||||
if (!file_priv || !file_priv->master || !file_priv->master->lessor)
|
if (!file_priv)
|
||||||
return crtcs_in;
|
return crtcs_in;
|
||||||
|
|
||||||
master = file_priv->master;
|
master = drm_file_get_master(file_priv);
|
||||||
|
if (!master)
|
||||||
|
return crtcs_in;
|
||||||
|
if (!master->lessor) {
|
||||||
|
crtcs_out = crtcs_in;
|
||||||
|
goto out;
|
||||||
|
}
|
||||||
dev = master->dev;
|
dev = master->dev;
|
||||||
|
|
||||||
count_in = count_out = 0;
|
count_in = count_out = 0;
|
||||||
@ -177,6 +201,9 @@ uint32_t drm_lease_filter_crtcs(struct drm_file *file_priv, uint32_t crtcs_in)
|
|||||||
count_in++;
|
count_in++;
|
||||||
}
|
}
|
||||||
mutex_unlock(&master->dev->mode_config.idr_mutex);
|
mutex_unlock(&master->dev->mode_config.idr_mutex);
|
||||||
|
|
||||||
|
out:
|
||||||
|
drm_master_put(&master);
|
||||||
return crtcs_out;
|
return crtcs_out;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -490,7 +517,7 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
size_t object_count;
|
size_t object_count;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
struct idr leases;
|
struct idr leases;
|
||||||
struct drm_master *lessor = lessor_priv->master;
|
struct drm_master *lessor;
|
||||||
struct drm_master *lessee = NULL;
|
struct drm_master *lessee = NULL;
|
||||||
struct file *lessee_file = NULL;
|
struct file *lessee_file = NULL;
|
||||||
struct file *lessor_file = lessor_priv->filp;
|
struct file *lessor_file = lessor_priv->filp;
|
||||||
@ -502,12 +529,6 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
return -EOPNOTSUPP;
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
/* Do not allow sub-leases */
|
|
||||||
if (lessor->lessor) {
|
|
||||||
DRM_DEBUG_LEASE("recursive leasing not allowed\n");
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* need some objects */
|
/* need some objects */
|
||||||
if (cl->object_count == 0) {
|
if (cl->object_count == 0) {
|
||||||
DRM_DEBUG_LEASE("no objects in lease\n");
|
DRM_DEBUG_LEASE("no objects in lease\n");
|
||||||
@ -519,12 +540,22 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
return -EINVAL;
|
return -EINVAL;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
lessor = drm_file_get_master(lessor_priv);
|
||||||
|
/* Do not allow sub-leases */
|
||||||
|
if (lessor->lessor) {
|
||||||
|
DRM_DEBUG_LEASE("recursive leasing not allowed\n");
|
||||||
|
ret = -EINVAL;
|
||||||
|
goto out_lessor;
|
||||||
|
}
|
||||||
|
|
||||||
object_count = cl->object_count;
|
object_count = cl->object_count;
|
||||||
|
|
||||||
object_ids = memdup_user(u64_to_user_ptr(cl->object_ids),
|
object_ids = memdup_user(u64_to_user_ptr(cl->object_ids),
|
||||||
array_size(object_count, sizeof(__u32)));
|
array_size(object_count, sizeof(__u32)));
|
||||||
if (IS_ERR(object_ids))
|
if (IS_ERR(object_ids)) {
|
||||||
return PTR_ERR(object_ids);
|
ret = PTR_ERR(object_ids);
|
||||||
|
goto out_lessor;
|
||||||
|
}
|
||||||
|
|
||||||
idr_init(&leases);
|
idr_init(&leases);
|
||||||
|
|
||||||
@ -535,14 +566,15 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
if (ret) {
|
if (ret) {
|
||||||
DRM_DEBUG_LEASE("lease object lookup failed: %i\n", ret);
|
DRM_DEBUG_LEASE("lease object lookup failed: %i\n", ret);
|
||||||
idr_destroy(&leases);
|
idr_destroy(&leases);
|
||||||
return ret;
|
goto out_lessor;
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Allocate a file descriptor for the lease */
|
/* Allocate a file descriptor for the lease */
|
||||||
fd = get_unused_fd_flags(cl->flags & (O_CLOEXEC | O_NONBLOCK));
|
fd = get_unused_fd_flags(cl->flags & (O_CLOEXEC | O_NONBLOCK));
|
||||||
if (fd < 0) {
|
if (fd < 0) {
|
||||||
idr_destroy(&leases);
|
idr_destroy(&leases);
|
||||||
return fd;
|
ret = fd;
|
||||||
|
goto out_lessor;
|
||||||
}
|
}
|
||||||
|
|
||||||
DRM_DEBUG_LEASE("Creating lease\n");
|
DRM_DEBUG_LEASE("Creating lease\n");
|
||||||
@ -578,6 +610,7 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
/* Hook up the fd */
|
/* Hook up the fd */
|
||||||
fd_install(fd, lessee_file);
|
fd_install(fd, lessee_file);
|
||||||
|
|
||||||
|
drm_master_put(&lessor);
|
||||||
DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl succeeded\n");
|
DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl succeeded\n");
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
@ -587,6 +620,8 @@ int drm_mode_create_lease_ioctl(struct drm_device *dev,
|
|||||||
out_leases:
|
out_leases:
|
||||||
put_unused_fd(fd);
|
put_unused_fd(fd);
|
||||||
|
|
||||||
|
out_lessor:
|
||||||
|
drm_master_put(&lessor);
|
||||||
DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);
|
DRM_DEBUG_LEASE("drm_mode_create_lease_ioctl failed: %d\n", ret);
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
@ -609,7 +644,7 @@ int drm_mode_list_lessees_ioctl(struct drm_device *dev,
|
|||||||
struct drm_mode_list_lessees *arg = data;
|
struct drm_mode_list_lessees *arg = data;
|
||||||
__u32 __user *lessee_ids = (__u32 __user *) (uintptr_t) (arg->lessees_ptr);
|
__u32 __user *lessee_ids = (__u32 __user *) (uintptr_t) (arg->lessees_ptr);
|
||||||
__u32 count_lessees = arg->count_lessees;
|
__u32 count_lessees = arg->count_lessees;
|
||||||
struct drm_master *lessor = lessor_priv->master, *lessee;
|
struct drm_master *lessor, *lessee;
|
||||||
int count;
|
int count;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
@ -620,6 +655,7 @@ int drm_mode_list_lessees_ioctl(struct drm_device *dev,
|
|||||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
return -EOPNOTSUPP;
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
|
lessor = drm_file_get_master(lessor_priv);
|
||||||
DRM_DEBUG_LEASE("List lessees for %d\n", lessor->lessee_id);
|
DRM_DEBUG_LEASE("List lessees for %d\n", lessor->lessee_id);
|
||||||
|
|
||||||
mutex_lock(&dev->mode_config.idr_mutex);
|
mutex_lock(&dev->mode_config.idr_mutex);
|
||||||
@ -643,6 +679,7 @@ int drm_mode_list_lessees_ioctl(struct drm_device *dev,
|
|||||||
arg->count_lessees = count;
|
arg->count_lessees = count;
|
||||||
|
|
||||||
mutex_unlock(&dev->mode_config.idr_mutex);
|
mutex_unlock(&dev->mode_config.idr_mutex);
|
||||||
|
drm_master_put(&lessor);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
@ -662,7 +699,7 @@ int drm_mode_get_lease_ioctl(struct drm_device *dev,
|
|||||||
struct drm_mode_get_lease *arg = data;
|
struct drm_mode_get_lease *arg = data;
|
||||||
__u32 __user *object_ids = (__u32 __user *) (uintptr_t) (arg->objects_ptr);
|
__u32 __user *object_ids = (__u32 __user *) (uintptr_t) (arg->objects_ptr);
|
||||||
__u32 count_objects = arg->count_objects;
|
__u32 count_objects = arg->count_objects;
|
||||||
struct drm_master *lessee = lessee_priv->master;
|
struct drm_master *lessee;
|
||||||
struct idr *object_idr;
|
struct idr *object_idr;
|
||||||
int count;
|
int count;
|
||||||
void *entry;
|
void *entry;
|
||||||
@ -676,6 +713,7 @@ int drm_mode_get_lease_ioctl(struct drm_device *dev,
|
|||||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
return -EOPNOTSUPP;
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
|
lessee = drm_file_get_master(lessee_priv);
|
||||||
DRM_DEBUG_LEASE("get lease for %d\n", lessee->lessee_id);
|
DRM_DEBUG_LEASE("get lease for %d\n", lessee->lessee_id);
|
||||||
|
|
||||||
mutex_lock(&dev->mode_config.idr_mutex);
|
mutex_lock(&dev->mode_config.idr_mutex);
|
||||||
@ -703,6 +741,7 @@ int drm_mode_get_lease_ioctl(struct drm_device *dev,
|
|||||||
arg->count_objects = count;
|
arg->count_objects = count;
|
||||||
|
|
||||||
mutex_unlock(&dev->mode_config.idr_mutex);
|
mutex_unlock(&dev->mode_config.idr_mutex);
|
||||||
|
drm_master_put(&lessee);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
@ -721,7 +760,7 @@ int drm_mode_revoke_lease_ioctl(struct drm_device *dev,
|
|||||||
void *data, struct drm_file *lessor_priv)
|
void *data, struct drm_file *lessor_priv)
|
||||||
{
|
{
|
||||||
struct drm_mode_revoke_lease *arg = data;
|
struct drm_mode_revoke_lease *arg = data;
|
||||||
struct drm_master *lessor = lessor_priv->master;
|
struct drm_master *lessor;
|
||||||
struct drm_master *lessee;
|
struct drm_master *lessee;
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
|
|
||||||
@ -731,6 +770,7 @@ int drm_mode_revoke_lease_ioctl(struct drm_device *dev,
|
|||||||
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
||||||
return -EOPNOTSUPP;
|
return -EOPNOTSUPP;
|
||||||
|
|
||||||
|
lessor = drm_file_get_master(lessor_priv);
|
||||||
mutex_lock(&dev->mode_config.idr_mutex);
|
mutex_lock(&dev->mode_config.idr_mutex);
|
||||||
|
|
||||||
lessee = _drm_find_lessee(lessor, arg->lessee_id);
|
lessee = _drm_find_lessee(lessor, arg->lessee_id);
|
||||||
@ -751,6 +791,7 @@ int drm_mode_revoke_lease_ioctl(struct drm_device *dev,
|
|||||||
|
|
||||||
fail:
|
fail:
|
||||||
mutex_unlock(&dev->mode_config.idr_mutex);
|
mutex_unlock(&dev->mode_config.idr_mutex);
|
||||||
|
drm_master_put(&lessor);
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
|
|||||||
@ -115,6 +115,8 @@ int exynos_drm_register_dma(struct drm_device *drm, struct device *dev,
|
|||||||
EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE);
|
EXYNOS_DEV_ADDR_START, EXYNOS_DEV_ADDR_SIZE);
|
||||||
else if (IS_ENABLED(CONFIG_IOMMU_DMA))
|
else if (IS_ENABLED(CONFIG_IOMMU_DMA))
|
||||||
mapping = iommu_get_domain_for_dev(priv->dma_dev);
|
mapping = iommu_get_domain_for_dev(priv->dma_dev);
|
||||||
|
else
|
||||||
|
mapping = ERR_PTR(-ENODEV);
|
||||||
|
|
||||||
if (IS_ERR(mapping))
|
if (IS_ERR(mapping))
|
||||||
return PTR_ERR(mapping);
|
return PTR_ERR(mapping);
|
||||||
|
|||||||
@ -43,6 +43,22 @@
|
|||||||
#define ATTR_INDEX 0x1fc0
|
#define ATTR_INDEX 0x1fc0
|
||||||
#define ATTR_DATA 0x1fc1
|
#define ATTR_DATA 0x1fc1
|
||||||
|
|
||||||
|
#define WREG_MISC(v) \
|
||||||
|
WREG8(MGA_MISC_OUT, v)
|
||||||
|
|
||||||
|
#define RREG_MISC(v) \
|
||||||
|
((v) = RREG8(MGA_MISC_IN))
|
||||||
|
|
||||||
|
#define WREG_MISC_MASKED(v, mask) \
|
||||||
|
do { \
|
||||||
|
u8 misc_; \
|
||||||
|
u8 mask_ = (mask); \
|
||||||
|
RREG_MISC(misc_); \
|
||||||
|
misc_ &= ~mask_; \
|
||||||
|
misc_ |= ((v) & mask_); \
|
||||||
|
WREG_MISC(misc_); \
|
||||||
|
} while (0)
|
||||||
|
|
||||||
#define WREG_ATTR(reg, v) \
|
#define WREG_ATTR(reg, v) \
|
||||||
do { \
|
do { \
|
||||||
RREG8(0x1fda); \
|
RREG8(0x1fda); \
|
||||||
|
|||||||
@ -172,6 +172,8 @@ static int mgag200_g200_set_plls(struct mga_device *mdev, long clock)
|
|||||||
drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
|
drm_dbg_kms(dev, "clock: %ld vco: %ld m: %d n: %d p: %d s: %d\n",
|
||||||
clock, f_vco, m, n, p, s);
|
clock, f_vco, m, n, p, s);
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_M, m);
|
WREG_DAC(MGA1064_PIX_PLLC_M, m);
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_N, n);
|
WREG_DAC(MGA1064_PIX_PLLC_N, n);
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
|
WREG_DAC(MGA1064_PIX_PLLC_P, (p | (s << 3)));
|
||||||
@ -287,6 +289,8 @@ static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
|
|||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_M, m);
|
WREG_DAC(MGA1064_PIX_PLLC_M, m);
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_N, n);
|
WREG_DAC(MGA1064_PIX_PLLC_N, n);
|
||||||
WREG_DAC(MGA1064_PIX_PLLC_P, p);
|
WREG_DAC(MGA1064_PIX_PLLC_P, p);
|
||||||
@ -383,6 +387,8 @@ static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
||||||
if (i > 0) {
|
if (i > 0) {
|
||||||
WREG8(MGAREG_CRTC_INDEX, 0x1e);
|
WREG8(MGAREG_CRTC_INDEX, 0x1e);
|
||||||
@ -520,6 +526,8 @@ static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
||||||
tmp = RREG8(DAC_DATA);
|
tmp = RREG8(DAC_DATA);
|
||||||
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
||||||
@ -652,6 +660,9 @@ static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
for (i = 0; i <= 32 && pll_locked == false; i++) {
|
||||||
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
||||||
tmp = RREG8(DAC_DATA);
|
tmp = RREG8(DAC_DATA);
|
||||||
@ -752,6 +763,8 @@ static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
WREG_MISC_MASKED(MGAREG_MISC_CLKSEL_MGA, MGAREG_MISC_CLKSEL_MASK);
|
||||||
|
|
||||||
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
|
||||||
tmp = RREG8(DAC_DATA);
|
tmp = RREG8(DAC_DATA);
|
||||||
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
|
||||||
@ -785,8 +798,6 @@ static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
|
|||||||
|
|
||||||
static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
|
static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
|
||||||
{
|
{
|
||||||
u8 misc;
|
|
||||||
|
|
||||||
switch(mdev->type) {
|
switch(mdev->type) {
|
||||||
case G200_PCI:
|
case G200_PCI:
|
||||||
case G200_AGP:
|
case G200_AGP:
|
||||||
@ -811,11 +822,6 @@ static int mgag200_crtc_set_plls(struct mga_device *mdev, long clock)
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
|
||||||
misc = RREG8(MGA_MISC_IN);
|
|
||||||
misc &= ~MGAREG_MISC_CLK_SEL_MASK;
|
|
||||||
misc |= MGAREG_MISC_CLK_SEL_MGA_MSK;
|
|
||||||
WREG8(MGA_MISC_OUT, misc);
|
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user