Merge c0842fbc1b ("random32: move the pseudo-random 32-bit definitions to prandom.h") into android-mainline
Baby steps on the way to 5.9-rc1. Resolves merge issues with: arch/arm64/boot/dts/qcom/sdm845-db845c.dts drivers/soc/qcom/Kconfig kernel/sched/cpufreq_schedutil.c Signed-off-by: Greg Kroah-Hartman <gregkh@google.com> Change-Id: Ieb3344a22f9cf0d55ec5fc0daebe7602a248ab53
This commit is contained in:
Greg Kroah-Hartman
commit
075d0ec13d
1
.gitignore
vendored
1
.gitignore
vendored
@ -44,6 +44,7 @@
|
||||
*.tab.[ch]
|
||||
*.tar
|
||||
*.xz
|
||||
*.zst
|
||||
Module.symvers
|
||||
modules.builtin
|
||||
modules.order
|
||||
|
||||
@ -206,3 +206,20 @@ Description: This file exposes the firmware version of burnable voltage
|
||||
regulator devices.
|
||||
|
||||
The file is read only.
|
||||
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_pn
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_pn
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_pn
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_pn
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld1_version_min
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld2_version_min
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld3_version_min
|
||||
What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/cpld4_version_min
|
||||
Date: July 2020
|
||||
KernelVersion: 5.9
|
||||
Contact: Vadim Pasternak <vadimpmellanox.com>
|
||||
Description: These files show with which CPLD part numbers and minor
|
||||
versions have been burned CPLD devices equipped on a
|
||||
system.
|
||||
|
||||
The files are read only.
|
||||
|
||||
9
Documentation/ABI/testing/debugfs-turris-mox-rwtm
Normal file
9
Documentation/ABI/testing/debugfs-turris-mox-rwtm
Normal file
@ -0,0 +1,9 @@
|
||||
What: /sys/kernel/debug/turris-mox-rwtm/do_sign
|
||||
Date: Jun 2020
|
||||
KernelVersion: 5.8
|
||||
Contact: Marek Behún <marek.behun@nic.cz>
|
||||
Description: (W) Message to sign with the ECDSA private key stored in
|
||||
device's OTP. The message must be exactly 64 bytes (since
|
||||
this is intended for SHA-512 hashes).
|
||||
(R) The resulting signature, 136 bytes. This contains the R and
|
||||
S values of the ECDSA signature, both in big-endian format.
|
||||
8
Documentation/ABI/testing/sysfs-bus-optee-devices
Normal file
8
Documentation/ABI/testing/sysfs-bus-optee-devices
Normal file
@ -0,0 +1,8 @@
|
||||
What: /sys/bus/tee/devices/optee-ta-<uuid>/
|
||||
Date: May 2020
|
||||
KernelVersion 5.8
|
||||
Contact: op-tee@lists.trustedfirmware.org
|
||||
Description:
|
||||
OP-TEE bus provides reference to registered drivers under this directory. The <uuid>
|
||||
matches Trusted Application (TA) driver and corresponding TA in secure OS. Drivers
|
||||
are free to create needed API under optee-ta-<uuid> directory.
|
||||
@ -108,3 +108,15 @@ Description:
|
||||
frequency requested by governors and min_freq.
|
||||
The max_freq overrides min_freq because max_freq may be
|
||||
used to throttle devices to avoid overheating.
|
||||
|
||||
What: /sys/class/devfreq/.../timer
|
||||
Date: July 2020
|
||||
Contact: Chanwoo Choi <cw00.choi@samsung.com>
|
||||
Description:
|
||||
This ABI shows and stores the kind of work timer by users.
|
||||
This work timer is used by devfreq workqueue in order to
|
||||
monitor the device status such as utilization. The user
|
||||
can change the work timer on runtime according to their demand
|
||||
as following:
|
||||
echo deferrable > /sys/class/devfreq/.../timer
|
||||
echo delayed > /sys/class/devfreq/.../timer
|
||||
|
||||
@ -26,6 +26,30 @@ Description:
|
||||
Read-only attribute common to all SoCs. Contains SoC family name
|
||||
(e.g. DB8500).
|
||||
|
||||
On many of ARM based silicon with SMCCC v1.2+ compliant firmware
|
||||
this will contain the JEDEC JEP106 manufacturer’s identification
|
||||
code. The format is "jep106:XXYY" where XX is identity code and
|
||||
YY is continuation code.
|
||||
|
||||
This manufacturer’s identification code is defined by one
|
||||
or more eight (8) bit fields, each consisting of seven (7)
|
||||
data bits plus one (1) odd parity bit. It is a single field,
|
||||
limiting the possible number of vendors to 126. To expand
|
||||
the maximum number of identification codes, a continuation
|
||||
scheme has been defined.
|
||||
|
||||
The specified mechanism is that an identity code of 0x7F
|
||||
represents the "continuation code" and implies the presence
|
||||
of an additional identity code field, and this mechanism
|
||||
may be extended to multiple continuation codes followed
|
||||
by the manufacturer's identity code.
|
||||
|
||||
For example, ARM has identity code 0x7F 0x7F 0x7F 0x7F 0x3B,
|
||||
which is code 0x3B on the fifth 'page'. This is shortened
|
||||
as JEP106 identity code of 0x3B and a continuation code of
|
||||
0x4 to represent the four continuation codes preceding the
|
||||
identity code.
|
||||
|
||||
What: /sys/devices/socX/serial_number
|
||||
Date: January 2019
|
||||
contact: Bjorn Andersson <bjorn.andersson@linaro.org>
|
||||
@ -40,6 +64,12 @@ Description:
|
||||
Read-only attribute supported by most SoCs. In the case of
|
||||
ST-Ericsson's chips this contains the SoC serial number.
|
||||
|
||||
On many of ARM based silicon with SMCCC v1.2+ compliant firmware
|
||||
this will contain the SOC ID appended to the family attribute
|
||||
to ensure there is no conflict in this namespace across various
|
||||
vendors. The format is "jep106:XXYY:ZZZZ" where XX is identity
|
||||
code, YY is continuation code and ZZZZ is the SOC ID.
|
||||
|
||||
What: /sys/devices/socX/revision
|
||||
Date: January 2012
|
||||
contact: Lee Jones <lee.jones@linaro.org>
|
||||
|
||||
@ -703,6 +703,11 @@
|
||||
cpufreq.off=1 [CPU_FREQ]
|
||||
disable the cpufreq sub-system
|
||||
|
||||
cpufreq.default_governor=
|
||||
[CPU_FREQ] Name of the default cpufreq governor or
|
||||
policy to use. This governor must be registered in the
|
||||
kernel before the cpufreq driver probes.
|
||||
|
||||
cpu_init_udelay=N
|
||||
[X86] Delay for N microsec between assert and de-assert
|
||||
of APIC INIT to start processors. This delay occurs
|
||||
|
||||
@ -50,6 +50,7 @@ detailed description):
|
||||
- WAN enable and disable
|
||||
- UWB enable and disable
|
||||
- LCD Shadow (PrivacyGuard) enable and disable
|
||||
- Lap mode sensor
|
||||
|
||||
A compatibility table by model and feature is maintained on the web
|
||||
site, http://ibm-acpi.sf.net/. I appreciate any success or failure
|
||||
@ -1432,6 +1433,20 @@ The first command ensures the best viewing angle and the latter one turns
|
||||
on the feature, restricting the viewing angles.
|
||||
|
||||
|
||||
DYTC Lapmode sensor
|
||||
------------------
|
||||
|
||||
sysfs: dytc_lapmode
|
||||
|
||||
Newer thinkpads and mobile workstations have the ability to determine if
|
||||
the device is in deskmode or lapmode. This feature is used by user space
|
||||
to decide if WWAN transmission can be increased to maximum power and is
|
||||
also useful for understanding the different thermal modes available as
|
||||
they differ between desk and lap mode.
|
||||
|
||||
The property is read-only. If the platform doesn't have support the sysfs
|
||||
class is not created.
|
||||
|
||||
EXPERIMENTAL: UWB
|
||||
-----------------
|
||||
|
||||
@ -1470,6 +1485,23 @@ For more details about which buttons will appear depending on the mode, please
|
||||
review the laptop's user guide:
|
||||
http://www.lenovo.com/shop/americas/content/user_guides/x1carbon_2_ug_en.pdf
|
||||
|
||||
Battery charge control
|
||||
----------------------
|
||||
|
||||
sysfs attributes:
|
||||
/sys/class/power_supply/BAT*/charge_control_{start,end}_threshold
|
||||
|
||||
These two attributes are created for those batteries that are supported by the
|
||||
driver. They enable the user to control the battery charge thresholds of the
|
||||
given battery. Both values may be read and set. `charge_control_start_threshold`
|
||||
accepts an integer between 0 and 99 (inclusive); this value represents a battery
|
||||
percentage level, below which charging will begin. `charge_control_end_threshold`
|
||||
accepts an integer between 1 and 100 (inclusive); this value represents a battery
|
||||
percentage level, above which charging will stop.
|
||||
|
||||
The exact semantics of the attributes may be found in
|
||||
Documentation/ABI/testing/sysfs-class-power.
|
||||
|
||||
Multiple Commands, Module Parameters
|
||||
------------------------------------
|
||||
|
||||
|
||||
@ -147,9 +147,9 @@ CPUs in it.
|
||||
|
||||
The next major initialization step for a new policy object is to attach a
|
||||
scaling governor to it (to begin with, that is the default scaling governor
|
||||
determined by the kernel configuration, but it may be changed later
|
||||
via ``sysfs``). First, a pointer to the new policy object is passed to the
|
||||
governor's ``->init()`` callback which is expected to initialize all of the
|
||||
determined by the kernel command line or configuration, but it may be changed
|
||||
later via ``sysfs``). First, a pointer to the new policy object is passed to
|
||||
the governor's ``->init()`` callback which is expected to initialize all of the
|
||||
data structures necessary to handle the given policy and, possibly, to add
|
||||
a governor ``sysfs`` interface to it. Next, the governor is started by
|
||||
invoking its ``->start()`` callback.
|
||||
|
||||
@ -431,6 +431,17 @@ argument is passed to the kernel in the command line.
|
||||
supported in the current configuration, writes to this attribute will
|
||||
fail with an appropriate error.
|
||||
|
||||
``energy_efficiency``
|
||||
This attribute is only present on platforms, which have CPUs matching
|
||||
Kaby Lake or Coffee Lake desktop CPU model. By default
|
||||
energy efficiency optimizations are disabled on these CPU models in HWP
|
||||
mode by this driver. Enabling energy efficiency may limit maximum
|
||||
operating frequency in both HWP and non HWP mode. In non HWP mode,
|
||||
optimizations are done only in the turbo frequency range. In HWP mode,
|
||||
optimizations are done in the entire frequency range. Setting this
|
||||
attribute to "1" enables energy efficiency optimizations and setting
|
||||
to "0" disables energy efficiency optimizations.
|
||||
|
||||
Interpretation of Policy Attributes
|
||||
-----------------------------------
|
||||
|
||||
@ -554,7 +565,11 @@ somewhere between the two extremes:
|
||||
Strings written to the ``energy_performance_preference`` attribute are
|
||||
internally translated to integer values written to the processor's
|
||||
Energy-Performance Preference (EPP) knob (if supported) or its
|
||||
Energy-Performance Bias (EPB) knob.
|
||||
Energy-Performance Bias (EPB) knob. It is also possible to write a positive
|
||||
integer value between 0 to 255, if the EPP feature is present. If the EPP
|
||||
feature is not present, writing integer value to this attribute is not
|
||||
supported. In this case, user can use
|
||||
"/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.
|
||||
|
||||
[Note that tasks may by migrated from one CPU to another by the scheduler's
|
||||
load-balancing algorithm and if different energy vs performance hints are
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/al,alpine.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Annapurna Labs Alpine Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Tsahee Zidenberg <tsahee@annapurnalabs.com>
|
||||
- Antoine Tenart <antoine.tenart@bootlin.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: al,alpine
|
||||
model:
|
||||
items:
|
||||
- const: "Annapurna Labs Alpine Dev Board"
|
||||
|
||||
...
|
||||
33
Documentation/devicetree/bindings/arm/amazon,al.yaml
Normal file
33
Documentation/devicetree/bindings/arm/amazon,al.yaml
Normal file
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/amazon,al.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Amazon's Annapurna Labs Alpine Platform Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Hanna Hawa <hhhawa@amazon.com>
|
||||
- Talel Shenhar <talel@amazon.com>, <talelshenhar@gmail.com>
|
||||
- Ronen Krupnik <ronenk@amazon.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: Boards with Alpine V1 SoC
|
||||
items:
|
||||
- const: al,alpine
|
||||
|
||||
- description: Boards with Alpine V2 SoC
|
||||
items:
|
||||
- enum:
|
||||
- al,alpine-v2-evp
|
||||
- const: al,alpine-v2
|
||||
|
||||
- description: Boards with Alpine V3 SoC
|
||||
items:
|
||||
- enum:
|
||||
- amazon,al-alpine-v3-evp
|
||||
- const: amazon,al-alpine-v3
|
||||
|
||||
...
|
||||
@ -121,6 +121,7 @@ properties:
|
||||
- libretech,aml-s912-pc
|
||||
- nexbox,a1
|
||||
- tronsmart,vega-s96
|
||||
- wetek,core2
|
||||
- const: amlogic,s912
|
||||
- const: amlogic,meson-gxm
|
||||
|
||||
|
||||
@ -120,6 +120,8 @@ properties:
|
||||
- fsl,imx6q-sabrelite
|
||||
- fsl,imx6q-sabresd
|
||||
- kontron,imx6q-samx6i # Kontron i.MX6 Dual/Quad SMARC Module
|
||||
- prt,prti6q # Protonic PRTI6Q board
|
||||
- prt,prtwd2 # Protonic WD2 board
|
||||
- technexion,imx6q-pico-dwarf # TechNexion i.MX6Q Pico-Dwarf
|
||||
- technexion,imx6q-pico-hobbit # TechNexion i.MX6Q Pico-Hobbit
|
||||
- technexion,imx6q-pico-nymph # TechNexion i.MX6Q Pico-Nymph
|
||||
@ -172,6 +174,8 @@ properties:
|
||||
- fsl,imx6dl-sabreauto # i.MX6 DualLite/Solo SABRE Automotive Board
|
||||
- fsl,imx6dl-sabresd # i.MX6 DualLite SABRE Smart Device Board
|
||||
- kontron,imx6dl-samx6i # Kontron i.MX6 Solo SMARC Module
|
||||
- prt,prtrvt # Protonic RVT board
|
||||
- prt,prtvt7 # Protonic VT7 board
|
||||
- technexion,imx6dl-pico-dwarf # TechNexion i.MX6DL Pico-Dwarf
|
||||
- technexion,imx6dl-pico-hobbit # TechNexion i.MX6DL Pico-Hobbit
|
||||
- technexion,imx6dl-pico-nymph # TechNexion i.MX6DL Pico-Nymph
|
||||
@ -268,6 +272,7 @@ properties:
|
||||
- armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
|
||||
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
|
||||
- kontron,imx6ull-n6411-som # Kontron N6411 SOM
|
||||
- myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board
|
||||
- toradex,colibri-imx6ull-eval # Colibri iMX6ULL Module on Colibri Evaluation Board
|
||||
- toradex,colibri-imx6ull-wifi-eval # Colibri iMX6ULL Wi-Fi / Bluetooth Module on Colibri Evaluation Board
|
||||
- const: fsl,imx6ull
|
||||
|
||||
19
Documentation/devicetree/bindings/arm/intel,keembay.yaml
Normal file
19
Documentation/devicetree/bindings/arm/intel,keembay.yaml
Normal file
@ -0,0 +1,19 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/intel,keembay.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Keem Bay platform device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- intel,keembay-evm
|
||||
- const: intel,keembay
|
||||
...
|
||||
@ -114,4 +114,9 @@ properties:
|
||||
- enum:
|
||||
- mediatek,mt8183-evb
|
||||
- const: mediatek,mt8183
|
||||
- description: Google Krane (Lenovo IdeaPad Duet, 10e,...)
|
||||
items:
|
||||
- const: google,krane-sku176
|
||||
- const: google,krane
|
||||
- const: mediatek,mt8183
|
||||
...
|
||||
|
||||
65
Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
Normal file
65
Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
Normal file
@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip Sparx5 Boards Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
description: |+
|
||||
The Microchip Sparx5 SoC is a ARMv8-based used in a family of
|
||||
gigabit TSN-capable gigabit switches.
|
||||
|
||||
The SparX-5 Ethernet switch family provides a rich set of switching
|
||||
features such as advanced TCAM-based VLAN and QoS processing
|
||||
enabling delivery of differentiated services, and security through
|
||||
TCAM-based frame processing using versatile content aware processor
|
||||
(VCAP)
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: The Sparx5 pcb125 board is a modular board,
|
||||
which has both spi-nor and eMMC storage. The modular design
|
||||
allows for connection of different network ports.
|
||||
items:
|
||||
- const: microchip,sparx5-pcb125
|
||||
- const: microchip,sparx5
|
||||
|
||||
- description: The Sparx5 pcb134 is a pizzabox form factor
|
||||
gigabit switch with 20 SFP ports. It features spi-nor and
|
||||
either spi-nand or eMMC storage (mount option).
|
||||
items:
|
||||
- const: microchip,sparx5-pcb134
|
||||
- const: microchip,sparx5
|
||||
|
||||
- description: The Sparx5 pcb135 is a pizzabox form factor
|
||||
gigabit switch with 48+4 Cu ports. It features spi-nor and
|
||||
either spi-nand or eMMC storage (mount option).
|
||||
items:
|
||||
- const: microchip,sparx5-pcb135
|
||||
- const: microchip,sparx5
|
||||
|
||||
axi@600000000:
|
||||
type: object
|
||||
description: the root node in the Sparx5 platforms must contain
|
||||
an axi bus child node. They are always at physical address
|
||||
0x600000000 in all the Sparx5 variants.
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: simple-bus
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- axi@600000000
|
||||
|
||||
...
|
||||
@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
# Copyright 2020 thingy.jp.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: MStar/SigmaStar Armv7 SoC l3bridge
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
description: |
|
||||
MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
|
||||
between the CPU and memory. This means that before DMA capable
|
||||
devices are allowed to run the pipeline must be flushed to ensure
|
||||
everything is in memory.
|
||||
|
||||
The l3bridge region contains registers that allow such a flush
|
||||
to be triggered.
|
||||
|
||||
This node is used by the platform code to find where the registers
|
||||
are and install a barrier that triggers the required pipeline flush.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: mstar,l3bridge
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
l3bridge: l3bridge@1f204400 {
|
||||
compatible = "mstar,l3bridge";
|
||||
reg = <0x1f204400 0x200>;
|
||||
};
|
||||
33
Documentation/devicetree/bindings/arm/mstar/mstar.yaml
Normal file
33
Documentation/devicetree/bindings/arm/mstar/mstar.yaml
Normal file
@ -0,0 +1,33 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/arm/mstar/mstar.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MStar platforms device tree bindings
|
||||
|
||||
maintainers:
|
||||
- Daniel Palmer <daniel@thingy.jp>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
- description: infinity boards
|
||||
items:
|
||||
- enum:
|
||||
- thingyjp,breadbee-crust # thingy.jp BreadBee Crust
|
||||
- const: mstar,infinity
|
||||
|
||||
- description: infinity3 boards
|
||||
items:
|
||||
- enum:
|
||||
- thingyjp,breadbee # thingy.jp BreadBee
|
||||
- const: mstar,infinity3
|
||||
|
||||
- description: mercury5 boards
|
||||
items:
|
||||
- enum:
|
||||
- 70mai,midrived08 # 70mai midrive d08
|
||||
- const: mstar,mercury5
|
||||
@ -118,6 +118,7 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2m # HopeRun HiHope RZ/G2M platform
|
||||
- beacon,beacon-rzg2m # Beacon EmbeddedWorks RZ/G2M Kit
|
||||
- const: renesas,r8a774a1
|
||||
|
||||
- items:
|
||||
@ -150,6 +151,18 @@ properties:
|
||||
- const: si-linux,cat874
|
||||
- const: renesas,r8a774c0
|
||||
|
||||
- description: RZ/G2H (R8A774E1)
|
||||
items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2h # HopeRun HiHope RZ/G2H platform
|
||||
- const: renesas,r8a774e1
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
- hoperun,hihope-rzg2-ex # HopeRun expansion board for HiHope RZ/G2 platforms
|
||||
- const: hoperun,hihope-rzg2h
|
||||
- const: renesas,r8a774e1
|
||||
|
||||
- description: R-Car M1A (R8A77781)
|
||||
items:
|
||||
- enum:
|
||||
|
||||
@ -435,6 +435,12 @@ properties:
|
||||
- const: radxa,rockpi4
|
||||
- const: rockchip,rk3399
|
||||
|
||||
- description: Radxa ROCK Pi N8
|
||||
items:
|
||||
- const: radxa,rockpi-n8
|
||||
- const: vamrs,rk3288-vmarc-som
|
||||
- const: rockchip,rk3288
|
||||
|
||||
- description: Radxa ROCK Pi N10
|
||||
items:
|
||||
- const: radxa,rockpi-n10
|
||||
|
||||
@ -16,6 +16,9 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- st,stm32mp157-syscfg
|
||||
- st,stm32mp151-pwr-mcu
|
||||
- st,stm32-syscfg
|
||||
- st,stm32-power-config
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
@ -27,7 +30,16 @@ properties:
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- st,stm32mp157-syscfg
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
||||
@ -657,6 +657,11 @@ properties:
|
||||
- const: pine64,pinephone-1.1
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PinePhone (1.2)
|
||||
items:
|
||||
- const: pine64,pinephone-1.2
|
||||
- const: allwinner,sun50i-a64
|
||||
|
||||
- description: Pine64 PineTab
|
||||
items:
|
||||
- const: pine64,pinetab
|
||||
|
||||
@ -34,6 +34,9 @@ properties:
|
||||
- toradex,colibri_t20-iris
|
||||
- const: toradex,colibri_t20
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- const: acer,picasso
|
||||
- const: nvidia,tegra20
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,beaver
|
||||
@ -59,6 +62,13 @@ properties:
|
||||
- toradex,colibri_t30-eval-v3
|
||||
- const: toradex,colibri_t30
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,grouper
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- const: asus,tilapia
|
||||
- const: asus,grouper
|
||||
- const: nvidia,tegra30
|
||||
- items:
|
||||
- enum:
|
||||
- nvidia,dalmore
|
||||
@ -101,3 +111,11 @@ properties:
|
||||
- enum:
|
||||
- nvidia,p2972-0000
|
||||
- const: nvidia,tegra194
|
||||
- description: Jetson Xavier NX
|
||||
items:
|
||||
- const: nvidia,p3668-0000
|
||||
- const: nvidia,tegra194
|
||||
- description: Jetson Xavier NX Developer Kit
|
||||
items:
|
||||
- const: nvidia,p3509-0000+p3668-0000
|
||||
- const: nvidia,tegra194
|
||||
|
||||
@ -0,0 +1,52 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Microchip Sparx5 DPLL Clock
|
||||
|
||||
maintainers:
|
||||
- Lars Povlsen <lars.povlsen@microchip.com>
|
||||
|
||||
description: |
|
||||
The Sparx5 DPLL clock controller generates and supplies clock to
|
||||
various peripherals within the SoC.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: microchip,sparx5-dpll
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
# Clock provider for eMMC:
|
||||
- |
|
||||
lcpll_clk: lcpll-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2500000000>;
|
||||
};
|
||||
clks: clock-controller@61110000c {
|
||||
compatible = "microchip,sparx5-dpll";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&lcpll_clk>;
|
||||
reg = <0x1110000c 0x24>;
|
||||
};
|
||||
|
||||
...
|
||||
@ -18,6 +18,8 @@ Optional properties:
|
||||
format depends on the interrupt controller.
|
||||
It should be a DCF interrupt. When DDR DVFS finishes
|
||||
a DCF interrupt is triggered.
|
||||
- rockchip,pmu: Phandle to the syscon managing the "PMU general register
|
||||
files".
|
||||
|
||||
Following properties relate to DDR timing:
|
||||
|
||||
|
||||
@ -11,10 +11,12 @@ Required properties:
|
||||
* "qcom,scm-apq8084"
|
||||
* "qcom,scm-ipq4019"
|
||||
* "qcom,scm-ipq806x"
|
||||
* "qcom,scm-ipq8074"
|
||||
* "qcom,scm-msm8660"
|
||||
* "qcom,scm-msm8916"
|
||||
* "qcom,scm-msm8960"
|
||||
* "qcom,scm-msm8974"
|
||||
* "qcom,scm-msm8994"
|
||||
* "qcom,scm-msm8996"
|
||||
* "qcom,scm-msm8998"
|
||||
* "qcom,scm-sc7180"
|
||||
|
||||
@ -4,8 +4,9 @@ Required properties:
|
||||
- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30,
|
||||
must contain "nvidia,tegra30-efuse". For Tegra114, must contain
|
||||
"nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse".
|
||||
Otherwise, must contain "nvidia,<chip>-efuse", plus one of the above, where
|
||||
<chip> is tegra132.
|
||||
For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse".
|
||||
For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain
|
||||
"nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse".
|
||||
Details:
|
||||
nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data
|
||||
due to a hardware bug. Tegra20 also lacks certain information which is
|
||||
|
||||
@ -6,6 +6,7 @@ Required properties:
|
||||
- nvidia,gk20a
|
||||
- nvidia,gm20b
|
||||
- nvidia,gp10b
|
||||
- nvidia,gv11b
|
||||
- reg: Physical base address and length of the controller's registers.
|
||||
Must contain two entries:
|
||||
- first entry for bar0
|
||||
@ -25,6 +26,9 @@ Required properties:
|
||||
If the compatible string is "nvidia,gm20b", then the following clock
|
||||
is also required:
|
||||
- ref
|
||||
If the compatible string is "nvidia,gv11b", then the following clock is also
|
||||
required:
|
||||
- fuse
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
@ -88,3 +92,24 @@ Example for GP10B:
|
||||
power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
|
||||
iommus = <&smmu TEGRA186_SID_GPU>;
|
||||
};
|
||||
|
||||
Example for GV11B:
|
||||
|
||||
gpu@17000000 {
|
||||
compatible = "nvidia,gv11b";
|
||||
reg = <0x17000000 0x10000000>,
|
||||
<0x18000000 0x10000000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "stall", "nonstall";
|
||||
clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
|
||||
<&bpmp TEGRA194_CLK_GPU_PWR>,
|
||||
<&bpmp TEGRA194_CLK_FUSE>;
|
||||
clock-names = "gpu", "pwr", "fuse";
|
||||
resets = <&bpmp TEGRA194_RESET_GPU>;
|
||||
reset-names = "gpu";
|
||||
dma-coherent;
|
||||
|
||||
power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
|
||||
iommus = <&smmu TEGRA194_SID_GPU>;
|
||||
};
|
||||
|
||||
@ -35,12 +35,12 @@ Required properties:
|
||||
Due to above changes, Tegra114 I2C driver makes incompatible with
|
||||
previous hardware driver. Hence, tegra114 I2C controller is compatible
|
||||
with "nvidia,tegra114-i2c".
|
||||
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is part of the
|
||||
host1x domain and typically used for camera use-cases. This VI I2C
|
||||
controller is mostly compatible with the programming model of the
|
||||
regular I2C controllers with a few exceptions. The I2C registers start
|
||||
at an offset of 0xc00 (instead of 0), registers are 16 bytes apart
|
||||
(rather than 4) and the controller does not support slave mode.
|
||||
nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus
|
||||
and is part of VE power domain and typically used for camera use-cases.
|
||||
This VI I2C controller is mostly compatible with the programming model
|
||||
of the regular I2C controllers with a few exceptions. The I2C registers
|
||||
start at an offset of 0xc00 (instead of 0), registers are 16 bytes
|
||||
apart (rather than 4) and the controller does not support slave mode.
|
||||
- reg: Should contain I2C controller registers physical address and length.
|
||||
- interrupts: Should contain I2C controller interrupts.
|
||||
- address-cells: Address cells for I2C device address.
|
||||
@ -53,10 +53,17 @@ Required properties:
|
||||
- fast-clk
|
||||
Tegra114:
|
||||
- div-clk
|
||||
Tegra210:
|
||||
- div-clk
|
||||
- slow (only for nvidia,tegra210-i2c-vi compatible node)
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must include the following entries:
|
||||
- i2c
|
||||
- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must
|
||||
include venc powergate node as vi i2c is part of VE power domain.
|
||||
tegra210-i2c-vi:
|
||||
- pd_venc
|
||||
- dmas: Must contain an entry for each entry in clock-names.
|
||||
See ../dma/dma.txt for details.
|
||||
- dma-names: Must include the following entries:
|
||||
|
||||
@ -55,7 +55,7 @@ Required Properties:
|
||||
corresponds to a range of host irqs.
|
||||
|
||||
For more details on TISCI IRQ resource management refer:
|
||||
http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
|
||||
https://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
|
||||
|
||||
Example:
|
||||
--------
|
||||
|
||||
@ -0,0 +1,88 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas Reduced Pin Count Interface (RPC-IF)
|
||||
|
||||
maintainers:
|
||||
- Sergei Shtylyov <sergei.shtylyov@gmail.com>
|
||||
|
||||
description: |
|
||||
Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
|
||||
be accessed via the external address space read mode or the manual mode.
|
||||
|
||||
The flash chip itself should be represented by a subnode of the RPC-IF node.
|
||||
The flash interface is selected based on the "compatible" property of this
|
||||
subnode:
|
||||
- if it contains "jedec,spi-nor", then SPI is used;
|
||||
- if it contains "cfi-flash", then HyperFlash is used.
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r8a77970-rpc-if # R-Car V3M
|
||||
- renesas,r8a77980-rpc-if # R-Car V3H
|
||||
- renesas,r8a77995-rpc-if # R-Car D3
|
||||
- const: renesas,rcar-gen3-rpc-if # a generic R-Car gen3 device
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: RPC-IF registers
|
||||
- description: direct mapping read mode area
|
||||
- description: write buffer area
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: regs
|
||||
- const: dirmap
|
||||
- const: wbuf
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
patternProperties:
|
||||
"flash@[0-9a-f]+$":
|
||||
type: object
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- cfi-flash
|
||||
- jedec,spi-nor
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/renesas-cpg-mssr.h>
|
||||
#include <dt-bindings/power/r8a77995-sysc.h>
|
||||
|
||||
spi@ee200000 {
|
||||
compatible = "renesas,r8a77995-rpc-if", "renesas,rcar-gen3-rpc-if";
|
||||
reg = <0xee200000 0x200>,
|
||||
<0x08000000 0x4000000>,
|
||||
<0xee208000 0x100>;
|
||||
reg-names = "regs", "dirmap", "wbuf";
|
||||
clocks = <&cpg CPG_MOD 917>;
|
||||
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <1>;
|
||||
};
|
||||
};
|
||||
@ -38,6 +38,8 @@ properties:
|
||||
- allwinner,sun8i-h3-system-controller
|
||||
- allwinner,sun8i-v3s-system-controller
|
||||
- allwinner,sun50i-a64-system-controller
|
||||
- microchip,sparx5-cpu-syscon
|
||||
- mstar,msc313-pmsleep
|
||||
|
||||
- const: syscon
|
||||
|
||||
|
||||
@ -0,0 +1,74 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: TI J721e System Controller Registers R/W Device Tree Bindings
|
||||
|
||||
description: |
|
||||
This represents the Control Module registers (CTRL_MMR0) on the SoC.
|
||||
System controller node represents a register region containing a set
|
||||
of miscellaneous registers. The registers are not cohesive enough to
|
||||
represent as any specific type of device. The typical use-case is
|
||||
for some other node's driver, or platform-specific code, to acquire
|
||||
a reference to the syscon node (e.g. by phandle, node path, or
|
||||
search using a specific compatible value), interrogate the node (or
|
||||
associated OS driver) to determine the location of the registers,
|
||||
and access the registers directly.
|
||||
|
||||
maintainers:
|
||||
- Kishon Vijay Abraham I <kishon@ti.com>
|
||||
- Roger Quadros <rogerq@ti.com
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
anyOf:
|
||||
- items:
|
||||
- enum:
|
||||
- ti,j721e-system-controller
|
||||
- const: syscon
|
||||
- const: simple-mfd
|
||||
|
||||
"#address-cells":
|
||||
const: 1
|
||||
|
||||
"#size-cells":
|
||||
const: 1
|
||||
|
||||
ranges: true
|
||||
|
||||
# Optional children
|
||||
|
||||
"^serdes-ln-ctrl@[0-9a-f]+$":
|
||||
type: object
|
||||
description: |
|
||||
This is the SERDES lane control mux. It should follow the bindings
|
||||
specified in
|
||||
Documentation/devicetree/bindings/mux/reg-mux.txt
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#address-cells"
|
||||
- "#size-cells"
|
||||
- ranges
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
scm_conf: scm-conf@100000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00100000 0x1c000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
|
||||
compatible = "mmio-mux";
|
||||
reg = <0x00004080 0x50>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -25,6 +25,7 @@ properties:
|
||||
- renesas,r8a774a1-sysc # RZ/G2M
|
||||
- renesas,r8a774b1-sysc # RZ/G2N
|
||||
- renesas,r8a774c0-sysc # RZ/G2E
|
||||
- renesas,r8a774e1-sysc # RZ/G2H
|
||||
- renesas,r8a7779-sysc # R-Car H1
|
||||
- renesas,r8a7790-sysc # R-Car H2
|
||||
- renesas,r8a7791-sysc # R-Car M2-W
|
||||
|
||||
@ -15,6 +15,8 @@ Required properties:
|
||||
Optional properties:
|
||||
- enable-gpios: platform gpio for control of BUCKA/BUCKB.
|
||||
- Any optional property defined in regulator.txt
|
||||
- regulator-initial-mode and regulator-allowed-modes may be specified using
|
||||
mode values from dt-bindings/regulator/dlg,da9211-regulator.h
|
||||
|
||||
Example 1) DA9211
|
||||
pmic: da9211@68 {
|
||||
@ -30,6 +32,8 @@ Example 1) DA9211
|
||||
regulator-min-microamp = <2000000>;
|
||||
regulator-max-microamp = <5000000>;
|
||||
enable-gpios = <&gpio 27 0>;
|
||||
regulator-allowed-modes = <DA9211_BUCK_MODE_SYNC
|
||||
DA9211_BUCK_MODE_AUTO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/google,cros-ec-regulator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: ChromeOS EC controlled voltage regulators
|
||||
|
||||
maintainers:
|
||||
- Pi-Hsun Shih <pihsun@chromium.org>
|
||||
|
||||
description:
|
||||
Any property defined as part of the core regulator binding, defined in
|
||||
regulator.yaml, can also be used.
|
||||
|
||||
allOf:
|
||||
- $ref: "regulator.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: google,cros-ec-regulator
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: Identifier for the voltage regulator to ChromeOS EC.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cros_ec: ec@0 {
|
||||
compatible = "google,cros-ec-spi";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
regulator@0 {
|
||||
compatible = "google,cros-ec-regulator";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -37,8 +37,8 @@ Optional properties:
|
||||
(Documentation/devicetree/bindings/regulator/regulator.txt)
|
||||
|
||||
Datasheet
|
||||
- LP8720: http://www.ti.com/lit/ds/symlink/lp8720.pdf
|
||||
- LP8725: http://www.ti.com/lit/ds/symlink/lp8725.pdf
|
||||
- LP8720: https://www.ti.com/lit/ds/symlink/lp8720.pdf
|
||||
- LP8725: https://www.ti.com/lit/ds/symlink/lp8725.pdf
|
||||
|
||||
Example 1) LP8720
|
||||
|
||||
|
||||
@ -16,6 +16,9 @@ LDO:
|
||||
ldo_vemc3v3, ldo_vgp1, ldo_vgp2, ldo_vgp3, ldo_vgp4, ldo_vgp5, ldo_vgp6,
|
||||
ldo_vibr
|
||||
|
||||
BUCK regulators can set regulator-initial-mode and regulator-allowed-modes to
|
||||
values specified in dt-bindings/regulator/mediatek,mt6397-regulator.h
|
||||
|
||||
Example:
|
||||
pmic {
|
||||
compatible = "mediatek,mt6397";
|
||||
|
||||
@ -0,0 +1,190 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/nxp,pca9450-regulator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: NXP PCA9450A/B/C Power Management Integrated Circuit regulators
|
||||
|
||||
maintainers:
|
||||
- Robin Gong <yibin.gong@nxp.com>
|
||||
|
||||
description: |
|
||||
Regulator nodes should be named to BUCK_<number> and LDO_<number>. The
|
||||
definition for each of these nodes is defined using the standard
|
||||
binding for regulators at
|
||||
Documentation/devicetree/bindings/regulator/regulator.txt.
|
||||
Datasheet is available at
|
||||
https://www.nxp.com/docs/en/data-sheet/PCA9450DS.pdf
|
||||
|
||||
#The valid names for PCA9450 regulator nodes are:
|
||||
#BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6,
|
||||
#LDO1, LDO2, LDO3, LDO4, LDO5
|
||||
#Note: Buck3 removed on PCA9450B and connect with Buck1 on PCA9450C.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- nxp,pca9450a
|
||||
- nxp,pca9450b
|
||||
- nxp,pca9450c
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
description: |
|
||||
list of regulators provided by this controller
|
||||
|
||||
patternProperties:
|
||||
"^LDO[1-5]$":
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
description:
|
||||
Properties for single LDO regulator.
|
||||
|
||||
properties:
|
||||
regulator-name:
|
||||
pattern: "^LDO[1-5]$"
|
||||
description:
|
||||
should be "LDO1", ..., "LDO5"
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
"^BUCK[1-6]$":
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
description:
|
||||
Properties for single BUCK regulator.
|
||||
|
||||
properties:
|
||||
regulator-name:
|
||||
pattern: "^BUCK[1-6]$"
|
||||
description:
|
||||
should be "BUCK1", ..., "BUCK6"
|
||||
|
||||
nxp,dvs-run-voltage:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 600000
|
||||
maximum: 2187500
|
||||
description:
|
||||
PMIC default "RUN" state voltage in uV. Only Buck1~3 have such
|
||||
dvs(dynamic voltage scaling) property.
|
||||
|
||||
nxp,dvs-standby-voltage:
|
||||
$ref: "/schemas/types.yaml#/definitions/uint32"
|
||||
minimum: 600000
|
||||
maximum: 2187500
|
||||
description:
|
||||
PMIC default "STANDBY" state voltage in uV. Only Buck1~3 have such
|
||||
dvs(dynamic voltage scaling) property.
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- regulators
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pmic: pmic@25 {
|
||||
compatible = "nxp,pca9450b";
|
||||
reg = <0x25>;
|
||||
pinctrl-0 = <&pinctrl_pmic>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
regulators {
|
||||
buck1: BUCK1 {
|
||||
regulator-name = "BUCK1";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
};
|
||||
buck2: BUCK2 {
|
||||
regulator-name = "BUCK2";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <2187500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <3125>;
|
||||
nxp,dvs-run-voltage = <950000>;
|
||||
nxp,dvs-standby-voltage = <850000>;
|
||||
};
|
||||
buck4: BUCK4 {
|
||||
regulator-name = "BUCK4";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
buck5: BUCK5 {
|
||||
regulator-name = "BUCK5";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
buck6: BUCK6 {
|
||||
regulator-name = "BUCK6";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <3400000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: LDO1 {
|
||||
regulator-name = "LDO1";
|
||||
regulator-min-microvolt = <1600000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
ldo2: LDO2 {
|
||||
regulator-name = "LDO2";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
ldo3: LDO3 {
|
||||
regulator-name = "LDO3";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
ldo4: LDO4 {
|
||||
regulator-name = "LDO4";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
ldo5: LDO5 {
|
||||
regulator-name = "LDO5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,85 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/onnn,fan53880.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Onsemi FAN53880 PMIC
|
||||
|
||||
maintainers:
|
||||
- Christoph Fritz <chf.fritz@googlemail.com>
|
||||
|
||||
description: |
|
||||
The FAN53880 is an I2C porgrammable power management IC (PMIC)
|
||||
that contains a BUCK (step-down converter), four low dropouts (LDO)
|
||||
and one BOOST (step-up converter) output. It is designed for mobile
|
||||
power applications.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "pmic@[0-9a-f]{1,2}"
|
||||
compatible:
|
||||
enum:
|
||||
- onnn,fan53880
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
VIN12-supply:
|
||||
description: Input supply phandle(s) for LDO1 and LDO2
|
||||
|
||||
VIN3-supply:
|
||||
description: Input supply phandle(s) for LDO3
|
||||
|
||||
VIN4-supply:
|
||||
description: Input supply phandle(s) for LDO4
|
||||
|
||||
PVIN-supply:
|
||||
description: Input supply phandle(s) for BUCK and BOOST
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
description: |
|
||||
list of regulators provided by this controller, must be named
|
||||
after their hardware counterparts LDO[1-4], BUCK and BOOST
|
||||
|
||||
patternProperties:
|
||||
"^LDO[1-4]$":
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
|
||||
"^BUCK|BOOST$":
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- regulators
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pmic@35 {
|
||||
compatible = "onnn,fan53880";
|
||||
reg = <0x35>;
|
||||
|
||||
PVIN-supply = <&fixreg_example_vcc>;
|
||||
|
||||
regulators {
|
||||
BUCK {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,320 +0,0 @@
|
||||
QCOM SMD RPM REGULATOR
|
||||
|
||||
The Qualcomm RPM over SMD regulator is modelled as a subdevice of the RPM.
|
||||
Because SMD is used as the communication transport mechanism, the RPM resides as
|
||||
a subnode of the SMD. As such, the SMD-RPM regulator requires that the SMD and
|
||||
RPM nodes be present.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for
|
||||
information pertaining to the SMD node.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.txt for
|
||||
information regarding the RPM node.
|
||||
|
||||
== Regulator
|
||||
|
||||
Regulator nodes are identified by their compatible:
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,rpm-pm8841-regulators"
|
||||
"qcom,rpm-pm8916-regulators"
|
||||
"qcom,rpm-pm8941-regulators"
|
||||
"qcom,rpm-pm8950-regulators"
|
||||
"qcom,rpm-pm8994-regulators"
|
||||
"qcom,rpm-pm8998-regulators"
|
||||
"qcom,rpm-pma8084-regulators"
|
||||
"qcom,rpm-pmi8994-regulators"
|
||||
"qcom,rpm-pmi8998-regulators"
|
||||
"qcom,rpm-pms405-regulators"
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_s6-supply:
|
||||
- vdd_s7-supply:
|
||||
- vdd_s8-supply:
|
||||
Usage: optional (pm8841 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_l1_l2_l3-supply:
|
||||
- vdd_l4_l5_l6-supply:
|
||||
- vdd_l7-supply:
|
||||
- vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18-supply:
|
||||
Usage: optional (pm8916 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_s6-supply:
|
||||
- vdd_l1_l19-supply:
|
||||
- vdd_l2_l23-supply:
|
||||
- vdd_l3-supply:
|
||||
- vdd_l4_l5_l6_l7_l16-supply:
|
||||
- vdd_l8_l11_l12_l17_l22-supply:
|
||||
- vdd_l9_l10_l13_l14_l15_l18-supply:
|
||||
- vdd_l20-supply:
|
||||
- vdd_l21-supply:
|
||||
Usage: optional (pm8950 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_l1_l3-supply:
|
||||
- vdd_l2_lvs1_2_3-supply:
|
||||
- vdd_l4_l11-supply:
|
||||
- vdd_l5_l7-supply:
|
||||
- vdd_l6_l12_l14_l15-supply:
|
||||
- vdd_l8_l16_l18_l19-supply:
|
||||
- vdd_l9_l10_l17_l22-supply:
|
||||
- vdd_l13_l20_l23_l24-supply:
|
||||
- vdd_l21-supply:
|
||||
- vin_5vs-supply:
|
||||
Usage: optional (pm8941 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_s6-supply:
|
||||
- vdd_s7-supply:
|
||||
- vdd_s8-supply:
|
||||
- vdd_s9-supply:
|
||||
- vdd_s10-supply:
|
||||
- vdd_s11-supply:
|
||||
- vdd_s12-supply:
|
||||
- vdd_l1-supply:
|
||||
- vdd_l2_l26_l28-supply:
|
||||
- vdd_l3_l11-supply:
|
||||
- vdd_l4_l27_l31-supply:
|
||||
- vdd_l5_l7-supply:
|
||||
- vdd_l6_l12_l32-supply:
|
||||
- vdd_l5_l7-supply:
|
||||
- vdd_l8_l16_l30-supply:
|
||||
- vdd_l9_l10_l18_l22-supply:
|
||||
- vdd_l9_l10_l18_l22-supply:
|
||||
- vdd_l3_l11-supply:
|
||||
- vdd_l6_l12_l32-supply:
|
||||
- vdd_l13_l19_l23_l24-supply:
|
||||
- vdd_l14_l15-supply:
|
||||
- vdd_l14_l15-supply:
|
||||
- vdd_l8_l16_l30-supply:
|
||||
- vdd_l17_l29-supply:
|
||||
- vdd_l9_l10_l18_l22-supply:
|
||||
- vdd_l13_l19_l23_l24-supply:
|
||||
- vdd_l20_l21-supply:
|
||||
- vdd_l20_l21-supply:
|
||||
- vdd_l9_l10_l18_l22-supply:
|
||||
- vdd_l13_l19_l23_l24-supply:
|
||||
- vdd_l13_l19_l23_l24-supply:
|
||||
- vdd_l25-supply:
|
||||
- vdd_l2_l26_l28-supply:
|
||||
- vdd_l4_l27_l31-supply:
|
||||
- vdd_l2_l26_l28-supply:
|
||||
- vdd_l17_l29-supply:
|
||||
- vdd_l8_l16_l30-supply:
|
||||
- vdd_l4_l27_l31-supply:
|
||||
- vdd_l6_l12_l32-supply:
|
||||
- vdd_lvs1_2-supply:
|
||||
Usage: optional (pm8994 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_bst_byp-supply:
|
||||
Usage: optional (pmi8994 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_s6-supply:
|
||||
- vdd_s7-supply:
|
||||
- vdd_s8-supply:
|
||||
- vdd_s9-supply:
|
||||
- vdd_s10-supply:
|
||||
- vdd_s11-supply:
|
||||
- vdd_s12-supply:
|
||||
- vdd_s13-supply:
|
||||
- vdd_l1_l27-supply:
|
||||
- vdd_l20_l24-supply:
|
||||
- vdd_l26-supply:
|
||||
- vdd_l2_l8_l17-supply:
|
||||
- vdd_l3_l11-supply:
|
||||
- vdd_l4_l5-supply:
|
||||
- vdd_l6-supply:
|
||||
- vdd_l7_l12_l14_l15-supply:
|
||||
- vdd_l9-supply:
|
||||
- vdd_l10_l23_l25-supply:
|
||||
- vdd_l13_l19_l21-supply:
|
||||
- vdd_l16_l28-supply:
|
||||
- vdd_l18_l22-supply:
|
||||
- vdd_lvs1_lvs2-supply:
|
||||
Usage: optional (pmi8998 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_s6-supply:
|
||||
- vdd_s7-supply:
|
||||
- vdd_s8-supply:
|
||||
- vdd_s9-supply:
|
||||
- vdd_s10-supply:
|
||||
- vdd_s11-supply:
|
||||
- vdd_s12-supply:
|
||||
- vdd_l1_l11-supply:
|
||||
- vdd_l2_l3_l4_l27-supply:
|
||||
- vdd_l5_l7-supply:
|
||||
- vdd_l6_l12_l14_l15_l26-supply:
|
||||
- vdd_l8-supply:
|
||||
- vdd_l9_l10_l13_l20_l23_l24-supply:
|
||||
- vdd_l16_l25-supply:
|
||||
- vdd_l17-supply:
|
||||
- vdd_l18-supply:
|
||||
- vdd_l19-supply:
|
||||
- vdd_l21-supply:
|
||||
- vdd_l22-supply:
|
||||
Usage: optional (pma8084 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_bob-supply:
|
||||
Usage: optional (pmi8998 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
- vdd_s1-supply:
|
||||
- vdd_s2-supply:
|
||||
- vdd_s3-supply:
|
||||
- vdd_s4-supply:
|
||||
- vdd_s5-supply:
|
||||
- vdd_l1_l2-supply:
|
||||
- vdd_l3_l8-supply:
|
||||
- vdd_l4-supply:
|
||||
- vdd_l5_l6-supply:
|
||||
- vdd_l7-supply:
|
||||
- vdd_l3_l8-supply:
|
||||
- vdd_l9-supply:
|
||||
- vdd_l10_l11_l12_l13-supply:
|
||||
Usage: optional (pms405 only)
|
||||
Value type: <phandle>
|
||||
Definition: reference to regulator supplying the input pin, as
|
||||
described in the data sheet
|
||||
|
||||
The regulator node houses sub-nodes for each regulator within the device. Each
|
||||
sub-node is identified using the node's name, with valid values listed for each
|
||||
of the pmics below.
|
||||
|
||||
pm8841:
|
||||
s1, s2, s3, s4, s5, s6, s7, s8
|
||||
|
||||
pm8916:
|
||||
s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
|
||||
l14, l15, l16, l17, l18
|
||||
|
||||
pm8941:
|
||||
s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
|
||||
l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2,
|
||||
lvs3, 5vs1, 5vs2
|
||||
|
||||
pm8994:
|
||||
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
|
||||
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
|
||||
l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2
|
||||
|
||||
pm8998:
|
||||
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2, l3, l4,
|
||||
l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
|
||||
l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2
|
||||
|
||||
pma8084:
|
||||
s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3, l4, l5,
|
||||
l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20,
|
||||
l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
|
||||
|
||||
pmi8994:
|
||||
s1, s2, s3, boost-bypass
|
||||
|
||||
pmi8998:
|
||||
bob
|
||||
|
||||
pms405:
|
||||
s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12,
|
||||
l13
|
||||
|
||||
The content of each sub-node is defined by the standard binding for regulators -
|
||||
see regulator.txt.
|
||||
|
||||
= EXAMPLE
|
||||
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8974";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
pm8941-regulators {
|
||||
compatible = "qcom,rpm-pm8941-regulators";
|
||||
vdd_l13_l20_l23_l24-supply = <&pm8941_boost>;
|
||||
|
||||
pm8941_s3: s3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8941_boost: s4 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
pm8941_l20: l20 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -0,0 +1,108 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/qcom,smd-rpm-regulator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: QCOM SMD RPM REGULATOR
|
||||
|
||||
description:
|
||||
The Qualcomm RPM over SMD regulator is modelled as a subdevice of the RPM.
|
||||
Because SMD is used as the communication transport mechanism, the RPM
|
||||
resides as a subnode of the SMD. As such, the SMD-RPM regulator requires
|
||||
that the SMD and RPM nodes be present.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd.txt for
|
||||
information pertaining to the SMD node.
|
||||
|
||||
Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
|
||||
for information regarding the RPM node.
|
||||
|
||||
The regulator node houses sub-nodes for each regulator within the device.
|
||||
Each sub-node is identified using the node's name, with valid values listed
|
||||
for each of the pmics below.
|
||||
|
||||
For mp5496, s2
|
||||
|
||||
For pm8841, s1, s2, s3, s4, s5, s6, s7, s8
|
||||
|
||||
For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
|
||||
l12, l13, l14, l15, l16, l17, l18
|
||||
|
||||
For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
|
||||
l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2,
|
||||
lvs3, 5vs1, 5vs2
|
||||
|
||||
For pm8994, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
|
||||
l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
|
||||
l20, l21, l22, l23, l24, l25, l26, l27, l28, l29, l30, l31, l32, lvs1, lvs2
|
||||
|
||||
For pm8998, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, l1, l2,
|
||||
l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
|
||||
l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1, lvs2
|
||||
|
||||
For pma8084, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, l1, l2, l3,
|
||||
l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19,
|
||||
l20, l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
|
||||
|
||||
For pmi8994, s1, s2, s3, boost-bypass
|
||||
|
||||
For pmi8998, bob
|
||||
|
||||
For pms405, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
|
||||
l12, l13
|
||||
|
||||
maintainers:
|
||||
- Kathiravan T <kathirav@codeaurora.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,rpm-mp5496-regulators
|
||||
- qcom,rpm-pm8841-regulators
|
||||
- qcom,rpm-pm8916-regulators
|
||||
- qcom,rpm-pm8941-regulators
|
||||
- qcom,rpm-pm8950-regulators
|
||||
- qcom,rpm-pm8994-regulators
|
||||
- qcom,rpm-pm8998-regulators
|
||||
- qcom,rpm-pma8084-regulators
|
||||
- qcom,rpm-pmi8994-regulators
|
||||
- qcom,rpm-pmi8998-regulators
|
||||
- qcom,rpm-pms405-regulators
|
||||
|
||||
patternProperties:
|
||||
".*-supply$":
|
||||
description: Input supply phandle(s) for this node
|
||||
|
||||
"^((s|l|lvs|5vs)[0-9]*)|(boost-bypass)|(bob)$":
|
||||
description: List of regulators and its properties
|
||||
allOf:
|
||||
- $ref: regulator.yaml#
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
examples:
|
||||
- |
|
||||
pm8941-regulators {
|
||||
compatible = "qcom,rpm-pm8941-regulators";
|
||||
vdd_l13_l20_l23_l24-supply = <&pm8941_boost>;
|
||||
|
||||
pm8941_s3: s3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
pm8941_boost: s4 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
pm8941_l20: l20 {
|
||||
regulator-min-microvolt = <2950000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,41 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/qcom,usb-vbus-regulator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: The Qualcomm PMIC VBUS output regulator driver
|
||||
|
||||
maintainers:
|
||||
- Wesley Cheng <wcheng@codeaurora.org>
|
||||
|
||||
description: |
|
||||
This regulator driver controls the VBUS output by the Qualcomm PMIC. This
|
||||
regulator will be enabled in situations where the device is required to
|
||||
provide power to the connected peripheral.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,pm8150b-vbus-reg
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
description: VBUS output base address
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
pm8150b {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pm8150b_vbus: dcdc@1100 {
|
||||
compatible = "qcom,pm8150b-vbus-reg";
|
||||
reg = <0x1100>;
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -0,0 +1,70 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/qcom-labibb-regulator.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm's LAB(LCD AMOLED Boost)/IBB(Inverting Buck Boost) Regulator
|
||||
|
||||
maintainers:
|
||||
- Sumit Semwal <sumit.semwal@linaro.org>
|
||||
|
||||
description:
|
||||
LAB can be used as a positive boost power supply and IBB can be used as a
|
||||
negative boost power supply for display panels. Currently implemented for
|
||||
pmi8998.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: qcom,pmi8998-lab-ibb
|
||||
|
||||
lab:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description:
|
||||
Short-circuit interrupt for lab.
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
ibb:
|
||||
type: object
|
||||
|
||||
properties:
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
description:
|
||||
Short-circuit interrupt for lab.
|
||||
|
||||
required:
|
||||
- interrupts
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
labibb {
|
||||
compatible = "qcom,pmi8998-lab-ibb";
|
||||
|
||||
lab {
|
||||
interrupts = <0x3 0x0 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "sc-err";
|
||||
};
|
||||
|
||||
ibb {
|
||||
interrupts = <0x3 0x2 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "sc-err";
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/regulator/silergy,sy8827n.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: silergy sy8827n PMIC
|
||||
|
||||
maintainers:
|
||||
- Jisheng Zhang <jszhang@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- silergy,sy8827n
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
enable-gpios:
|
||||
description: GPIO to enable/disable the regulator.
|
||||
maxItems: 1
|
||||
|
||||
silergy,vsel-state-high:
|
||||
type: boolean
|
||||
description:
|
||||
Indicates if the VSEL pin is set to high.
|
||||
If this property is missing, assume the VSEL pin is set to low.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
examples:
|
||||
- |
|
||||
i2c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
regulator@60 {
|
||||
compatible = "silergy,sy8827n";
|
||||
reg = <0x60>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@ -1,49 +0,0 @@
|
||||
Freescale i.MX System Reset Controller
|
||||
======================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<chip>-src"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
|
||||
in this order.
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
example:
|
||||
|
||||
src: src@20d8000 {
|
||||
compatible = "fsl,imx6q-src";
|
||||
reg = <0x020d8000 0x4000>;
|
||||
interrupts = <0 91 0x04 0 96 0x04>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
The system reset controller can be used to reset the GPU, VPU,
|
||||
IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
|
||||
nodes should specify the reset line on the SRC in their resets
|
||||
property, containing a phandle to the SRC device node and a
|
||||
RESET_INDEX specifying which module to reset, as described in
|
||||
reset.txt
|
||||
|
||||
example:
|
||||
|
||||
ipu1: ipu@2400000 {
|
||||
resets = <&src 2>;
|
||||
};
|
||||
ipu2: ipu@2800000 {
|
||||
resets = <&src 4>;
|
||||
};
|
||||
|
||||
The following RESET_INDEX values are valid for i.MX5:
|
||||
GPU_RESET 0
|
||||
VPU_RESET 1
|
||||
IPU1_RESET 2
|
||||
OPEN_VG_RESET 3
|
||||
The following additional RESET_INDEX value is valid for i.MX6:
|
||||
IPU2_RESET 4
|
||||
82
Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
Normal file
82
Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
Normal file
@ -0,0 +1,82 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/fsl,imx-src.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX System Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Philipp Zabel <p.zabel@pengutronix.de>
|
||||
|
||||
description: |
|
||||
The system reset controller can be used to reset the GPU, VPU,
|
||||
IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
|
||||
nodes should specify the reset line on the SRC in their resets
|
||||
property, containing a phandle to the SRC device node and a
|
||||
RESET_INDEX specifying which module to reset, as described in
|
||||
reset.txt
|
||||
|
||||
The following RESET_INDEX values are valid for i.MX5:
|
||||
GPU_RESET 0
|
||||
VPU_RESET 1
|
||||
IPU1_RESET 2
|
||||
OPEN_VG_RESET 3
|
||||
The following additional RESET_INDEX value is valid for i.MX6:
|
||||
IPU2_RESET 4
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx50-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx53-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx6q-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx6sx-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx6sl-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx6ul-src"
|
||||
- const: "fsl,imx51-src"
|
||||
- items:
|
||||
- const: "fsl,imx6sll-src"
|
||||
- const: "fsl,imx51-src"
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: SRC interrupt
|
||||
- description: CPU WDOG interrupts out of SRC
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
reset-controller@73fd0000 {
|
||||
compatible = "fsl,imx51-src";
|
||||
reg = <0x73fd0000 0x4000>;
|
||||
interrupts = <75>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -1,56 +0,0 @@
|
||||
Freescale i.MX7 System Reset Controller
|
||||
======================================
|
||||
|
||||
Please also refer to reset.txt in this directory for common reset
|
||||
controller binding usage.
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
- For i.MX7 SoCs should be "fsl,imx7d-src", "syscon"
|
||||
- For i.MX8MQ SoCs should be "fsl,imx8mq-src", "syscon"
|
||||
- For i.MX8MM SoCs should be "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon"
|
||||
- For i.MX8MN SoCs should be "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon"
|
||||
- For i.MX8MP SoCs should be "fsl,imx8mp-src", "syscon"
|
||||
- reg: should be register base and length as documented in the
|
||||
datasheet
|
||||
- interrupts: Should contain SRC interrupt
|
||||
- #reset-cells: 1, see below
|
||||
|
||||
example:
|
||||
|
||||
src: reset-controller@30390000 {
|
||||
compatible = "fsl,imx7d-src", "syscon";
|
||||
reg = <0x30390000 0x2000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
|
||||
Specifying reset lines connected to IP modules
|
||||
==============================================
|
||||
|
||||
The system reset controller can be used to reset various set of
|
||||
peripherals. Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
Example:
|
||||
|
||||
pcie: pcie@33800000 {
|
||||
|
||||
...
|
||||
|
||||
resets = <&src IMX7_RESET_PCIEPHY>,
|
||||
<&src IMX7_RESET_PCIE_CTRL_APPS_EN>;
|
||||
reset-names = "pciephy", "apps";
|
||||
|
||||
...
|
||||
};
|
||||
|
||||
|
||||
For list of all valid reset indices see
|
||||
<dt-bindings/reset/imx7-reset.h> for i.MX7,
|
||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ and
|
||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MM and
|
||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MN and
|
||||
<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP
|
||||
58
Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml
Normal file
58
Documentation/devicetree/bindings/reset/fsl,imx7-src.yaml
Normal file
@ -0,0 +1,58 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale i.MX7 System Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Andrey Smirnov <andrew.smirnov@gmail.com>
|
||||
|
||||
description: |
|
||||
The system reset controller can be used to reset various set of
|
||||
peripherals. Device nodes that need access to reset lines should
|
||||
specify them as a reset phandle in their corresponding node as
|
||||
specified in reset.txt.
|
||||
|
||||
For list of all valid reset indices see
|
||||
<dt-bindings/reset/imx7-reset.h> for i.MX7,
|
||||
<dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN,
|
||||
<dt-bindings/reset/imx8mp-reset.h> for i.MX8MP.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- fsl,imx7d-src
|
||||
- fsl,imx8mq-src
|
||||
- fsl,imx8mp-src
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
reset-controller@30390000 {
|
||||
compatible = "fsl,imx7d-src", "syscon";
|
||||
reg = <0x30390000 0x2000>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
@ -31,6 +31,7 @@ properties:
|
||||
- renesas,r8a774a1-rst # RZ/G2M
|
||||
- renesas,r8a774b1-rst # RZ/G2N
|
||||
- renesas,r8a774c0-rst # RZ/G2E
|
||||
- renesas,r8a774e1-rst # RZ/G2H
|
||||
- renesas,r8a7778-reset-wdt # R-Car M1A
|
||||
- renesas,r8a7779-reset-wdt # R-Car H1
|
||||
- renesas,r8a7790-rst # R-Car H2
|
||||
|
||||
@ -1,7 +1,9 @@
|
||||
Atmel AT91SAM9260 Real Time Timer
|
||||
|
||||
Required properties:
|
||||
- compatible: should be: "atmel,at91sam9260-rtt"
|
||||
- compatible: should be one of the following:
|
||||
- "atmel,at91sam9260-rtt"
|
||||
- "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"
|
||||
- reg: should encode the memory region of the RTT controller
|
||||
- interrupts: rtt alarm/event interrupt
|
||||
- clocks: should contain the 32 KHz slow clk that will drive the RTT block.
|
||||
|
||||
@ -1,62 +0,0 @@
|
||||
Qualcomm Resource Power Manager (RPM) over SMD
|
||||
|
||||
This driver is used to interface with the Resource Power Manager (RPM) found in
|
||||
various Qualcomm platforms. The RPM allows each component in the system to vote
|
||||
for state of the system resources, such as clocks, regulators and bus
|
||||
frequencies.
|
||||
|
||||
The SMD information for the RPM edge should be filled out. See qcom,smd.txt for
|
||||
the required edge properties. All SMD related properties will reside within the
|
||||
RPM node itself.
|
||||
|
||||
= SUBDEVICES
|
||||
|
||||
The RPM exposes resources to its subnodes. The rpm_requests node must be
|
||||
present and this subnode may contain children that designate regulator
|
||||
resources.
|
||||
|
||||
- compatible:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be one of:
|
||||
"qcom,rpm-apq8084"
|
||||
"qcom,rpm-msm8916"
|
||||
"qcom,rpm-msm8974"
|
||||
"qcom,rpm-msm8976"
|
||||
"qcom,rpm-msm8998"
|
||||
"qcom,rpm-sdm660"
|
||||
"qcom,rpm-qcs404"
|
||||
|
||||
- qcom,smd-channels:
|
||||
Usage: required
|
||||
Value type: <string>
|
||||
Definition: must be "rpm_requests"
|
||||
|
||||
Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt
|
||||
for information on the regulator subnodes that can exist under the rpm_requests.
|
||||
|
||||
Example:
|
||||
|
||||
soc {
|
||||
apcs: syscon@f9011000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xf9011000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <0 168 1>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8974";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
87
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
Normal file
87
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
Normal file
@ -0,0 +1,87 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/qcom/qcom,smd-rpm.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Qualcomm Resource Power Manager (RPM) over SMD
|
||||
|
||||
description: |
|
||||
This driver is used to interface with the Resource Power Manager (RPM) found
|
||||
in various Qualcomm platforms. The RPM allows each component in the system
|
||||
to vote for state of the system resources, such as clocks, regulators and bus
|
||||
frequencies.
|
||||
|
||||
The SMD information for the RPM edge should be filled out. See qcom,smd.txt
|
||||
for the required edge properties. All SMD related properties will reside
|
||||
within the RPM node itself.
|
||||
|
||||
The RPM exposes resources to its subnodes. The rpm_requests node must be
|
||||
present and this subnode may contain children that designate regulator
|
||||
resources.
|
||||
|
||||
Refer to Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.txt
|
||||
for information on the regulator subnodes that can exist under the
|
||||
rpm_requests.
|
||||
|
||||
maintainers:
|
||||
- Kathiravan T <kathirav@codeaurora.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,rpm-apq8084
|
||||
- qcom,rpm-ipq6018
|
||||
- qcom,rpm-msm8916
|
||||
- qcom,rpm-msm8974
|
||||
- qcom,rpm-msm8976
|
||||
- qcom,rpm-msm8996
|
||||
- qcom,rpm-msm8998
|
||||
- qcom,rpm-sdm660
|
||||
- qcom,rpm-qcs404
|
||||
|
||||
qcom,smd-channels:
|
||||
$ref: /schemas/types.yaml#/definitions/string-array
|
||||
description: Channel name used for the RPM communication
|
||||
items:
|
||||
- const: rpm_requests
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,rpm-apq8084
|
||||
- qcom,rpm-msm8916
|
||||
- qcom,rpm-msm8974
|
||||
then:
|
||||
required:
|
||||
- qcom,smd-channels
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
smd {
|
||||
compatible = "qcom,smd";
|
||||
|
||||
rpm {
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
|
||||
qcom,ipc = <&apcs 8 0>;
|
||||
qcom,smd-edge = <15>;
|
||||
|
||||
rpm_requests {
|
||||
compatible = "qcom,rpm-msm8974";
|
||||
qcom,smd-channels = "rpm_requests";
|
||||
|
||||
/* Regulator nodes to follow */
|
||||
};
|
||||
};
|
||||
};
|
||||
...
|
||||
@ -1,59 +0,0 @@
|
||||
* Texas Instruments K3 NavigatorSS Ring Accelerator
|
||||
|
||||
The Ring Accelerator (RA) is a machine which converts read/write accesses
|
||||
from/to a constant address into corresponding read/write accesses from/to a
|
||||
circular data structure in memory. The RA eliminates the need for each DMA
|
||||
controller which needs to access ring elements from having to know the current
|
||||
state of the ring (base address, current offset). The DMA controller
|
||||
performs a read or write access to a specific address range (which maps to the
|
||||
source interface on the RA) and the RA replaces the address for the transaction
|
||||
with a new address which corresponds to the head or tail element of the ring
|
||||
(head for reads, tail for writes).
|
||||
|
||||
The Ring Accelerator is a hardware module that is responsible for accelerating
|
||||
management of the packet queues. The K3 SoCs can have more than one RA instances
|
||||
|
||||
Required properties:
|
||||
- compatible : Must be "ti,am654-navss-ringacc";
|
||||
- reg : Should contain register location and length of the following
|
||||
named register regions.
|
||||
- reg-names : should be
|
||||
"rt" - The RA Ring Real-time Control/Status Registers
|
||||
"fifos" - The RA Queues Registers
|
||||
"proxy_gcfg" - The RA Proxy Global Config Registers
|
||||
"proxy_target" - The RA Proxy Datapath Registers
|
||||
- ti,num-rings : Number of rings supported by RA
|
||||
- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range
|
||||
- ti,sci : phandle on TI-SCI compatible System controller node
|
||||
- ti,sci-dev-id : TI-SCI device id of the ring accelerator
|
||||
- msi-parent : phandle for "ti,sci-inta" interrupt controller
|
||||
|
||||
Optional properties:
|
||||
-- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability
|
||||
issue software w/a
|
||||
|
||||
Example:
|
||||
|
||||
ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos",
|
||||
"proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
};
|
||||
|
||||
client:
|
||||
|
||||
dma_ipx: dma_ipx@<addr> {
|
||||
...
|
||||
ti,ringacc = <&ringacc>;
|
||||
...
|
||||
}
|
||||
102
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
Normal file
102
Documentation/devicetree/bindings/soc/ti/k3-ringacc.yaml
Normal file
@ -0,0 +1,102 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Texas Instruments K3 NavigatorSS Ring Accelerator
|
||||
|
||||
maintainers:
|
||||
- Santosh Shilimkar <ssantosh@kernel.org>
|
||||
- Grygorii Strashko <grygorii.strashko@ti.com>
|
||||
|
||||
description: |
|
||||
The Ring Accelerator (RA) is a machine which converts read/write accesses
|
||||
from/to a constant address into corresponding read/write accesses from/to a
|
||||
circular data structure in memory. The RA eliminates the need for each DMA
|
||||
controller which needs to access ring elements from having to know the current
|
||||
state of the ring (base address, current offset). The DMA controller
|
||||
performs a read or write access to a specific address range (which maps to the
|
||||
source interface on the RA) and the RA replaces the address for the transaction
|
||||
with a new address which corresponds to the head or tail element of the ring
|
||||
(head for reads, tail for writes).
|
||||
|
||||
The Ring Accelerator is a hardware module that is responsible for accelerating
|
||||
management of the packet queues. The K3 SoCs can have more than one RA instances
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: ti,am654-navss-ringacc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: real time registers regions
|
||||
- description: fifos registers regions
|
||||
- description: proxy gcfg registers regions
|
||||
- description: proxy target registers regions
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: rt
|
||||
- const: fifos
|
||||
- const: proxy_gcfg
|
||||
- const: proxy_target
|
||||
|
||||
msi-parent: true
|
||||
|
||||
ti,num-rings:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: Number of rings supported by RA
|
||||
|
||||
ti,sci-rm-range-gp-rings:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: TI-SCI RM subtype for GP ring range
|
||||
|
||||
ti,sci:
|
||||
$ref: /schemas/types.yaml#definitions/phandle-array
|
||||
description: phandle on TI-SCI compatible System controller node
|
||||
|
||||
ti,sci-dev-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: TI-SCI device id of the ring accelerator
|
||||
|
||||
ti,dma-ring-reset-quirk:
|
||||
$ref: /schemas/types.yaml#definitions/flag
|
||||
description: |
|
||||
enable ringacc/udma ring state interoperability issue software w/a
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- msi-parent
|
||||
- ti,num-rings
|
||||
- ti,sci-rm-range-gp-rings
|
||||
- ti,sci
|
||||
- ti,sci-dev-id
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
bus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
ringacc: ringacc@3c000000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x0 0x3c000000 0x0 0x400000>,
|
||||
<0x0 0x38000000 0x0 0x400000>,
|
||||
<0x0 0x31120000 0x0 0x100>,
|
||||
<0x0 0x33000000 0x0 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <818>;
|
||||
ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
|
||||
ti,dma-ring-reset-quirk;
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <187>;
|
||||
msi-parent = <&inta_main_udmass>;
|
||||
};
|
||||
};
|
||||
@ -1,56 +0,0 @@
|
||||
* Freescale (Enhanced) Configurable Serial Peripheral Interface
|
||||
(CSPI/eCSPI) for i.MX
|
||||
|
||||
Required properties:
|
||||
- compatible :
|
||||
- "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
|
||||
- "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
|
||||
- "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
|
||||
- "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
|
||||
- "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
|
||||
- "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
|
||||
- "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc
|
||||
- "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8MQ
|
||||
- "fsl,imx8mm-ecspi" for SPI compatible with the one integrated on i.MX8MM
|
||||
- "fsl,imx8mn-ecspi" for SPI compatible with the one integrated on i.MX8MN
|
||||
- "fsl,imx8mp-ecspi" for SPI compatible with the one integrated on i.MX8MP
|
||||
- reg : Offset and length of the register set for the device
|
||||
- interrupts : Should contain CSPI/eCSPI interrupt
|
||||
- clocks : Clock specifiers for both ipg and per clocks.
|
||||
- clock-names : Clock names should include both "ipg" and "per"
|
||||
See the clock consumer binding,
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Recommended properties:
|
||||
- cs-gpios : GPIOs to use as chip selects, see spi-bus.txt. While the native chip
|
||||
select lines can be used, they appear to always generate a pulse between each
|
||||
word of a transfer. Most use cases will require GPIO based chip selects to
|
||||
generate a valid transaction.
|
||||
|
||||
Optional properties:
|
||||
- num-cs : Number of total chip selects, see spi-bus.txt.
|
||||
- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
|
||||
Documentation/devicetree/bindings/dma/dma.txt.
|
||||
- dma-names: DMA request names, if present, should include "tx" and "rx".
|
||||
- fsl,spi-rdy-drctl: Integer, representing the value of DRCTL, the register
|
||||
controlling the SPI_READY handling. Note that to enable the DRCTL consideration,
|
||||
the SPI_READY mode-flag needs to be set too.
|
||||
Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
|
||||
|
||||
Obsolete properties:
|
||||
- fsl,spi-num-chipselects : Contains the number of the chipselect
|
||||
|
||||
Example:
|
||||
|
||||
ecspi@70010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x70010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */
|
||||
<&gpio3 25 0>; /* GPIO3_25 */
|
||||
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
fsl,spi-rdy-drctl = <1>;
|
||||
};
|
||||
97
Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml
Normal file
97
Documentation/devicetree/bindings/spi/fsl-imx-cspi.yaml
Normal file
@ -0,0 +1,97 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale (Enhanced) Configurable Serial Peripheral Interface (CSPI/eCSPI) for i.MX
|
||||
|
||||
maintainers:
|
||||
- Shawn Guo <shawn.guo@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: fsl,imx1-cspi
|
||||
- const: fsl,imx21-cspi
|
||||
- const: fsl,imx27-cspi
|
||||
- const: fsl,imx31-cspi
|
||||
- const: fsl,imx35-cspi
|
||||
- const: fsl,imx51-ecspi
|
||||
- const: fsl,imx53-ecspi
|
||||
- items:
|
||||
- enum:
|
||||
- fsl,imx50-ecspi
|
||||
- fsl,imx6q-ecspi
|
||||
- fsl,imx6sx-ecspi
|
||||
- fsl,imx6sl-ecspi
|
||||
- fsl,imx6sll-ecspi
|
||||
- fsl,imx6ul-ecspi
|
||||
- fsl,imx7d-ecspi
|
||||
- fsl,imx8mq-ecspi
|
||||
- fsl,imx8mm-ecspi
|
||||
- fsl,imx8mn-ecspi
|
||||
- fsl,imx8mp-ecspi
|
||||
- const: fsl,imx51-ecspi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: SoC SPI ipg clock
|
||||
- description: SoC SPI per clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ipg
|
||||
- const: per
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: DMA controller phandle and request line for RX
|
||||
- description: DMA controller phandle and request line for TX
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: rx
|
||||
- const: tx
|
||||
|
||||
fsl,spi-rdy-drctl:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Integer, representing the value of DRCTL, the register controlling
|
||||
the SPI_READY handling. Note that to enable the DRCTL consideration,
|
||||
the SPI_READY mode-flag needs to be set too.
|
||||
Valid values are: 0 (disabled), 1 (edge-triggered burst) and 2 (level-triggered burst).
|
||||
enum: [0, 1, 2]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx5-clock.h>
|
||||
|
||||
spi@70010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx51-ecspi";
|
||||
reg = <0x70010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
|
||||
<&clks IMX5_CLK_ECSPI1_PER_GATE>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
@ -1,26 +0,0 @@
|
||||
* Freescale MX233/MX28 SSP/SPI
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be "fsl,<soc>-spi", where soc is "imx23" or "imx28"
|
||||
- reg: Offset and length of the register set for the device
|
||||
- interrupts: Should contain SSP ERROR interrupt
|
||||
- dmas: DMA specifier, consisting of a phandle to DMA controller node
|
||||
and SSP DMA channel ID.
|
||||
Refer to dma.txt and fsl-mxs-dma.txt for details.
|
||||
- dma-names: Must be "rx-tx".
|
||||
|
||||
Optional properties:
|
||||
- clock-frequency : Input clock frequency to the SPI block in Hz.
|
||||
Default is 160000000 Hz.
|
||||
|
||||
Example:
|
||||
|
||||
ssp0: ssp@80010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <96>;
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
56
Documentation/devicetree/bindings/spi/mxs-spi.yaml
Normal file
56
Documentation/devicetree/bindings/spi/mxs-spi.yaml
Normal file
@ -0,0 +1,56 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/mxs-spi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale MX233/MX28 SSP/SPI
|
||||
|
||||
maintainers:
|
||||
- Marek Vasut <marex@denx.de>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx23-spi
|
||||
- fsl,imx28-spi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
maxItems: 1
|
||||
|
||||
dma-names:
|
||||
const: rx-tx
|
||||
|
||||
clock-frequency:
|
||||
description: input clock frequency to the SPI block in Hz.
|
||||
default: 160000000
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- dmas
|
||||
- dma-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
spi@80010000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,imx28-spi";
|
||||
reg = <0x80010000 0x2000>;
|
||||
interrupts = <96>;
|
||||
dmas = <&dma_apbh 0>;
|
||||
dma-names = "rx-tx";
|
||||
};
|
||||
@ -21,6 +21,7 @@ properties:
|
||||
# device
|
||||
- items:
|
||||
- enum:
|
||||
- renesas,msiof-r8a7742 # RZ/G1H
|
||||
- renesas,msiof-r8a7743 # RZ/G1M
|
||||
- renesas,msiof-r8a7744 # RZ/G1N
|
||||
- renesas,msiof-r8a7745 # RZ/G1E
|
||||
@ -37,6 +38,7 @@ properties:
|
||||
- renesas,msiof-r8a774a1 # RZ/G2M
|
||||
- renesas,msiof-r8a774b1 # RZ/G2N
|
||||
- renesas,msiof-r8a774c0 # RZ/G2E
|
||||
- renesas,msiof-r8a774e1 # RZ/G2H
|
||||
- renesas,msiof-r8a7795 # R-Car H3
|
||||
- renesas,msiof-r8a7796 # R-Car M3-W
|
||||
- renesas,msiof-r8a77965 # R-Car M3-N
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
Davinci SPI controller device bindings
|
||||
|
||||
Links on DM:
|
||||
Keystone 2 - http://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
|
||||
dm644x - http://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
|
||||
Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
|
||||
dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
|
||||
OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
|
||||
|
||||
Required properties:
|
||||
|
||||
@ -1,29 +0,0 @@
|
||||
* Freescale Low Power SPI (LPSPI) for i.MX
|
||||
|
||||
Required properties:
|
||||
- compatible :
|
||||
- "fsl,imx7ulp-spi" for LPSPI compatible with the one integrated on i.MX7ULP soc
|
||||
- "fsl,imx8qxp-spi" for LPSPI compatible with the one integrated on i.MX8QXP soc
|
||||
- reg : address and length of the lpspi master registers
|
||||
- interrupt-parent : core interrupt controller
|
||||
- interrupts : lpspi interrupt
|
||||
- clocks : lpspi clock specifier. Its number and order need to correspond to the
|
||||
value in clock-names.
|
||||
- clock-names : Corresponding to per clock and ipg clock in "clocks"
|
||||
respectively. In i.MX7ULP, it only has per clk, so use CLK_DUMMY
|
||||
to fill the "ipg" blank.
|
||||
- spi-slave : spi slave mode support. In slave mode, add this attribute without
|
||||
value. In master mode, remove it.
|
||||
|
||||
Examples:
|
||||
|
||||
lpspi2: lpspi@40290000 {
|
||||
compatible = "fsl,imx7ulp-spi";
|
||||
reg = <0x40290000 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPSPI2>,
|
||||
<&clks IMX7ULP_CLK_DUMMY>;
|
||||
clock-names = "per", "ipg";
|
||||
spi-slave;
|
||||
};
|
||||
67
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
Normal file
67
Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
Normal file
@ -0,0 +1,67 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Freescale Low Power SPI (LPSPI) for i.MX
|
||||
|
||||
maintainers:
|
||||
- Anson Huang <Anson.Huang@nxp.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "/schemas/spi/spi-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,imx7ulp-spi
|
||||
- fsl,imx8qxp-spi
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: SoC SPI per clock
|
||||
- description: SoC SPI ipg clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: per
|
||||
- const: ipg
|
||||
|
||||
fsl,spi-only-use-cs1-sel:
|
||||
description:
|
||||
spi common code does not support use of CS signals discontinuously.
|
||||
i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
|
||||
this property to re-config the chipselect value in the LPSPI driver.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/imx7ulp-clock.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
spi@40290000 {
|
||||
compatible = "fsl,imx7ulp-spi";
|
||||
reg = <0x40290000 0x10000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX7ULP_CLK_LPSPI2>,
|
||||
<&clks IMX7ULP_CLK_DUMMY>;
|
||||
clock-names = "per", "ipg";
|
||||
spi-slave;
|
||||
fsl,spi-only-use-cs1-sel;
|
||||
};
|
||||
@ -1,11 +1,17 @@
|
||||
Lantiq Synchronous Serial Controller (SSC) SPI master driver
|
||||
|
||||
Required properties:
|
||||
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
|
||||
- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
|
||||
"intel,lgm-spi"
|
||||
- #address-cells: see spi-bus.txt
|
||||
- #size-cells: see spi-bus.txt
|
||||
- reg: address and length of the spi master registers
|
||||
- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
|
||||
- interrupts:
|
||||
For compatible "intel,lgm-ssc" - the common interrupt number for
|
||||
all of tx rx & err interrupts.
|
||||
or
|
||||
For rest of the compatibles, should contain the "spi_rx", "spi_tx" and
|
||||
"spi_err" interrupt.
|
||||
|
||||
|
||||
Optional properties:
|
||||
@ -27,3 +33,14 @@ spi: spi@e100800 {
|
||||
num-cs = <6>;
|
||||
base-cs = <1>;
|
||||
};
|
||||
|
||||
ssc0: spi@e0800000 {
|
||||
compatible = "intel,lgm-spi";
|
||||
reg = <0xe0800000 0x400>;
|
||||
interrupt-parent = <&ioapic1>;
|
||||
interrupts = <35 1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&cgu0 LGM_CLK_NGI>, <&cgu0 LGM_GCLK_SSC0>;
|
||||
clock-names = "freq", "gate";
|
||||
};
|
||||
|
||||
@ -11,6 +11,7 @@ Required properties:
|
||||
- mediatek,mt8135-spi: for mt8135 platforms
|
||||
- mediatek,mt8173-spi: for mt8173 platforms
|
||||
- mediatek,mt8183-spi: for mt8183 platforms
|
||||
- "mediatek,mt8192-spi", "mediatek,mt6765-spi": for mt8192 platforms
|
||||
- "mediatek,mt8516-spi", "mediatek,mt2712-spi": for mt8516 platforms
|
||||
|
||||
- #address-cells: should be 1.
|
||||
|
||||
@ -40,6 +40,8 @@ properties:
|
||||
- qcom,msm8998-tsens
|
||||
- qcom,sc7180-tsens
|
||||
- qcom,sdm845-tsens
|
||||
- qcom,sm8150-tsens
|
||||
- qcom,sm8250-tsens
|
||||
- const: qcom,tsens-v2
|
||||
|
||||
reg:
|
||||
|
||||
@ -44,7 +44,9 @@ properties:
|
||||
- const: st,stm32f4x9-hsotg
|
||||
- const: st,stm32f7-hsotg
|
||||
- const: st,stm32mp15-fsotg
|
||||
- const: st,stm32mp15-hsotg
|
||||
- items:
|
||||
- const: st,stm32mp15-hsotg
|
||||
- const: snps,dwc2
|
||||
- const: samsung,s3c6400-hsotg
|
||||
|
||||
reg:
|
||||
@ -93,7 +95,7 @@ properties:
|
||||
vusb_a-supply:
|
||||
description: phandle to voltage regulator of analog section.
|
||||
|
||||
vusb33d-supply:
|
||||
usb33d-supply:
|
||||
description: reference to the VBUS and ID sensing comparators supply, in
|
||||
order to perform OTG operation, used on STM32MP15 SoCs.
|
||||
|
||||
|
||||
@ -23,10 +23,14 @@ patternProperties:
|
||||
"^(simple-audio-card|simple-graph-card|st-plgpio|st-spics|ts),.*": true
|
||||
|
||||
# Keep list in alphabetical order.
|
||||
"^70mai,.*":
|
||||
description: 70mai Co., Ltd.
|
||||
"^abilis,.*":
|
||||
description: Abilis Systems
|
||||
"^abracon,.*":
|
||||
description: Abracon Corporation
|
||||
"^acer,.*":
|
||||
description: Acer Inc.
|
||||
"^acme,.*":
|
||||
description: Acme Systems srl
|
||||
"^actions,.*":
|
||||
@ -680,6 +684,8 @@ patternProperties:
|
||||
description: Microsemi Corporation
|
||||
"^msi,.*":
|
||||
description: Micro-Star International Co. Ltd.
|
||||
"^mstar,.*":
|
||||
description: MStar Semiconductor, Inc. (acquired by MediaTek Inc.)
|
||||
"^mti,.*":
|
||||
description: Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
|
||||
"^multi-inno,.*":
|
||||
@ -984,6 +990,8 @@ patternProperties:
|
||||
description: Spreadtrum Communications Inc.
|
||||
"^sst,.*":
|
||||
description: Silicon Storage Technology, Inc.
|
||||
"^sstar,.*":
|
||||
description: Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.)
|
||||
"^st,.*":
|
||||
description: STMicroelectronics
|
||||
"^starry,.*":
|
||||
@ -1032,6 +1040,8 @@ patternProperties:
|
||||
description: Three Five Corp
|
||||
"^thine,.*":
|
||||
description: THine Electronics, Inc.
|
||||
"^thingyjp,.*":
|
||||
description: thingy.jp
|
||||
"^ti,.*":
|
||||
description: Texas Instruments
|
||||
"^tianma,.*":
|
||||
|
||||
@ -55,6 +55,7 @@
|
||||
*.ver
|
||||
*.xml
|
||||
*.xz
|
||||
*.zst
|
||||
*_MODULES
|
||||
*_vga16.c
|
||||
*~
|
||||
|
||||
@ -96,5 +96,5 @@ contents.
|
||||
References
|
||||
==========
|
||||
|
||||
.. [1] http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf
|
||||
.. [2] http://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf
|
||||
.. [1] https://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf
|
||||
.. [2] https://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf
|
||||
|
||||
@ -85,9 +85,9 @@ References
|
||||
==========
|
||||
|
||||
[1] Hierarchical Data Extension UUID For _DSD.
|
||||
<http://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf>,
|
||||
<https://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf>,
|
||||
referenced 2018-07-17.
|
||||
|
||||
[2] Device Properties UUID For _DSD.
|
||||
<http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf>,
|
||||
<https://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf>,
|
||||
referenced 2016-10-04.
|
||||
|
||||
@ -154,23 +154,23 @@ References
|
||||
==========
|
||||
|
||||
[1] _DSD (Device Specific Data) Implementation Guide.
|
||||
http://www.uefi.org/sites/default/files/resources/_DSD-implementation-guide-toplevel-1_1.htm,
|
||||
https://www.uefi.org/sites/default/files/resources/_DSD-implementation-guide-toplevel-1_1.htm,
|
||||
referenced 2016-10-03.
|
||||
|
||||
[2] Devicetree. http://www.devicetree.org, referenced 2016-10-03.
|
||||
[2] Devicetree. https://www.devicetree.org, referenced 2016-10-03.
|
||||
|
||||
[3] Documentation/devicetree/bindings/graph.txt
|
||||
|
||||
[4] Device Properties UUID For _DSD.
|
||||
http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf,
|
||||
https://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf,
|
||||
referenced 2016-10-04.
|
||||
|
||||
[5] Hierarchical Data Extension UUID For _DSD.
|
||||
http://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf,
|
||||
https://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf,
|
||||
referenced 2016-10-04.
|
||||
|
||||
[6] Advanced Configuration and Power Interface Specification.
|
||||
http://www.uefi.org/sites/default/files/resources/ACPI_6_1.pdf,
|
||||
https://www.uefi.org/sites/default/files/resources/ACPI_6_1.pdf,
|
||||
referenced 2016-10-04.
|
||||
|
||||
[7] _DSD Device Properties Usage Rules.
|
||||
|
||||
@ -90,7 +90,7 @@ where
|
||||
References
|
||||
==========
|
||||
|
||||
[1] Device tree. <URL:http://www.devicetree.org>, referenced 2019-02-21.
|
||||
[1] Device tree. <URL:https://www.devicetree.org>, referenced 2019-02-21.
|
||||
|
||||
[2] Advanced Configuration and Power Interface Specification.
|
||||
<URL:https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf>,
|
||||
@ -101,11 +101,11 @@ References
|
||||
[4] Documentation/devicetree/bindings/media/video-interfaces.txt
|
||||
|
||||
[5] Device Properties UUID For _DSD.
|
||||
<URL:http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf>,
|
||||
<URL:https://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf>,
|
||||
referenced 2019-02-21.
|
||||
|
||||
[6] Hierarchical Data Extension UUID For _DSD.
|
||||
<URL:http://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf>,
|
||||
<URL:https://www.uefi.org/sites/default/files/resources/_DSD-hierarchical-data-extension-UUID-v1.1.pdf>,
|
||||
referenced 2019-02-21.
|
||||
|
||||
[7] Documentation/firmware-guide/acpi/dsd/data-node-references.rst
|
||||
|
||||
@ -7,7 +7,7 @@ Low Power Idle Table (LPIT)
|
||||
To enumerate platform Low Power Idle states, Intel platforms are using
|
||||
“Low Power Idle Table” (LPIT). More details about this table can be
|
||||
downloaded from:
|
||||
http://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
|
||||
https://www.uefi.org/sites/default/files/resources/Intel_ACPI_Low_Power_S0_Idle.pdf
|
||||
|
||||
Residencies for each low power state can be read via FFH
|
||||
(Function fixed hardware) or a memory mapped interface.
|
||||
|
||||
@ -9,7 +9,7 @@ Supported systems:
|
||||
|
||||
Prefix: 'power_meter'
|
||||
|
||||
Datasheet: http://acpi.info/, section 10.4.
|
||||
Datasheet: https://uefi.org/specifications, section 10.4.
|
||||
|
||||
Author: Darrick J. Wong
|
||||
|
||||
|
||||
@ -1,15 +1,17 @@
|
||||
====================
|
||||
Energy Model of CPUs
|
||||
====================
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=======================
|
||||
Energy Model of devices
|
||||
=======================
|
||||
|
||||
1. Overview
|
||||
-----------
|
||||
|
||||
The Energy Model (EM) framework serves as an interface between drivers knowing
|
||||
the power consumed by CPUs at various performance levels, and the kernel
|
||||
the power consumed by devices at various performance levels, and the kernel
|
||||
subsystems willing to use that information to make energy-aware decisions.
|
||||
|
||||
The source of the information about the power consumed by CPUs can vary greatly
|
||||
The source of the information about the power consumed by devices can vary greatly
|
||||
from one platform to another. These power costs can be estimated using
|
||||
devicetree data in some cases. In others, the firmware will know better.
|
||||
Alternatively, userspace might be best positioned. And so on. In order to avoid
|
||||
@ -25,7 +27,7 @@ framework, and interested clients reading the data from it::
|
||||
+---------------+ +-----------------+ +---------------+
|
||||
| Thermal (IPA) | | Scheduler (EAS) | | Other |
|
||||
+---------------+ +-----------------+ +---------------+
|
||||
| | em_pd_energy() |
|
||||
| | em_cpu_energy() |
|
||||
| | em_cpu_get() |
|
||||
+---------+ | +---------+
|
||||
| | |
|
||||
@ -35,7 +37,7 @@ framework, and interested clients reading the data from it::
|
||||
| Framework |
|
||||
+---------------------+
|
||||
^ ^ ^
|
||||
| | | em_register_perf_domain()
|
||||
| | | em_dev_register_perf_domain()
|
||||
+----------+ | +---------+
|
||||
| | |
|
||||
+---------------+ +---------------+ +--------------+
|
||||
@ -47,12 +49,12 @@ framework, and interested clients reading the data from it::
|
||||
| Device Tree | | Firmware | | ? |
|
||||
+--------------+ +---------------+ +--------------+
|
||||
|
||||
The EM framework manages power cost tables per 'performance domain' in the
|
||||
system. A performance domain is a group of CPUs whose performance is scaled
|
||||
together. Performance domains generally have a 1-to-1 mapping with CPUFreq
|
||||
policies. All CPUs in a performance domain are required to have the same
|
||||
micro-architecture. CPUs in different performance domains can have different
|
||||
micro-architectures.
|
||||
In case of CPU devices the EM framework manages power cost tables per
|
||||
'performance domain' in the system. A performance domain is a group of CPUs
|
||||
whose performance is scaled together. Performance domains generally have a
|
||||
1-to-1 mapping with CPUFreq policies. All CPUs in a performance domain are
|
||||
required to have the same micro-architecture. CPUs in different performance
|
||||
domains can have different micro-architectures.
|
||||
|
||||
|
||||
2. Core APIs
|
||||
@ -70,14 +72,16 @@ CONFIG_ENERGY_MODEL must be enabled to use the EM framework.
|
||||
Drivers are expected to register performance domains into the EM framework by
|
||||
calling the following API::
|
||||
|
||||
int em_register_perf_domain(cpumask_t *span, unsigned int nr_states,
|
||||
struct em_data_callback *cb);
|
||||
int em_dev_register_perf_domain(struct device *dev, unsigned int nr_states,
|
||||
struct em_data_callback *cb, cpumask_t *cpus);
|
||||
|
||||
Drivers must specify the CPUs of the performance domains using the cpumask
|
||||
argument, and provide a callback function returning <frequency, power> tuples
|
||||
for each capacity state. The callback function provided by the driver is free
|
||||
Drivers must provide a callback function returning <frequency, power> tuples
|
||||
for each performance state. The callback function provided by the driver is free
|
||||
to fetch data from any relevant location (DT, firmware, ...), and by any mean
|
||||
deemed necessary. See Section 3. for an example of driver implementing this
|
||||
deemed necessary. Only for CPU devices, drivers must specify the CPUs of the
|
||||
performance domains using cpumask. For other devices than CPUs the last
|
||||
argument must be set to NULL.
|
||||
See Section 3. for an example of driver implementing this
|
||||
callback, and kernel/power/energy_model.c for further documentation on this
|
||||
API.
|
||||
|
||||
@ -85,13 +89,20 @@ API.
|
||||
2.3 Accessing performance domains
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
There are two API functions which provide the access to the energy model:
|
||||
em_cpu_get() which takes CPU id as an argument and em_pd_get() with device
|
||||
pointer as an argument. It depends on the subsystem which interface it is
|
||||
going to use, but in case of CPU devices both functions return the same
|
||||
performance domain.
|
||||
|
||||
Subsystems interested in the energy model of a CPU can retrieve it using the
|
||||
em_cpu_get() API. The energy model tables are allocated once upon creation of
|
||||
the performance domains, and kept in memory untouched.
|
||||
|
||||
The energy consumed by a performance domain can be estimated using the
|
||||
em_pd_energy() API. The estimation is performed assuming that the schedutil
|
||||
CPUfreq governor is in use.
|
||||
em_cpu_energy() API. The estimation is performed assuming that the schedutil
|
||||
CPUfreq governor is in use in case of CPU device. Currently this calculation is
|
||||
not provided for other type of devices.
|
||||
|
||||
More details about the above APIs can be found in include/linux/energy_model.h.
|
||||
|
||||
@ -106,42 +117,46 @@ EM framework::
|
||||
|
||||
-> drivers/cpufreq/foo_cpufreq.c
|
||||
|
||||
01 static int est_power(unsigned long *mW, unsigned long *KHz, int cpu)
|
||||
02 {
|
||||
03 long freq, power;
|
||||
04
|
||||
05 /* Use the 'foo' protocol to ceil the frequency */
|
||||
06 freq = foo_get_freq_ceil(cpu, *KHz);
|
||||
07 if (freq < 0);
|
||||
08 return freq;
|
||||
09
|
||||
10 /* Estimate the power cost for the CPU at the relevant freq. */
|
||||
11 power = foo_estimate_power(cpu, freq);
|
||||
12 if (power < 0);
|
||||
13 return power;
|
||||
14
|
||||
15 /* Return the values to the EM framework */
|
||||
16 *mW = power;
|
||||
17 *KHz = freq;
|
||||
18
|
||||
19 return 0;
|
||||
20 }
|
||||
21
|
||||
22 static int foo_cpufreq_init(struct cpufreq_policy *policy)
|
||||
23 {
|
||||
24 struct em_data_callback em_cb = EM_DATA_CB(est_power);
|
||||
25 int nr_opp, ret;
|
||||
26
|
||||
27 /* Do the actual CPUFreq init work ... */
|
||||
28 ret = do_foo_cpufreq_init(policy);
|
||||
29 if (ret)
|
||||
30 return ret;
|
||||
31
|
||||
32 /* Find the number of OPPs for this policy */
|
||||
33 nr_opp = foo_get_nr_opp(policy);
|
||||
34
|
||||
35 /* And register the new performance domain */
|
||||
36 em_register_perf_domain(policy->cpus, nr_opp, &em_cb);
|
||||
37
|
||||
38 return 0;
|
||||
39 }
|
||||
01 static int est_power(unsigned long *mW, unsigned long *KHz,
|
||||
02 struct device *dev)
|
||||
03 {
|
||||
04 long freq, power;
|
||||
05
|
||||
06 /* Use the 'foo' protocol to ceil the frequency */
|
||||
07 freq = foo_get_freq_ceil(dev, *KHz);
|
||||
08 if (freq < 0);
|
||||
09 return freq;
|
||||
10
|
||||
11 /* Estimate the power cost for the dev at the relevant freq. */
|
||||
12 power = foo_estimate_power(dev, freq);
|
||||
13 if (power < 0);
|
||||
14 return power;
|
||||
15
|
||||
16 /* Return the values to the EM framework */
|
||||
17 *mW = power;
|
||||
18 *KHz = freq;
|
||||
19
|
||||
20 return 0;
|
||||
21 }
|
||||
22
|
||||
23 static int foo_cpufreq_init(struct cpufreq_policy *policy)
|
||||
24 {
|
||||
25 struct em_data_callback em_cb = EM_DATA_CB(est_power);
|
||||
26 struct device *cpu_dev;
|
||||
27 int nr_opp, ret;
|
||||
28
|
||||
29 cpu_dev = get_cpu_device(cpumask_first(policy->cpus));
|
||||
30
|
||||
31 /* Do the actual CPUFreq init work ... */
|
||||
32 ret = do_foo_cpufreq_init(policy);
|
||||
33 if (ret)
|
||||
34 return ret;
|
||||
35
|
||||
36 /* Find the number of OPPs for this policy */
|
||||
37 nr_opp = foo_get_nr_opp(policy);
|
||||
38
|
||||
39 /* And register the new performance domain */
|
||||
40 em_dev_register_perf_domain(cpu_dev, nr_opp, &em_cb, policy->cpus);
|
||||
41
|
||||
42 return 0;
|
||||
43 }
|
||||
|
||||
@ -167,11 +167,13 @@ For example::
|
||||
package-0
|
||||
---------
|
||||
|
||||
The Intel RAPL technology allows two constraints, short term and long term,
|
||||
with two different time windows to be applied to each power zone. Thus for
|
||||
each zone there are 2 attributes representing the constraint names, 2 power
|
||||
limits and 2 attributes representing the sizes of the time windows. Such that,
|
||||
constraint_j_* attributes correspond to the jth constraint (j = 0,1).
|
||||
Depending on different power zones, the Intel RAPL technology allows
|
||||
one or multiple constraints like short term, long term and peak power,
|
||||
with different time windows to be applied to each power zone.
|
||||
All the zones contain attributes representing the constraint names,
|
||||
power limits and the sizes of the time windows. Note that time window
|
||||
is not applicable to peak power. Here, constraint_j_* attributes
|
||||
correspond to the jth constraint (j = 0,1,2).
|
||||
|
||||
For example::
|
||||
|
||||
@ -181,6 +183,9 @@ For example::
|
||||
constraint_1_name
|
||||
constraint_1_power_limit_uw
|
||||
constraint_1_time_window_us
|
||||
constraint_2_name
|
||||
constraint_2_power_limit_uw
|
||||
constraint_2_time_window_us
|
||||
|
||||
Power Zone Attributes
|
||||
=====================
|
||||
|
||||
@ -6,7 +6,7 @@ Supported chips:
|
||||
|
||||
* NXP SI18IS602/602B/603
|
||||
|
||||
Datasheet: http://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf
|
||||
Datasheet: https://www.nxp.com/documents/data_sheet/SC18IS602_602B_603.pdf
|
||||
|
||||
Author:
|
||||
Guenter Roeck <linux@roeck-us.net>
|
||||
|
||||
@ -782,9 +782,9 @@ Protocol: 2.08+
|
||||
uncompressed data should be determined using the standard magic
|
||||
numbers. The currently supported compression formats are gzip
|
||||
(magic numbers 1F 8B or 1F 9E), bzip2 (magic number 42 5A), LZMA
|
||||
(magic number 5D 00), XZ (magic number FD 37), and LZ4 (magic number
|
||||
02 21). The uncompressed payload is currently always ELF (magic
|
||||
number 7F 45 4C 46).
|
||||
(magic number 5D 00), XZ (magic number FD 37), LZ4 (magic number
|
||||
02 21) and ZSTD (magic number 28 B5). The uncompressed payload is
|
||||
currently always ELF (magic number 7F 45 4C 46).
|
||||
|
||||
============ ==============
|
||||
Field name: payload_length
|
||||
|
||||
57
MAINTAINERS
57
MAINTAINERS
@ -1606,6 +1606,9 @@ F: sound/soc/meson/
|
||||
|
||||
ARM/Amlogic Meson SoC support
|
||||
M: Kevin Hilman <khilman@baylibre.com>
|
||||
R: Neil Armstrong <narmstrong@baylibre.com>
|
||||
R: Jerome Brunet <jbrunet@baylibre.com>
|
||||
R: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Maintained
|
||||
@ -1626,7 +1629,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/boot/dts/alpine*
|
||||
F: arch/arm/mach-alpine/
|
||||
F: arch/arm64/boot/dts/al/
|
||||
F: arch/arm64/boot/dts/amazon/
|
||||
F: drivers/*/*alpine*
|
||||
|
||||
ARM/ARTPEC MACHINE SUPPORT
|
||||
@ -1963,6 +1966,14 @@ F: drivers/irqchip/irq-ixp4xx.c
|
||||
F: include/linux/irqchip/irq-ixp4xx.h
|
||||
F: include/linux/platform_data/timer-ixp4xx.h
|
||||
|
||||
ARM/INTEL KEEMBAY ARCHITECTURE
|
||||
M: Paul J. Murphy <paul.j.murphy@intel.com>
|
||||
M: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/arm/intel,keembay.yaml
|
||||
F: arch/arm64/boot/dts/intel/keembay-evm.dts
|
||||
F: arch/arm64/boot/dts/intel/keembay-soc.dtsi
|
||||
|
||||
ARM/INTEL RESEARCH IMOTE/STARGATE 2 MACHINE SUPPORT
|
||||
M: Jonathan Cameron <jic23@cam.ac.uk>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
@ -2120,12 +2131,32 @@ X: drivers/net/wireless/atmel/
|
||||
N: at91
|
||||
N: atmel
|
||||
|
||||
ARM/Microchip Sparx5 SoC support
|
||||
M: Lars Povlsen <lars.povlsen@microchip.com>
|
||||
M: Steen Hegelund <Steen.Hegelund@microchip.com>
|
||||
M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
F: arch/arm64/boot/dts/microchip/
|
||||
N: sparx5
|
||||
|
||||
ARM/MIOA701 MACHINE SUPPORT
|
||||
M: Robert Jarzmik <robert.jarzmik@free.fr>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-pxa/mioa701.c
|
||||
|
||||
ARM/MStar/Sigmastar Armv7 SoC support
|
||||
M: Daniel Palmer <daniel@thingy.jp>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
W: http://linux-chenxing.org/
|
||||
F: Documentation/devicetree/bindings/arm/mstar/*
|
||||
F: arch/arm/boot/dts/infinity*.dtsi
|
||||
F: arch/arm/boot/dts/mercury*.dtsi
|
||||
F: arch/arm/boot/dts/mstar-v7.dtsi
|
||||
F: arch/arm/mach-mstar/
|
||||
|
||||
ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT
|
||||
M: Michael Petchkovsky <mkpetch@internode.on.net>
|
||||
S: Maintained
|
||||
@ -8617,6 +8648,12 @@ L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/intel_atomisp2_pm.c
|
||||
|
||||
INTEL ATOMISP2 LED DRIVER
|
||||
M: Hans de Goede <hdegoede@redhat.com>
|
||||
L: platform-driver-x86@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/platform/x86/intel_atomisp2_led.c
|
||||
|
||||
INTEL BROXTON PMC DRIVER
|
||||
M: Mika Westerberg <mika.westerberg@linux.intel.com>
|
||||
M: Zha Qipeng <qipeng.zha@intel.com>
|
||||
@ -11115,6 +11152,23 @@ F: Documentation/core-api/boot-time-mm.rst
|
||||
F: include/linux/memblock.h
|
||||
F: mm/memblock.c
|
||||
|
||||
MEMORY CONTROLLER DRIVERS
|
||||
M: Krzysztof Kozlowski <krzk@kernel.org>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git
|
||||
F: Documentation/devicetree/bindings/memory-controllers/
|
||||
F: drivers/memory/
|
||||
|
||||
MEMORY FREQUENCY SCALING DRIVERS FOR NVIDIA TEGRA
|
||||
M: Dmitry Osipenko <digetx@gmail.com>
|
||||
L: linux-pm@vger.kernel.org
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
|
||||
S: Maintained
|
||||
F: drivers/devfreq/tegra20-devfreq.c
|
||||
F: drivers/devfreq/tegra30-devfreq.c
|
||||
|
||||
MEMORY MANAGEMENT
|
||||
M: Andrew Morton <akpm@linux-foundation.org>
|
||||
L: linux-mm@kvack.org
|
||||
@ -12733,6 +12787,7 @@ OP-TEE DRIVER
|
||||
M: Jens Wiklander <jens.wiklander@linaro.org>
|
||||
L: op-tee@lists.trustedfirmware.org
|
||||
S: Maintained
|
||||
F: Documentation/ABI/testing/sysfs-bus-optee-devices
|
||||
F: drivers/tee/optee/
|
||||
|
||||
OP-TEE RANDOM NUMBER GENERATOR (RNG) DRIVER
|
||||
|
||||
3
Makefile
3
Makefile
@ -464,6 +464,7 @@ KLZOP = lzop
|
||||
LZMA = lzma
|
||||
LZ4 = lz4
|
||||
XZ = xz
|
||||
ZSTD = zstd
|
||||
|
||||
CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
|
||||
-Wbitwise -Wno-return-void -Wno-unknown-attribute $(CF)
|
||||
@ -512,7 +513,7 @@ CLANG_FLAGS :=
|
||||
export ARCH SRCARCH CONFIG_SHELL BASH HOSTCC KBUILD_HOSTCFLAGS CROSS_COMPILE LD CC
|
||||
export CPP AR NM STRIP OBJCOPY OBJDUMP OBJSIZE READELF PAHOLE LEX YACC AWK INSTALLKERNEL
|
||||
export PERL PYTHON PYTHON3 CHECK CHECKFLAGS MAKE UTS_MACHINE HOSTCXX
|
||||
export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ
|
||||
export KGZIP KBZIP2 KLZOP LZMA LZ4 XZ ZSTD
|
||||
export KBUILD_HOSTCXXFLAGS KBUILD_HOSTLDFLAGS KBUILD_HOSTLDLIBS LDFLAGS_MODULE
|
||||
|
||||
export KBUILD_CPPFLAGS NOSTDINC_FLAGS LINUXINCLUDE OBJCOPYFLAGS KBUILD_LDFLAGS
|
||||
|
||||
@ -668,6 +668,8 @@ source "arch/arm/mach-mmp/Kconfig"
|
||||
|
||||
source "arch/arm/mach-moxart/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mstar/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mv78xx0/Kconfig"
|
||||
|
||||
source "arch/arm/mach-mvebu/Kconfig"
|
||||
|
||||
@ -197,6 +197,7 @@ machine-$(CONFIG_ARCH_MXC) += imx
|
||||
machine-$(CONFIG_ARCH_MEDIATEK) += mediatek
|
||||
machine-$(CONFIG_ARCH_MILBEAUT) += milbeaut
|
||||
machine-$(CONFIG_ARCH_MXS) += mxs
|
||||
machine-$(CONFIG_ARCH_MSTARV7) += mstar
|
||||
machine-$(CONFIG_ARCH_NOMADIK) += nomadik
|
||||
machine-$(CONFIG_ARCH_NPCM) += npcm
|
||||
machine-$(CONFIG_ARCH_NSPIRE) += nspire
|
||||
|
||||
@ -455,6 +455,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6dl-pico-hobbit.dtb \
|
||||
imx6dl-pico-nymph.dtb \
|
||||
imx6dl-pico-pi.dtb \
|
||||
imx6dl-prtrvt.dtb \
|
||||
imx6dl-prtvt7.dtb \
|
||||
imx6dl-rex-basic.dtb \
|
||||
imx6dl-riotboard.dtb \
|
||||
imx6dl-sabreauto.dtb \
|
||||
@ -543,6 +545,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
|
||||
imx6q-pico-nymph.dtb \
|
||||
imx6q-pico-pi.dtb \
|
||||
imx6q-pistachio.dtb \
|
||||
imx6q-prti6q.dtb \
|
||||
imx6q-prtwd2.dtb \
|
||||
imx6q-rex-pro.dtb \
|
||||
imx6q-sabreauto.dtb \
|
||||
imx6q-sabrelite.dtb \
|
||||
@ -592,6 +596,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \
|
||||
imx6sx-sdb-reva.dtb \
|
||||
imx6sx-sdb-sai.dtb \
|
||||
imx6sx-sdb.dtb \
|
||||
imx6sx-sdb-mqs.dtb \
|
||||
imx6sx-softing-vining-2000.dtb \
|
||||
imx6sx-udoo-neo-basic.dtb \
|
||||
imx6sx-udoo-neo-extended.dtb \
|
||||
@ -617,6 +622,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
|
||||
imx6ull-14x14-evk.dtb \
|
||||
imx6ull-colibri-eval-v3.dtb \
|
||||
imx6ull-colibri-wifi-eval-v3.dtb \
|
||||
imx6ull-myir-mys-6ulx-eval.dtb \
|
||||
imx6ull-opos6uldev.dtb \
|
||||
imx6ull-phytec-segin-ff-rdk-nand.dtb \
|
||||
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
|
||||
@ -890,6 +896,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
qcom-ipq8064-rb3011.dtb \
|
||||
qcom-msm8660-surf.dtb \
|
||||
qcom-msm8960-cdp.dtb \
|
||||
qcom-msm8974-fairphone-fp2.dtb \
|
||||
@ -927,6 +934,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
|
||||
r8a73a4-ape6evm.dtb \
|
||||
r8a7740-armadillo800eva.dtb \
|
||||
r8a7742-iwg21d-q7.dtb \
|
||||
r8a7742-iwg21d-q7-dbcm-ca.dtb \
|
||||
r8a7743-iwg20d-q7.dtb \
|
||||
r8a7743-iwg20d-q7-dbcm-ca.dtb \
|
||||
r8a7743-sk-rzg1m.dtb \
|
||||
@ -974,6 +982,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
|
||||
rk3288-popmetal.dtb \
|
||||
rk3288-r89.dtb \
|
||||
rk3288-rock2-square.dtb \
|
||||
rk3288-rock-pi-n8.dtb \
|
||||
rk3288-tinker.dtb \
|
||||
rk3288-tinker-s.dtb \
|
||||
rk3288-veyron-brain.dtb \
|
||||
@ -1197,6 +1206,7 @@ dtb-$(CONFIG_MACH_SUNIV) += \
|
||||
dtb-$(CONFIG_ARCH_TANGO) += \
|
||||
tango4-vantage-1172.dtb
|
||||
dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
|
||||
tegra20-acer-a500-picasso.dtb \
|
||||
tegra20-harmony.dtb \
|
||||
tegra20-colibri-eval-v3.dtb \
|
||||
tegra20-colibri-iris.dtb \
|
||||
@ -1210,6 +1220,9 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
|
||||
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
|
||||
tegra30-apalis-eval.dtb \
|
||||
tegra30-apalis-v1.1-eval.dtb \
|
||||
tegra30-asus-nexus7-grouper-PM269.dtb \
|
||||
tegra30-asus-nexus7-grouper-E1565.dtb \
|
||||
tegra30-asus-nexus7-tilapia-E1565.dtb \
|
||||
tegra30-beaver.dtb \
|
||||
tegra30-cardhu-a02.dtb \
|
||||
tegra30-cardhu-a04.dtb \
|
||||
@ -1342,10 +1355,15 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
|
||||
mt8127-moose.dtb \
|
||||
mt8135-evbp1.dtb
|
||||
dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb
|
||||
dtb-$(CONFIG_ARCH_MSTARV7) += \
|
||||
infinity-msc313-breadbee_crust.dtb \
|
||||
infinity3-msc313e-breadbee.dtb \
|
||||
mercury5-ssc8336n-midrived08.dtb
|
||||
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
|
||||
dtb-$(CONFIG_ARCH_ASPEED) += \
|
||||
aspeed-ast2500-evb.dtb \
|
||||
aspeed-ast2600-evb.dtb \
|
||||
aspeed-bmc-amd-ethanolx.dtb \
|
||||
aspeed-bmc-arm-centriq2400-rep.dtb \
|
||||
aspeed-bmc-arm-stardragon4800-rep2.dtb \
|
||||
aspeed-bmc-facebook-cmm.dtb \
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/ {
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/display/tda998x.h>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
@ -23,3 +23,147 @@ oppnitro-1000000000 {
|
||||
opp-supported-hw = <0x06 0x0100>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
gpio-line-names =
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"P9_22 [spi0_sclk]",
|
||||
"P9_21 [spi0_d0]",
|
||||
"P9_18 [spi0_d1]",
|
||||
"P9_17 [spi0_cs0]",
|
||||
"[sd card]",
|
||||
"P9_42A [ecappwm0]",
|
||||
"P8_35 [hdmi]",
|
||||
"P8_33 [hdmi]",
|
||||
"P8_31 [hdmi]",
|
||||
"P8_32 [hdmi]",
|
||||
"P9_20 [i2c2_sda]",
|
||||
"P9_19 [i2c2_scl]",
|
||||
"P9_26 [uart1_rxd]",
|
||||
"P9_24 [uart1_txd]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[usb]",
|
||||
"[hdmi]",
|
||||
"P9_41B",
|
||||
"[ethernet]",
|
||||
"P8_19 [ehrpwm2a]",
|
||||
"P8_13 [ehrpwm2b]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"P8_14",
|
||||
"P8_17",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"P9_11 [uart4_rxd]",
|
||||
"P9_13 [uart4_txd]";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
"P8_25 [emmc]",
|
||||
"[emmc]",
|
||||
"P8_5 [emmc]",
|
||||
"P8_6 [emmc]",
|
||||
"P8_23 [emmc]",
|
||||
"P8_22 [emmc]",
|
||||
"P8_3 [emmc]",
|
||||
"P8_4 [emmc]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"P8_12",
|
||||
"P8_11",
|
||||
"P8_16",
|
||||
"P8_15",
|
||||
"P9_15A",
|
||||
"P9_23",
|
||||
"P9_14 [ehrpwm1a]",
|
||||
"P9_16 [ehrpwm1b]",
|
||||
"[emmc]",
|
||||
"[usr0 led]",
|
||||
"[usr1 led]",
|
||||
"[usr2 led]",
|
||||
"[usr3 led]",
|
||||
"[hdmi]",
|
||||
"[usb]",
|
||||
"[hdmi audio]",
|
||||
"P9_12",
|
||||
"P8_26",
|
||||
"P8_21 [emmc]",
|
||||
"P8_20 [emmc]";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names =
|
||||
"P9_15B",
|
||||
"P8_18",
|
||||
"P8_7",
|
||||
"P8_8",
|
||||
"P8_10",
|
||||
"P8_9",
|
||||
"P8_45 [hdmi]",
|
||||
"P8_46 [hdmi]",
|
||||
"P8_43 [hdmi]",
|
||||
"P8_44 [hdmi]",
|
||||
"P8_41 [hdmi]",
|
||||
"P8_42 [hdmi]",
|
||||
"P8_39 [hdmi]",
|
||||
"P8_40 [hdmi]",
|
||||
"P8_37 [hdmi]",
|
||||
"P8_38 [hdmi]",
|
||||
"P8_36 [hdmi]",
|
||||
"P8_34 [hdmi]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"P8_27 [hdmi]",
|
||||
"P8_29 [hdmi]",
|
||||
"P8_28 [hdmi]",
|
||||
"P8_30 [hdmi]",
|
||||
"[emmc]",
|
||||
"[emmc]",
|
||||
"[emmc]",
|
||||
"[emmc]",
|
||||
"[emmc]",
|
||||
"[emmc]";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
gpio-line-names =
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[i2c0]",
|
||||
"[i2c0]",
|
||||
"[emu]",
|
||||
"[emu]",
|
||||
"[ethernet]",
|
||||
"[ethernet]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[usb]",
|
||||
"P9_31 [spi1_sclk]",
|
||||
"P9_29 [spi1_d0]",
|
||||
"P9_30 [spi1_d1]",
|
||||
"P9_28 [spi1_cs0]",
|
||||
"P9_42B [ecappwm0]",
|
||||
"P9_27",
|
||||
"P9_41A",
|
||||
"P9_25",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]",
|
||||
"[NC]";
|
||||
};
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&ldo3_reg {
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
|
||||
* Copyright (C) 2015 Jablotron s.r.o. -- https://www.jablotron.com/
|
||||
* Author: Rostislav Lisovy <lisovy@jablotron.cz>
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user