2019-12-24 19:03:31 +09:00
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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2021-01-20 23:53:30 +09:00
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* Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
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2019-12-24 19:03:31 +09:00
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/of.h>
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#include <linux/vmalloc.h>
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#include "tsens.h"
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#include "thermal_core.h"
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#include <linux/qcom_scm.h>
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2021-01-20 23:53:30 +09:00
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#include <linux/msm_rtb.h>
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2019-12-24 19:03:31 +09:00
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#define TSENS_TM_INT_EN(n) ((n) + 0x4)
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#define TSENS_TM_CRITICAL_INT_STATUS(n) ((n) + 0x14)
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#define TSENS_TM_CRITICAL_INT_CLEAR(n) ((n) + 0x18)
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#define TSENS_TM_CRITICAL_INT_MASK(n) ((n) + 0x1c)
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#define TSENS_TM_CRITICAL_WD_BARK BIT(31)
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#define TSENS_TM_CRITICAL_CYCLE_MONITOR BIT(30)
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#define TSENS_TM_CRITICAL_INT_EN BIT(2)
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#define TSENS_TM_UPPER_INT_EN BIT(1)
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#define TSENS_TM_LOWER_INT_EN BIT(0)
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#define TSENS_TM_UPPER_LOWER_INT_DISABLE 0xffffffff
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#define TSENS_TM_SN_UPPER_LOWER_THRESHOLD(n) ((n) + 0x20)
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#define TSENS_TM_SN_ADDR_OFFSET 0x4
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#define TSENS_TM_UPPER_THRESHOLD_SET(n) ((n) << 12)
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#define TSENS_TM_UPPER_THRESHOLD_VALUE_SHIFT(n) ((n) >> 12)
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#define TSENS_TM_LOWER_THRESHOLD_VALUE(n) ((n) & 0xfff)
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#define TSENS_TM_UPPER_THRESHOLD_VALUE(n) (((n) & 0xfff000) >> 12)
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#define TSENS_TM_UPPER_THRESHOLD_MASK 0xfff000
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#define TSENS_TM_LOWER_THRESHOLD_MASK 0xfff
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#define TSENS_TM_UPPER_THRESHOLD_SHIFT 12
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#define TSENS_TM_SN_CRITICAL_THRESHOLD(n) ((n) + 0x60)
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#define TSENS_STATUS_ADDR_OFFSET 2
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#define TSENS_TM_UPPER_INT_MASK(n) (((n) & 0xffff0000) >> 16)
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#define TSENS_TM_LOWER_INT_MASK(n) ((n) & 0xffff)
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#define TSENS_TM_UPPER_LOWER_INT_STATUS(n) ((n) + 0x8)
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#define TSENS_TM_UPPER_LOWER_INT_CLEAR(n) ((n) + 0xc)
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#define TSENS_TM_UPPER_LOWER_INT_MASK(n) ((n) + 0x10)
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#define TSENS_TM_UPPER_INT_SET(n) (1 << (n + 16))
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#define TSENS_TM_SN_CRITICAL_THRESHOLD_MASK 0xfff
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#define TSENS_TM_SN_STATUS_VALID_BIT BIT(21)
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#define TSENS_TM_SN_STATUS_CRITICAL_STATUS BIT(19)
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#define TSENS_TM_SN_STATUS_UPPER_STATUS BIT(18)
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#define TSENS_TM_SN_STATUS_LOWER_STATUS BIT(17)
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#define TSENS_TM_SN_LAST_TEMP_MASK 0xfff
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#define TSENS_TM_CODE_BIT_MASK 0xfff
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#define TSENS_TM_0C_THR_MASK 0xfff
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#define TSENS_TM_0C_THR_OFFSET 12
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#define TSENS_TM_CODE_SIGN_BIT 0x800
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#define TSENS_TM_SCALE_DECI_MILLIDEG 100
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#define TSENS_DEBUG_WDOG_TRIGGER_COUNT 5
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#define TSENS_TM_WATCHDOG_LOG(n) ((n) + 0x13c)
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#define TSENS_TM_WATCHDOG_LOG_v23(n) ((n) + 0x170)
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#define TSENS_EN BIT(0)
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#define TSENS_CTRL_SENSOR_EN_MASK(n) ((n >> 3) & 0xffff)
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#define TSENS_TM_TRDY(n) ((n) + 0xe4)
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#define TSENS_TM_TRDY_FIRST_ROUND_COMPLETE BIT(3)
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#define TSENS_TM_TRDY_FIRST_ROUND_COMPLETE_SHIFT 3
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#define TSENS_TM_0C_INT_STATUS(n) ((n) + 0xe0)
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#define TSENS_TM_0C_THRESHOLDS(n) ((n) + 0x1c)
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#define TSENS_MAX_READ_FAIL 50
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#define TSENS_INIT_ID 0x5
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#define TSENS_RECOVERY_LOOP_COUNT 5
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2020-06-26 19:49:32 +09:00
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#define TSENS_RE_INIT_MAX_COUNT 5
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2019-12-24 19:03:31 +09:00
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static void msm_tsens_convert_temp(int last_temp, int *temp)
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{
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int code_mask = ~TSENS_TM_CODE_BIT_MASK;
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if (last_temp & TSENS_TM_CODE_SIGN_BIT) {
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/* Sign extension for negative value */
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last_temp |= code_mask;
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}
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*temp = last_temp * TSENS_TM_SCALE_DECI_MILLIDEG;
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}
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static int tsens2xxx_get_temp(struct tsens_sensor *sensor, int *temp)
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{
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struct tsens_device *tmdev = NULL, *tmdev_itr;
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unsigned int code, ret;
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void __iomem *sensor_addr, *trdy;
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int last_temp = 0, last_temp2 = 0, last_temp3 = 0, count = 0;
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int tsens_ret;
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2020-06-26 19:49:32 +09:00
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static atomic_t in_tsens_reinit;
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2019-12-24 19:03:31 +09:00
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if (!sensor)
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return -EINVAL;
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tmdev = sensor->tmdev;
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sensor_addr = TSENS_TM_SN_STATUS(tmdev->tsens_tm_addr);
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trdy = TSENS_TM_TRDY(tmdev->tsens_tm_addr);
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code = readl_relaxed_no_log(trdy);
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if (!((code & TSENS_TM_TRDY_FIRST_ROUND_COMPLETE) >>
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TSENS_TM_TRDY_FIRST_ROUND_COMPLETE_SHIFT)) {
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2020-06-26 19:49:32 +09:00
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if (atomic_read(&in_tsens_reinit)) {
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pr_err("%s: tsens re-init is in progress\n", __func__);
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return -EAGAIN;
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}
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2019-12-24 19:03:31 +09:00
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pr_err("%s: tsens device first round not complete0x%x\n",
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__func__, code);
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2020-06-26 19:49:32 +09:00
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2019-12-24 19:03:31 +09:00
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/* Wait for 2.5 ms for tsens controller to recover */
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do {
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udelay(500);
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code = readl_relaxed_no_log(trdy);
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if (code & TSENS_TM_TRDY_FIRST_ROUND_COMPLETE) {
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TSENS_DUMP(tmdev, "%s",
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"tsens controller recovered\n");
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goto sensor_read;
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}
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} while (++count < TSENS_RECOVERY_LOOP_COUNT);
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/*
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* TSENS controller did not recover,
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* proceed with SCM call to re-init it
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*/
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if (tmdev->tsens_reinit_wa) {
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2020-06-26 19:49:32 +09:00
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if (atomic_read(&in_tsens_reinit)) {
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pr_err("%s: tsens re-init is in progress\n",
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__func__);
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return -EAGAIN;
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}
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atomic_set(&in_tsens_reinit, 1);
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2019-12-24 19:03:31 +09:00
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if (tmdev->ops->dbg)
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tmdev->ops->dbg(tmdev, 0,
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TSENS_DBG_LOG_BUS_ID_DATA, NULL);
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2020-06-26 19:49:32 +09:00
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if (tmdev->tsens_reinit_cnt >=
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TSENS_RE_INIT_MAX_COUNT) {
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pr_err(
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"%s: TSENS not recovered after %d re-init\n",
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__func__, tmdev->tsens_reinit_cnt);
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BUG();
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}
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2019-12-24 19:03:31 +09:00
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/*Make an scm call to re-init TSENS */
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TSENS_DBG(tmdev, "%s",
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2020-06-26 19:49:32 +09:00
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"Calling TZ to re-init TSENS\n");
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2019-12-24 19:03:31 +09:00
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ret = qcom_scm_tsens_reinit(&tsens_ret);
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TSENS_DBG(tmdev, "%s",
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2020-06-26 19:49:32 +09:00
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"return from scm call\n");
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2019-12-24 19:03:31 +09:00
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if (ret) {
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pr_err("%s: scm call failed %d\n",
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__func__, ret);
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BUG();
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}
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if (tsens_ret) {
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pr_err("%s: scm call failed to init tsens %d\n",
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__func__, tsens_ret);
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BUG();
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}
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2020-06-26 19:49:32 +09:00
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tmdev->tsens_reinit_cnt++;
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atomic_set(&in_tsens_reinit, 0);
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2019-12-24 19:03:31 +09:00
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/* Notify thermal fwk */
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list_for_each_entry(tmdev_itr,
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&tsens_device_list, list) {
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queue_work(tmdev_itr->tsens_reinit_work,
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&tmdev_itr->therm_fwk_notify);
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}
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} else {
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pr_err("%s: tsens controller got reset\n", __func__);
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BUG();
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}
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return -EAGAIN;
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}
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sensor_read:
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tmdev->trdy_fail_ctr = 0;
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2020-06-26 19:49:32 +09:00
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tmdev->tsens_reinit_cnt = 0;
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2019-12-24 19:03:31 +09:00
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code = readl_relaxed_no_log(sensor_addr +
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(sensor->hw_id << TSENS_STATUS_ADDR_OFFSET));
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last_temp = code & TSENS_TM_SN_LAST_TEMP_MASK;
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if (code & TSENS_TM_SN_STATUS_VALID_BIT) {
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msm_tsens_convert_temp(last_temp, temp);
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goto dbg;
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}
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code = readl_relaxed_no_log(sensor_addr +
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(sensor->hw_id << TSENS_STATUS_ADDR_OFFSET));
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last_temp2 = code & TSENS_TM_SN_LAST_TEMP_MASK;
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if (code & TSENS_TM_SN_STATUS_VALID_BIT) {
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last_temp = last_temp2;
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msm_tsens_convert_temp(last_temp, temp);
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goto dbg;
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}
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code = readl_relaxed_no_log(sensor_addr +
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(sensor->hw_id <<
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TSENS_STATUS_ADDR_OFFSET));
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last_temp3 = code & TSENS_TM_SN_LAST_TEMP_MASK;
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if (code & TSENS_TM_SN_STATUS_VALID_BIT) {
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last_temp = last_temp3;
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msm_tsens_convert_temp(last_temp, temp);
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goto dbg;
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}
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if (last_temp == last_temp2)
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last_temp = last_temp2;
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else if (last_temp2 == last_temp3)
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last_temp = last_temp3;
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msm_tsens_convert_temp(last_temp, temp);
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dbg:
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if (tmdev->ops->dbg)
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tmdev->ops->dbg(tmdev, (u32) sensor->hw_id,
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TSENS_DBG_LOG_TEMP_READS, temp);
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return 0;
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}
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2020-07-07 16:58:42 +09:00
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int tsens_2xxx_get_zeroc_status(struct tsens_sensor *sensor, int *status)
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2019-12-24 19:03:31 +09:00
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{
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struct tsens_device *tmdev = NULL;
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2020-07-07 16:58:42 +09:00
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void __iomem *addr;
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2019-12-24 19:03:31 +09:00
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if (!sensor)
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return -EINVAL;
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tmdev = sensor->tmdev;
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2020-07-07 16:58:42 +09:00
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addr = TSENS_TM_0C_INT_STATUS(tmdev->tsens_tm_addr);
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*status = readl_relaxed(addr);
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2019-12-24 19:03:31 +09:00
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2020-07-07 16:58:42 +09:00
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TSENS_DBG(tmdev, "ZeroC status: %d\n", *status);
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2019-12-24 19:03:31 +09:00
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return 0;
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}
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static int tsens_tm_activate_trip_type(struct tsens_sensor *tm_sensor,
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int trip, enum thermal_device_mode mode)
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{
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struct tsens_device *tmdev = NULL;
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unsigned int reg_cntl, mask;
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int rc = 0;
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/* clear the interrupt and unmask */
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if (!tm_sensor || trip < 0)
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return -EINVAL;
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tmdev = tm_sensor->tmdev;
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if (!tmdev)
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return -EINVAL;
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mask = (tm_sensor->hw_id);
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switch (trip) {
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case THERMAL_TRIP_CRITICAL:
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tmdev->sensor[tm_sensor->hw_id].thr_state.crit_th_state = mode;
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reg_cntl = readl_relaxed(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr));
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if (mode == THERMAL_DEVICE_DISABLED)
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writel_relaxed(reg_cntl | (1 << mask),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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else
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writel_relaxed(reg_cntl & ~(1 << mask),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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break;
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case TSENS_TRIP_CONFIGURABLE_HI:
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tmdev->sensor[tm_sensor->hw_id].thr_state.high_th_state = mode;
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reg_cntl = readl_relaxed(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr));
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if (mode == THERMAL_DEVICE_DISABLED)
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writel_relaxed(reg_cntl |
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(TSENS_TM_UPPER_INT_SET(mask)),
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(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr)));
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else
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writel_relaxed(reg_cntl &
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~(TSENS_TM_UPPER_INT_SET(mask)),
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(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr)));
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break;
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case TSENS_TRIP_CONFIGURABLE_LOW:
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tmdev->sensor[tm_sensor->hw_id].thr_state.low_th_state = mode;
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reg_cntl = readl_relaxed(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr));
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if (mode == THERMAL_DEVICE_DISABLED)
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writel_relaxed(reg_cntl | (1 << mask),
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(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr)));
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else
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writel_relaxed(reg_cntl & ~(1 << mask),
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(TSENS_TM_UPPER_LOWER_INT_MASK
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(tmdev->tsens_tm_addr)));
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break;
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default:
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rc = -EINVAL;
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}
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/* Activate and enable the respective trip threshold setting */
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|
|
mb();
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsens2xxx_set_trip_temp(struct tsens_sensor *tm_sensor,
|
|
|
|
int low_temp, int high_temp)
|
|
|
|
{
|
|
|
|
unsigned int reg_cntl;
|
|
|
|
unsigned long flags;
|
|
|
|
struct tsens_device *tmdev = NULL;
|
|
|
|
int rc = 0;
|
|
|
|
|
|
|
|
if (!tm_sensor)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
tmdev = tm_sensor->tmdev;
|
|
|
|
if (!tmdev)
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pr_debug("%s: sensor:%d low_temp(mdegC):%d, high_temp(mdegC):%d\n",
|
|
|
|
__func__, tm_sensor->hw_id, low_temp, high_temp);
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tmdev->tsens_upp_low_lock, flags);
|
|
|
|
|
|
|
|
if (high_temp != INT_MAX) {
|
|
|
|
tmdev->sensor[tm_sensor->hw_id].thr_state.high_temp = high_temp;
|
|
|
|
reg_cntl = readl_relaxed((TSENS_TM_SN_UPPER_LOWER_THRESHOLD
|
|
|
|
(tmdev->tsens_tm_addr)) +
|
|
|
|
(tm_sensor->hw_id *
|
|
|
|
TSENS_TM_SN_ADDR_OFFSET));
|
|
|
|
high_temp /= TSENS_TM_SCALE_DECI_MILLIDEG;
|
|
|
|
high_temp = TSENS_TM_UPPER_THRESHOLD_SET(high_temp);
|
|
|
|
high_temp &= TSENS_TM_UPPER_THRESHOLD_MASK;
|
|
|
|
reg_cntl &= ~TSENS_TM_UPPER_THRESHOLD_MASK;
|
|
|
|
writel_relaxed(reg_cntl | high_temp,
|
|
|
|
(TSENS_TM_SN_UPPER_LOWER_THRESHOLD
|
|
|
|
(tmdev->tsens_tm_addr) +
|
|
|
|
(tm_sensor->hw_id * TSENS_TM_SN_ADDR_OFFSET)));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (low_temp != INT_MIN) {
|
|
|
|
tmdev->sensor[tm_sensor->hw_id].thr_state.low_temp = low_temp;
|
|
|
|
reg_cntl = readl_relaxed((TSENS_TM_SN_UPPER_LOWER_THRESHOLD
|
|
|
|
(tmdev->tsens_tm_addr)) +
|
|
|
|
(tm_sensor->hw_id *
|
|
|
|
TSENS_TM_SN_ADDR_OFFSET));
|
|
|
|
low_temp /= TSENS_TM_SCALE_DECI_MILLIDEG;
|
|
|
|
low_temp &= TSENS_TM_LOWER_THRESHOLD_MASK;
|
|
|
|
reg_cntl &= ~TSENS_TM_LOWER_THRESHOLD_MASK;
|
|
|
|
writel_relaxed(reg_cntl | low_temp,
|
|
|
|
(TSENS_TM_SN_UPPER_LOWER_THRESHOLD
|
|
|
|
(tmdev->tsens_tm_addr) +
|
|
|
|
(tm_sensor->hw_id * TSENS_TM_SN_ADDR_OFFSET)));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Set trip temperature thresholds */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
if (high_temp != INT_MAX) {
|
|
|
|
rc = tsens_tm_activate_trip_type(tm_sensor,
|
|
|
|
TSENS_TRIP_CONFIGURABLE_HI,
|
|
|
|
THERMAL_DEVICE_ENABLED);
|
|
|
|
if (rc) {
|
|
|
|
pr_err("trip high enable error :%d\n", rc);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc = tsens_tm_activate_trip_type(tm_sensor,
|
|
|
|
TSENS_TRIP_CONFIGURABLE_HI,
|
|
|
|
THERMAL_DEVICE_DISABLED);
|
|
|
|
if (rc) {
|
|
|
|
pr_err("trip high disable error :%d\n", rc);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (low_temp != INT_MIN) {
|
|
|
|
rc = tsens_tm_activate_trip_type(tm_sensor,
|
|
|
|
TSENS_TRIP_CONFIGURABLE_LOW,
|
|
|
|
THERMAL_DEVICE_ENABLED);
|
|
|
|
if (rc) {
|
|
|
|
pr_err("trip low enable activation error :%d\n", rc);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc = tsens_tm_activate_trip_type(tm_sensor,
|
|
|
|
TSENS_TRIP_CONFIGURABLE_LOW,
|
|
|
|
THERMAL_DEVICE_DISABLED);
|
|
|
|
if (rc) {
|
|
|
|
pr_err("trip low disable error :%d\n", rc);
|
|
|
|
goto fail;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fail:
|
|
|
|
spin_unlock_irqrestore(&tmdev->tsens_upp_low_lock, flags);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t tsens_tm_critical_irq_thread(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct tsens_device *tm = data;
|
|
|
|
unsigned int i, status, wd_log, wd_mask;
|
|
|
|
unsigned long flags;
|
|
|
|
void __iomem *sensor_status_addr, *sensor_int_mask_addr;
|
|
|
|
void __iomem *sensor_critical_addr;
|
|
|
|
void __iomem *wd_critical_addr, *wd_log_addr;
|
|
|
|
|
|
|
|
sensor_status_addr = TSENS_TM_SN_STATUS(tm->tsens_tm_addr);
|
|
|
|
sensor_int_mask_addr =
|
|
|
|
TSENS_TM_CRITICAL_INT_MASK(tm->tsens_tm_addr);
|
|
|
|
sensor_critical_addr =
|
|
|
|
TSENS_TM_SN_CRITICAL_THRESHOLD(tm->tsens_tm_addr);
|
|
|
|
wd_critical_addr =
|
|
|
|
TSENS_TM_CRITICAL_INT_STATUS(tm->tsens_tm_addr);
|
|
|
|
if (tm->ctrl_data->ver_major == 2 && tm->ctrl_data->ver_minor == 3)
|
|
|
|
wd_log_addr = TSENS_TM_WATCHDOG_LOG_v23(tm->tsens_tm_addr);
|
|
|
|
else
|
|
|
|
wd_log_addr = TSENS_TM_WATCHDOG_LOG(tm->tsens_tm_addr);
|
|
|
|
|
|
|
|
if (tm->ctrl_data->wd_bark) {
|
|
|
|
wd_mask = readl_relaxed(wd_critical_addr);
|
|
|
|
if (wd_mask & TSENS_TM_CRITICAL_WD_BARK) {
|
|
|
|
/*
|
|
|
|
* Clear watchdog interrupt and
|
|
|
|
* increment global wd count
|
|
|
|
*/
|
|
|
|
writel_relaxed(wd_mask | TSENS_TM_CRITICAL_WD_BARK,
|
|
|
|
(TSENS_TM_CRITICAL_INT_CLEAR
|
|
|
|
(tm->tsens_tm_addr)));
|
|
|
|
writel_relaxed(wd_mask & ~(TSENS_TM_CRITICAL_WD_BARK),
|
|
|
|
(TSENS_TM_CRITICAL_INT_CLEAR
|
|
|
|
(tm->tsens_tm_addr)));
|
|
|
|
wd_log = readl_relaxed(wd_log_addr);
|
|
|
|
if (wd_log >= TSENS_DEBUG_WDOG_TRIGGER_COUNT) {
|
|
|
|
pr_err("Watchdog count:%d\n", wd_log);
|
|
|
|
if (tm->ops->dbg)
|
|
|
|
tm->ops->dbg(tm, 0,
|
|
|
|
TSENS_DBG_LOG_BUS_ID_DATA, NULL);
|
|
|
|
BUG();
|
|
|
|
}
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < TSENS_MAX_SENSORS; i++) {
|
|
|
|
int int_mask, int_mask_val;
|
|
|
|
u32 addr_offset;
|
|
|
|
|
|
|
|
if (IS_ERR(tm->sensor[i].tzd))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tm->tsens_crit_lock, flags);
|
|
|
|
addr_offset = tm->sensor[i].hw_id *
|
|
|
|
TSENS_TM_SN_ADDR_OFFSET;
|
|
|
|
status = readl_relaxed(sensor_status_addr + addr_offset);
|
|
|
|
int_mask = readl_relaxed(sensor_int_mask_addr);
|
|
|
|
|
|
|
|
if ((status & TSENS_TM_SN_STATUS_CRITICAL_STATUS) &&
|
|
|
|
!(int_mask & (1 << tm->sensor[i].hw_id))) {
|
|
|
|
int_mask = readl_relaxed(sensor_int_mask_addr);
|
|
|
|
int_mask_val = (1 << tm->sensor[i].hw_id);
|
|
|
|
/* Mask the corresponding interrupt for the sensors */
|
|
|
|
writel_relaxed(int_mask | int_mask_val,
|
|
|
|
TSENS_TM_CRITICAL_INT_MASK(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
/* Clear the corresponding sensors interrupt */
|
|
|
|
writel_relaxed(int_mask_val,
|
|
|
|
TSENS_TM_CRITICAL_INT_CLEAR
|
|
|
|
(tm->tsens_tm_addr));
|
|
|
|
writel_relaxed(0,
|
|
|
|
TSENS_TM_CRITICAL_INT_CLEAR(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
tm->sensor[i].thr_state.crit_th_state =
|
|
|
|
THERMAL_DEVICE_DISABLED;
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&tm->tsens_crit_lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Mask critical interrupt */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t tsens_tm_irq_thread(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct tsens_device *tm = data;
|
|
|
|
unsigned int i, status, threshold, temp;
|
|
|
|
unsigned long flags;
|
|
|
|
void __iomem *sensor_status_addr;
|
|
|
|
void __iomem *sensor_int_mask_addr;
|
|
|
|
void __iomem *sensor_upper_lower_addr;
|
|
|
|
u32 addr_offset = 0;
|
|
|
|
|
|
|
|
sensor_status_addr = TSENS_TM_SN_STATUS(tm->tsens_tm_addr);
|
|
|
|
sensor_int_mask_addr =
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_MASK(tm->tsens_tm_addr);
|
|
|
|
sensor_upper_lower_addr =
|
|
|
|
TSENS_TM_SN_UPPER_LOWER_THRESHOLD(tm->tsens_tm_addr);
|
|
|
|
|
|
|
|
for (i = 0; i < TSENS_MAX_SENSORS; i++) {
|
|
|
|
bool upper_thr = false, lower_thr = false;
|
|
|
|
int int_mask, int_mask_val = 0, rc;
|
|
|
|
|
|
|
|
if (IS_ERR(tm->sensor[i].tzd))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
rc = tsens2xxx_get_temp(&tm->sensor[i], &temp);
|
|
|
|
if (rc) {
|
|
|
|
pr_debug("Error:%d reading temp sensor:%d\n", rc, i);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_lock_irqsave(&tm->tsens_upp_low_lock, flags);
|
|
|
|
addr_offset = tm->sensor[i].hw_id *
|
|
|
|
TSENS_TM_SN_ADDR_OFFSET;
|
|
|
|
status = readl_relaxed(sensor_status_addr + addr_offset);
|
|
|
|
threshold = readl_relaxed(sensor_upper_lower_addr +
|
|
|
|
addr_offset);
|
|
|
|
int_mask = readl_relaxed(sensor_int_mask_addr);
|
|
|
|
|
|
|
|
if ((status & TSENS_TM_SN_STATUS_UPPER_STATUS) &&
|
|
|
|
!(int_mask &
|
|
|
|
(1 << (tm->sensor[i].hw_id + 16)))) {
|
|
|
|
int_mask = readl_relaxed(sensor_int_mask_addr);
|
|
|
|
int_mask_val = TSENS_TM_UPPER_INT_SET(
|
|
|
|
tm->sensor[i].hw_id);
|
|
|
|
/* Mask the corresponding interrupt for the sensors */
|
|
|
|
writel_relaxed(int_mask | int_mask_val,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_MASK(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
/* Clear the corresponding sensors interrupt */
|
|
|
|
writel_relaxed(int_mask_val,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_CLEAR(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
writel_relaxed(0,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_CLEAR(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
if (TSENS_TM_UPPER_THRESHOLD_VALUE(threshold) >
|
|
|
|
(temp/TSENS_TM_SCALE_DECI_MILLIDEG)) {
|
|
|
|
pr_debug("Re-arm high threshold\n");
|
|
|
|
rc = tsens_tm_activate_trip_type(
|
|
|
|
&tm->sensor[i],
|
|
|
|
TSENS_TRIP_CONFIGURABLE_HI,
|
|
|
|
THERMAL_DEVICE_ENABLED);
|
|
|
|
if (rc)
|
|
|
|
pr_err("high rearm failed:%d\n", rc);
|
|
|
|
} else {
|
|
|
|
upper_thr = true;
|
|
|
|
tm->sensor[i].thr_state.high_th_state =
|
|
|
|
THERMAL_DEVICE_DISABLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((status & TSENS_TM_SN_STATUS_LOWER_STATUS) &&
|
|
|
|
!(int_mask &
|
|
|
|
(1 << tm->sensor[i].hw_id))) {
|
|
|
|
int_mask = readl_relaxed(sensor_int_mask_addr);
|
|
|
|
int_mask_val = (1 << tm->sensor[i].hw_id);
|
|
|
|
/* Mask the corresponding interrupt for the sensors */
|
|
|
|
writel_relaxed(int_mask | int_mask_val,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_MASK(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
/* Clear the corresponding sensors interrupt */
|
|
|
|
writel_relaxed(int_mask_val,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_CLEAR(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
writel_relaxed(0,
|
|
|
|
TSENS_TM_UPPER_LOWER_INT_CLEAR(
|
|
|
|
tm->tsens_tm_addr));
|
|
|
|
if (TSENS_TM_LOWER_THRESHOLD_VALUE(threshold)
|
|
|
|
< (temp/TSENS_TM_SCALE_DECI_MILLIDEG)) {
|
|
|
|
pr_debug("Re-arm low threshold\n");
|
|
|
|
rc = tsens_tm_activate_trip_type(
|
|
|
|
&tm->sensor[i],
|
|
|
|
TSENS_TRIP_CONFIGURABLE_LOW,
|
|
|
|
THERMAL_DEVICE_ENABLED);
|
|
|
|
if (rc)
|
|
|
|
pr_err("low rearm failed:%d\n", rc);
|
|
|
|
} else {
|
|
|
|
lower_thr = true;
|
|
|
|
tm->sensor[i].thr_state.low_th_state =
|
|
|
|
THERMAL_DEVICE_DISABLED;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&tm->tsens_upp_low_lock, flags);
|
|
|
|
|
|
|
|
if (upper_thr || lower_thr) {
|
|
|
|
/* Use id for multiple controllers */
|
|
|
|
pr_debug("sensor:%d trigger temp (%d degC)\n",
|
|
|
|
tm->sensor[i].hw_id, temp);
|
|
|
|
of_thermal_handle_trip_temp(tm->dev,
|
|
|
|
tm->sensor[i].tzd, temp);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Disable monitoring sensor trip threshold for triggered sensor */
|
|
|
|
mb();
|
|
|
|
|
|
|
|
if (tm->ops->dbg)
|
|
|
|
tm->ops->dbg(tm, 0, TSENS_DBG_LOG_INTERRUPT_TIMESTAMP, NULL);
|
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2020-07-07 16:58:42 +09:00
|
|
|
static irqreturn_t tsens_tm_zeroc_irq_thread(int irq, void *data)
|
2019-12-24 19:03:31 +09:00
|
|
|
{
|
|
|
|
struct tsens_device *tm = data;
|
|
|
|
int status, thrs, set_thr, reset_thr;
|
|
|
|
void __iomem *srot_addr, *addr;
|
|
|
|
|
|
|
|
addr = TSENS_TM_0C_INT_STATUS(tm->tsens_tm_addr);
|
|
|
|
status = readl_relaxed(addr);
|
|
|
|
|
|
|
|
srot_addr = TSENS_CTRL_ADDR(tm->tsens_srot_addr);
|
|
|
|
thrs = readl_relaxed(TSENS_TM_0C_THRESHOLDS(srot_addr));
|
|
|
|
|
|
|
|
msm_tsens_convert_temp(thrs & TSENS_TM_0C_THR_MASK, &reset_thr);
|
2020-07-07 16:58:42 +09:00
|
|
|
msm_tsens_convert_temp(((thrs >> TSENS_TM_0C_THR_OFFSET)
|
|
|
|
& TSENS_TM_0C_THR_MASK), &set_thr);
|
2019-12-24 19:03:31 +09:00
|
|
|
|
2020-07-07 16:58:42 +09:00
|
|
|
TSENS_DBG(tm, "Tsens ZeroC status: %d set_t:%d reset_t:%d\n",
|
|
|
|
status, set_thr, reset_thr);
|
|
|
|
of_thermal_handle_trip_temp(tm->dev, tm->zeroc.tzd, status);
|
2019-12-24 19:03:31 +09:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int tsens2xxx_hw_sensor_en(struct tsens_device *tmdev,
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u32 sensor_id)
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{
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void __iomem *srot_addr;
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unsigned int srot_val, sensor_en;
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srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr + 0x4);
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srot_val = readl_relaxed(srot_addr);
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srot_val = TSENS_CTRL_SENSOR_EN_MASK(srot_val);
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sensor_en = ((1 << sensor_id) & srot_val);
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return sensor_en;
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}
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static int tsens2xxx_hw_init(struct tsens_device *tmdev)
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{
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void __iomem *srot_addr;
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void __iomem *sensor_int_mask_addr;
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unsigned int srot_val, crit_mask, crit_val;
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void __iomem *int_mask_addr;
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srot_addr = TSENS_CTRL_ADDR(tmdev->tsens_srot_addr + 0x4);
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srot_val = readl_relaxed(srot_addr);
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if (!(srot_val & TSENS_EN)) {
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pr_err("TSENS device is not enabled\n");
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return -ENODEV;
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}
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if (tmdev->ctrl_data->cycle_monitor) {
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sensor_int_mask_addr =
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TSENS_TM_CRITICAL_INT_MASK(tmdev->tsens_tm_addr);
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crit_mask = readl_relaxed(sensor_int_mask_addr);
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crit_val = TSENS_TM_CRITICAL_CYCLE_MONITOR;
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if (tmdev->ctrl_data->cycle_compltn_monitor_mask)
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writel_relaxed((crit_mask | crit_val),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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else
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writel_relaxed((crit_mask & ~crit_val),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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/*Update critical cycle monitoring*/
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mb();
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}
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if (tmdev->ctrl_data->wd_bark) {
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sensor_int_mask_addr =
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TSENS_TM_CRITICAL_INT_MASK(tmdev->tsens_tm_addr);
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crit_mask = readl_relaxed(sensor_int_mask_addr);
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crit_val = TSENS_TM_CRITICAL_WD_BARK;
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if (tmdev->ctrl_data->wd_bark_mask)
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writel_relaxed((crit_mask | crit_val),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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else
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writel_relaxed((crit_mask & ~crit_val),
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(TSENS_TM_CRITICAL_INT_MASK
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(tmdev->tsens_tm_addr)));
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/*Update watchdog monitoring*/
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mb();
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}
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int_mask_addr = TSENS_TM_UPPER_LOWER_INT_MASK(tmdev->tsens_tm_addr);
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writel_relaxed(TSENS_TM_UPPER_LOWER_INT_DISABLE, int_mask_addr);
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writel_relaxed(TSENS_TM_CRITICAL_INT_EN |
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TSENS_TM_UPPER_INT_EN | TSENS_TM_LOWER_INT_EN,
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TSENS_TM_INT_EN(tmdev->tsens_tm_addr));
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spin_lock_init(&tmdev->tsens_crit_lock);
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spin_lock_init(&tmdev->tsens_upp_low_lock);
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if (tmdev->ctrl_data->mtc) {
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if (tmdev->ops->dbg)
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tmdev->ops->dbg(tmdev, 0, TSENS_DBG_MTC_DATA, NULL);
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}
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return 0;
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}
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static const struct tsens_irqs tsens2xxx_irqs[] = {
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{ "tsens-upper-lower", tsens_tm_irq_thread},
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{ "tsens-critical", tsens_tm_critical_irq_thread},
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2020-07-07 16:58:42 +09:00
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{ "tsens-0C", tsens_tm_zeroc_irq_thread},
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2019-12-24 19:03:31 +09:00
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};
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static int tsens2xxx_register_interrupts(struct tsens_device *tmdev)
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{
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struct platform_device *pdev;
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int i, rc, irq_no;
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unsigned long irqflags = IRQF_TRIGGER_HIGH | IRQF_ONESHOT;
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if (!tmdev)
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return -EINVAL;
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2020-07-07 16:58:42 +09:00
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if (tmdev->zeroc_sensor_id != MIN_TEMP_DEF_OFFSET)
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2019-12-24 19:03:31 +09:00
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irq_no = ARRAY_SIZE(tsens2xxx_irqs);
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else
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irq_no = ARRAY_SIZE(tsens2xxx_irqs) - 1;
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pdev = tmdev->pdev;
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for (i = 0; i < irq_no; i++) {
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int irq;
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irq = platform_get_irq_byname(pdev, tsens2xxx_irqs[i].name);
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if (irq < 0) {
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dev_err(&pdev->dev, "failed to get irq %s\n",
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tsens2xxx_irqs[i].name);
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return irq;
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}
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if (i == 2)
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irqflags = IRQF_TRIGGER_RISING | IRQF_ONESHOT;
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rc = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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tsens2xxx_irqs[i].handler,
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irqflags, tsens2xxx_irqs[i].name, tmdev);
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if (rc) {
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dev_err(&pdev->dev, "failed to get irq %s\n",
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tsens2xxx_irqs[i].name);
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return rc;
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}
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enable_irq_wake(irq);
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}
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return 0;
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}
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static const struct tsens_ops ops_tsens2xxx = {
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.hw_init = tsens2xxx_hw_init,
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.get_temp = tsens2xxx_get_temp,
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.set_trips = tsens2xxx_set_trip_temp,
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.interrupts_reg = tsens2xxx_register_interrupts,
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.dbg = tsens2xxx_dbg,
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.sensor_en = tsens2xxx_hw_sensor_en,
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};
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const struct tsens_data data_tsens2xxx = {
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.cycle_monitor = false,
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.cycle_compltn_monitor_mask = 1,
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.wd_bark = false,
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.wd_bark_mask = 1,
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.ops = &ops_tsens2xxx,
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.mtc = true,
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};
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const struct tsens_data data_tsens23xx = {
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.cycle_monitor = true,
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.cycle_compltn_monitor_mask = 1,
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.wd_bark = true,
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.wd_bark_mask = 1,
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.ops = &ops_tsens2xxx,
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.mtc = false,
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.ver_major = 2,
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.ver_minor = 3,
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};
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const struct tsens_data data_tsens24xx = {
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.cycle_monitor = true,
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.cycle_compltn_monitor_mask = 1,
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.wd_bark = true,
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/* Enable Watchdog monitoring by unmasking */
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.wd_bark_mask = 0,
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.ops = &ops_tsens2xxx,
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.mtc = false,
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};
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const struct tsens_data data_tsens26xx = {
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.cycle_monitor = true,
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.cycle_compltn_monitor_mask = 1,
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.wd_bark = true,
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.wd_bark_mask = 0,
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.ops = &ops_tsens2xxx,
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.mtc = false,
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.ver_major = 2,
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.ver_minor = 6,
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};
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