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android_kernel_xiaomi_sm8450/drivers/memory/Makefile

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memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 21:24:05 +09:00
#
# Makefile for memory devices
#
memory: fix build when CONFIG_OF && !CONFIG_DDR Commit e6b42eb "memory: emif: add device tree support to emif driver" added drivers/memory/of_memory.c, which references tables defined in lib/jedec_ddr_data.c. of_memory.c is compiled when CONFIG_OF, whereas jedec_ddr_data.c is compiled when CONFIG_DDR. This breaks the build when CONFIG_OF is defined but not CONFIG_DDR: drivers/built-in.o: In function `of_get_ddr_timings': drivers/memory/of_memory.c:138: undefined reference to `lpddr2_jedec_timings' drivers/built-in.o: In function `of_get_min_tck': drivers/memory/of_memory.c:62: undefined reference to `lpddr2_jedec_min_tck' make: *** [vmlinux] Error 1 To solve this, only compile of_memory.c when CONFIG_OF && CONFIG_DDR, otherwise, stub out the functions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-09-06 03:29:23 +09:00
ifeq ($(CONFIG_DDR),y)
memory: emif: add device tree support to emif driver Device tree support for the EMIF driver. LPDDR2 generic timings extraction from device is managed using couple of helper functions which can be used by other memory controller drivers. Reviewed-by: Benoit Cousson <b-cousson@ti.com> Reviewed-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Aneesh V <aneesh@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-08-17 17:35:15 +09:00
obj-$(CONFIG_OF) += of_memory.o
memory: fix build when CONFIG_OF && !CONFIG_DDR Commit e6b42eb "memory: emif: add device tree support to emif driver" added drivers/memory/of_memory.c, which references tables defined in lib/jedec_ddr_data.c. of_memory.c is compiled when CONFIG_OF, whereas jedec_ddr_data.c is compiled when CONFIG_DDR. This breaks the build when CONFIG_OF is defined but not CONFIG_DDR: drivers/built-in.o: In function `of_get_ddr_timings': drivers/memory/of_memory.c:138: undefined reference to `lpddr2_jedec_timings' drivers/built-in.o: In function `of_get_min_tck': drivers/memory/of_memory.c:62: undefined reference to `lpddr2_jedec_min_tck' make: *** [vmlinux] Error 1 To solve this, only compile of_memory.c when CONFIG_OF && CONFIG_DDR, otherwise, stub out the functions. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-09-06 03:29:23 +09:00
endif
memory: add ARM PL172 MultiPort Memory Controller driver This driver makes it possible to configure the static memory chip selects on the ARM PL172 MultiPort Memory Controller from a set of properties in DT. Configuration of dynamic memory is not supported and is left to the boot loader. The intended usage is to setup timing and configuration for static memory devices like NAND and NOR Flash before they are probed by a driver. Signed-off-by: Joachim Eastwood <manabian@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
2015-07-14 06:20:11 +09:00
obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o
memory: add a driver for atmel ram controllers Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks to run. This driver handle those clocks. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-07-09 01:21:12 +09:00
obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
memory: add Atmel EBI (External Bus Interface) driver The EBI (External Bus Interface) is used to access external peripherals (NOR, SRAM, NAND, and other specific devices like ethernet controllers). Each device is assigned a CS line and an address range and can have its own configuration (timings, access mode, bus width, ...). This driver provides a generic DT binding to configure a device according to its requirements. For specific device controllers (like the NAND one) the SMC timings should be configured by the controller driver through the matrix and smc syscon regmaps. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
2016-05-23 16:44:54 +09:00
obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o
memory: ti-aemif: introduce AEMIF driver Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-02-25 02:26:11 +09:00
obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
memory: emif: add basic infrastructure for EMIF driver EMIF is an SDRAM controller used in various Texas Instruments SoCs. EMIF supports, based on its revision, one or more of LPDDR2/DDR2/DDR3 protocols. Add the basic infrastructure for EMIF driver that includes driver registration, probe, parsing of platform data etc. Signed-off-by: Aneesh V <aneesh@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Reviewed-by: Benoit Cousson <b-cousson@ti.com> [santosh.shilimkar@ti.com: Moved to drivers/memory from drivers/misc] Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-04-27 21:24:05 +09:00
obj-$(CONFIG_TI_EMIF) += emif.o
memory: gpmc: Move omap gpmc code to live under drivers Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
2014-11-21 02:13:42 +09:00
obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o
memory: Freescale CoreNet Coherency Fabric error reporting driver The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
2014-07-03 08:52:11 +09:00
obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
driver/memory:Move Freescale IFC driver to a common driver Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-01-17 14:45:16 +09:00
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
drivers: memory: Introduce Marvell EBU Device Bus driver Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2013-04-24 04:21:26 +09:00
obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
ARM: tegra20: Add Tegra Memory Controller(MC) driver Tegra Memory Controller(MC) driver for Tegra20 Added to support MC General interrupts, mainly for IOMMU(GART). Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-05-10 16:42:30 +09:00
obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCs Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780 and later SoCs. The primary function of this driver is to configure parameters, such as timings, for external memory devices using data supplied in the device tree. Devices connected to the NEMC are represented in the DT as children of the NEMC node, the driver uses optional properties specified in these child nodes to configure the parameters of each bank. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2015-03-09 23:29:04 +09:00
obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o
memory: mediatek: Add SMI driver This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-02-23 02:20:49 +09:00
obj-$(CONFIG_MTK_SMI) += mtk-smi.o
memory: davinci: add support for da8xx DDR2/mDDR controller Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> [nsekhar@ti.com: subject line adjustment] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
2016-10-31 23:45:34 +09:00
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
memory: Add NVIDIA Tegra memory controller support The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-16 16:24:44 +09:00
memory: Add support for Exynos SROM driver This patch adds Exynos SROM controller driver which will handle save restore of SROM registers during S2R. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [p.fedin@samsung.com: tested on SMDK5410] Tested-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org> [k.kozlowski: Minor COMPILE_TEST adjustments in Kconfig entries] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-04-11 16:42:24 +09:00
obj-$(CONFIG_SAMSUNG_MC) += samsung/
memory: Add NVIDIA Tegra memory controller support The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-16 16:24:44 +09:00
obj-$(CONFIG_TEGRA_MC) += tegra/
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