84a0124a9d
The Ralink MIPS platform does not use Common Clock Framework and does
not define certain clock operations leading to compile test failures:
/usr/bin/mips-linux-gnu-ld: drivers/usb/phy/phy-tegra-usb.o: in function `tegra_usb_phy_init':
phy-tegra-usb.c:(.text+0x1dd4): undefined reference to `clk_get_parent'
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Acked-by: John Crispin <john@phrozen.org>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
102 lines
1.7 KiB
C
102 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (C) 2013 John Crispin <john@phrozen.org>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <asm/time.h>
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#include "common.h"
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struct clk {
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struct clk_lookup cl;
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unsigned long rate;
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};
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void ralink_clk_add(const char *dev, unsigned long rate)
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{
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struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
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if (!clk)
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panic("failed to add clock");
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clk->cl.dev_id = dev;
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clk->cl.clk = clk;
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clk->rate = rate;
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clkdev_add(&clk->cl);
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}
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/*
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* Linux clock API
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*/
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int clk_enable(struct clk *clk)
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{
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return 0;
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}
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EXPORT_SYMBOL_GPL(clk_enable);
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void clk_disable(struct clk *clk)
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{
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}
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EXPORT_SYMBOL_GPL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (!clk)
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return 0;
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return clk->rate;
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}
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EXPORT_SYMBOL_GPL(clk_get_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return -1;
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}
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EXPORT_SYMBOL_GPL(clk_set_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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return -1;
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}
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EXPORT_SYMBOL_GPL(clk_round_rate);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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WARN_ON(clk);
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return -1;
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}
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EXPORT_SYMBOL_GPL(clk_set_parent);
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struct clk *clk_get_parent(struct clk *clk)
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{
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WARN_ON(clk);
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return NULL;
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}
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EXPORT_SYMBOL_GPL(clk_get_parent);
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void __init plat_time_init(void)
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{
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struct clk *clk;
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ralink_of_remap();
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ralink_clk_init();
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clk = clk_get_sys("cpu", NULL);
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
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mips_hpt_frequency = clk_get_rate(clk) / 2;
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clk_put(clk);
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timer_probe();
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}
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