eea08813f0
This branch is based on V_01-00-59 ## TC956X_Linux_Host_Driver_20230810_V_01-01-59 1. A part of Automotive AVB/TSN support 2. Default Port 0 interface is XFI and Port1 interface is SGMII 3. IPA (macro TC956X_DMA_OFFLOAD_ENABLE) enabled by default 4. Kernel timers are used to process transmitted TX descriptor. Systick timers are not used. 5. Dynamic change of MTU not supported. Max MTU supported is 9000. 6. Port 1 supports USXGMII, XFI and 25000Base-X interface also. ## TC956X_Linux_Host_Driver_20231110_V_01-02-59 1. Kernel 6.1.18 Porting changes 2. TC956x switch to switch connection support (upto 1 level) over DSP ports ## TC956X_Linux_Host_Driver_20231226_V_01-03-59 1. Kernel 6.6.1 Porting changes 2. Added the support for TC commands taprio and flower
132 lines
5.2 KiB
C
132 lines
5.2 KiB
C
/*
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* TC956x XPCS Header
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*
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* tc956x_xpcs.h
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*
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* Copyright (C) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/*! History:
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* 05 Nov 2020 : Initial version
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* VERSION : 00-01
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*
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* 15 Mar 2021 : Base lined
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* VERSION : 01-00
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*
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* 05 Jul 2021 : 1. Used Systick handler instead of Driver kernel timer to process transmitted Tx descriptors.
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* 2. XFI interface support and module parameters for selection of Port0 and Port1 interface
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* VERSION : 01-00-01
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* 15 Jul 2021 : 1. USXGMII/XFI/SGMII/RGMII interface supported without module parameter
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* VERSION : 01-00-02
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* 26 Oct 2021 : 1. Added EEE macros for PHY and MAC Controlled Mode.
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* VERSION : 01-00-19
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* 25 Feb 2022 : 1. Helper function added for XPCS Rx LPI enable/disable
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* VERSION : 01-00-44
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*/
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#ifndef __TC956X_XPCS_H__
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#define __TC956X_XPCS_H__
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#include "common.h"
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#ifdef TC956X
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#define XPCS_XGMAC_OFFSET 0x3A00
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#endif
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/*XPCS registers*/
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#define XGMAC_SR_MII_CTRL 0x7C0000
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#define XGMAC_VR_MII_AN_CTRL 0x7e0004
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#define XGMAC_VR_MII_DIG_CTRL1 0x7e0000
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#define XGMAC_SR_XS_PCS_CTRL1 0xC0000
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#define XGMAC_SR_XS_PCS_STS1 0xC0004
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#define XGMAC_SR_XS_PCS_CTRL2 0xC001C
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#define XGMAC_SR_XS_PCS_EEE_ABL 0xC0050
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#define XGMAC_SR_XS_PCS_STS2 0xC0020
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#define XGMAC_VR_XS_PCS_DIG_CTRL1 0xe0000
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#define XGMAC_VR_XS_PCS_EEE_MCTRL0 0xe0018
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#define XGMAC_VR_XS_PCS_EEE_MCTRL1 0xe002c
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#define XGMAC_VR_XS_PCS_KR_CTRL 0xe001c
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#define XGMAC_VR_XS_PCS_EEE_TXTIMER 0xe0020
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#define XGMAC_VR_XS_PCS_EEE_RXTIMER 0xe0024
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#define XGMAC_VR_XS_PCS_DIG_STS 0xe0040
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#define XGMAC_VR_MII_AN_INTR_STS 0x7e0008
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#define XGMAC_SR_XS_PCS_STS2 0xC0020
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#define XGMAC_LTX_LRX_STATE 0xFC00
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#define XGMAC_LPI_RECEIVE_STATE 0x1C00
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#define XGMAC_LPI_TRANSMIT_STATE 0xE000
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#define XGMAC_RX_LPI_RECEIVE 0x400
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#define XGAMC_TX_LPI_RECEIVE 0x800
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#define XGMAC_LPI_ENABLE 0x0800
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#define XGMAC_PSEQ_STATE 0x001C
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#define XGMAC_KXEEE 0x0010
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#define XGMAC_MULT_FACT_100NS 0x0F00
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#define XGMAC_SIGN_BIT 0x40
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#define XGMAC_TX_RX_EN 0x90
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#define XGMAC_EEE_RX_TIMER 0x3FFF
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#define XGMAC_EEE_TX_TIMER 0x1FFF
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#define XGMAC_TX_RX_QUIET_EN 0x000F
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#define XGMAC_MULT_FACT_100NS_MAC 0xB00
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#define XGMAC_MULT_FACT_100NS_PHY 0xA00
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#define XGMAC_EEE_TX_TIMER_MAC_CONT 0x0543
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#define XGMAC_EEE_TX_TIMER_PHY_CONT 0x0E9C
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#define XGMAC_EEE_RX_TIMER_MAC_CONT 0x062A
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#define XGMAC_EEE_RX_TIMER_PHY_CONT 0x2888
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#define XGMAC_TRN_LPI 0x1
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/*XPCS Register value*/
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#define XGMAC_PCS_MODE_MASK 0xFFFFFFF9
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#define XGMAC_SGMII_MODE 0x00000004
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#define XGMAC_TX_CFIG_INTR_EN_MASK 0xFFFFFFF6/*Mask TX_CONFIG & MII_AN_INTR_EN*/
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#define XGMAC_MII_AN_INTR_EN 0x00000001/*MII_AN_INTR_EN*/
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#define XGMAC_MAC_AUTO_SW_EN 0x00000200/*MAC_AUTO_SW*/
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#define XGMAC_AN_37_ENABLE 0x00001000/*AN_EN*/
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#define XGMAC_PCS_TYPE_SEL 0xFFFFFFF0/*PCS_TYPE_SEL: 0x0000*/
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#define XGMAC_USXG_EN 0x00000200/*USXG_EN enable*/
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#define XGMAC_USXG_MODE 0x00001c00/*USXG_MODE: 0x000*/
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#define XGMAC_VR_RST 0x00008000/*set VR_RST*/
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#define XGMAC_USXG_AN_STS_SPEED_MASK 0x00001c00/*USXGMII autonegotiated speed*/
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#define XGMAC_USXG_AN_STS_DUPLEX_MASK 0x00002000/*USXGMII autonegtiated duplex*/
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#define XGMAC_USXG_AN_STS_LINK_MASK 0x00004000/*USXGMII link status*/
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#define XGMAC_SGM_STS_LINK_MASK 0x00000010/*SGMII link status*/
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#define XGMAC_SGM_STS_DUPLEX 0x00000002/*SGMII autonegotiated duplex*/
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#define XGMAC_SGM_STS_SPEED_MASK 0x0000000c/*SGMII autonegotiated speed*/
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#define XGMAC_SOFT_RST 0x00008000/*SOFT RST*/
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#define XGMAC_C37_AN_COMPL 0x00000001/*C37 Autoneg complete*/
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#define XGMAC_SR_MII_CTRL_SPEED 0x00002060/* SR_MII_CTRL Reg SPEED SS13, SS6, SS5 */
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#define XGMAC_SR_MII_CTRL_SPEED_10G 0x00002040/* SR_MII_CTRL SPEED: 10G */
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#define XGMAC_SR_MII_CTRL_SPEED_5G 0x00002020/* SR_MII_CTRL SPEED: 5G */
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#define XGMAC_SR_MII_CTRL_SPEED_2_5G 0x00000020/* SR_MII_CTRL SPEED: 5G */
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#define XGMAC_USRA_RST 0x400/* USRA_RST */
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#define XGMAC_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
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#define XPCS_REG_BASE_ADDR 10
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#define XPCS_REG_OFFSET 0x0003FF
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#define XPCS_IND_ACCESS 0x3FC
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#define XPCS_SS_SGMII_1G 0x40
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#define XPCS_SS_SGMII_100M 0x2000
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#define XPCS_SS_SGMII_10M 0x0
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u32 tc956x_xpcs_read(void __iomem *xpcsaddr, u32 pcs_reg_num);
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u32 tc956x_xpcs_write(void __iomem *xpcsaddr, u32 pcs_reg_num, u32 value);
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void tc956x_xpcs_ctrl_ane(struct tc956xmac_priv *priv, bool ane);
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int tc956x_xpcs_init(struct tc956xmac_priv *priv, void __iomem *xpcsaddr);
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void tc956x_xpcs_ctrl0_lrx(struct tc956xmac_priv *priv, bool lrx);
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#endif /* __TC956X_XPCS_H__ */
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