Atsushi Nemoto d10e025f0e MIPS: TXx9: Cache fixup
TX39/TX49 can enable/disable I/D cache at runtime.  Add kernel options
to control them.  This is useful to debug some cache-related issues,
such as aliasing or I/D coherency.  Also enable CWF bit for TX49 SoCs.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2008-10-11 16:18:42 +01:00
..
2008-07-30 21:54:43 +01:00
2008-04-28 17:14:32 +01:00
2008-10-11 16:18:41 +01:00
2008-09-21 14:52:56 +02:00
2008-04-28 17:14:25 +01:00
2008-07-15 22:08:52 +02:00
2008-10-11 16:18:41 +01:00
2008-10-11 16:18:42 +01:00