f5792b1dd5
1. Configuring pause frame control using kernel module parameter also forwarding only Link partner pause frames to Application and filtering PHY pause frames using FRP. 2. Returning error on disabling Receive Flow Control via ethtool for speed other than 10G in XFI mode.
148 lines
4.9 KiB
C
148 lines
4.9 KiB
C
/*
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* TC956X PCIe Logging and Statistics header file.
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*
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* tc956x_pcie_logstat.h
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*
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* Copyright (C) 2021 Toshiba Electronic Devices & Storage Corporation
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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/*! History:
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* 17 Sep 2020 : Base lined
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* VERSION : 00-01
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*
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* 15 Mar 2021 : Base lined
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* VERSION : 01-00
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* 14 Oct 2021 : 1. Moving common Macros to common header file
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* VERSION : 01-00-16
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*/
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#ifndef __TC956X_PCIE_LOGSTAT_H__
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#define __TC956X_PCIE_LOGSTAT_H__
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/* ===================================
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* Include
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* ===================================
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*/
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#include "common.h"
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#include "tc956xmac.h"
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#include "tc956xmac_ioctl.h"
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#ifdef TC956X_PCIE_LOGSTAT
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/* ===================================
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* Macros
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* ===================================
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*/
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/* Configuration Register Address */
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#ifdef TC956X
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#define TC956X_CONF_REG_NPCIEUSPLOGCFG (0x00001320U)
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#define TC956X_CONF_REG_NPCIEUSPLOGCTRL (0x00001324U)
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#define TC956X_CONF_REG_NPCIEUSPLOGST (0x00001328U)
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#define TC956X_CONF_REG_NPCIEUSPLOGRDCTRL (0x0000132CU)
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#define TC956X_CONF_REG_NPCIEUSPLOGD (0x00001330U)
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#define LTSSM_CONF_REG_OFFSET (0x20U)
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#endif /* TC956X */
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/* LTSSM Enable Bit Mask Value*/
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#define LTSSM_BIT_MASK (0x00000001U)
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#define LTSSM_PORT_EN_SHIFT (0x4U)
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/* Common NPCIEUSPLOGCFG, NPCIEDSP1LOGCFG, NPCIEDSP2LOGCFG, NPCIEEPLOGCFG
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* register Logging Configuration Bit Mask and Shift Value
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*/
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#define STOP_COUNT_VALUE_MASK (0x00000FF0U)
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#define STOP_COUNT_VALUE_SHIFT (4U)
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#define LINKWIDTH_DOWN_ST_MASK (0x00000008U)
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#define LINKWIDTH_DOWN_ST_SHIFT (3U)
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#define LINKSPEED_DOWN_ST_MASK (0x00000004U)
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#define LINKSPEED_DOWN_ST_SHIFT (2U)
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#define TIMEOUT_STOP_MASK (0x00000002U)
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#define TIMEOUT_STOP_SHIFT (1U)
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#define L0S_MASK_MASK (0x00000001U)
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#define L0S_MASK_SHIFT (0U)
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#define STATE_LOGGING_ENABLE_MASK (0x00000001U)
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#define STATE_LOGGING_ENABLE_SHIFT (0U)
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#define FIFO_READ_POINTER_MASK (0x0000001FU)
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#define FIFO_READ_POINTER_SHIFT (0U)
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#define COUNT_LTSSM_REG_STATES (28U)
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/* Common NPCIEUSPLOGD, NPCIEDSP1LOGD, NPCIEDSP2LOGD, NPCIEEPLOGD
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* Register Logging Read Data Bit Mask and Shift Value
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*/
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#define FIFO_READ_VALUE8_MASK (0x20000000U)
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#define FIFO_READ_VALUE8_SHIFT (29U)
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#define FIFO_READ_VALUE7_MASK (0x10000000U)
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#define FIFO_READ_VALUE7_SHIFT (28U)
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#define FIFO_READ_VALUE6_MASK (0x03000000U)
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#define FIFO_READ_VALUE6_SHIFT (24U)
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#define FIFO_READ_VALUE5_MASK (0x00F00000U)
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#define FIFO_READ_VALUE5_SHIFT (20U)
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#define FIFO_READ_VALUE4_MASK (0x00070000U)
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#define FIFO_READ_VALUE4_SHIFT (16U)
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#define FIFO_READ_VALUE3_MASK (0x0000C000U)
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#define FIFO_READ_VALUE3_SHIFT (14U)
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#define FIFO_READ_VALUE2_MASK (0x00003000U)
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#define FIFO_READ_VALUE2_SHIFT (12U)
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#define FIFO_READ_VALUE1_MASK (0x00000300U)
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#define FIFO_READ_VALUE1_SHIFT (8U)
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#define FIFO_READ_VALUE0_MASK (0x0000001FU)
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#define FIFO_READ_VALUE0_SHIFT (0U)
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#define STOP_STATUS_MASK (0x00000001U)
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#define STOP_STATUS_SHIFT (0U)
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/* Common NPCIEUSPLOGD, NPCIEDSP1LOGD, NPCIEDSP2LOGD, NPCIEEPLOGD
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* Register, Different Lanes Bit Mask Values
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*/
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#define LANE0_MASK (0x1U)
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#define LANE0_SHIFT (0U)
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#define LANE1_MASK (0x2U)
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#define LANE1_SHIFT (1U)
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#define LANE2_MASK (0x4U)
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#define LANE2_SHIFT (2U)
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#define LANE3_MASK (0x8U)
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#define LANE3_SHIFT (3U)
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#define MAX_STOP_CNT (0xFFU)
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#define MAX_FIFO_POINTER (31U)
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/* ===================================
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* Function Declaration
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* ===================================
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*/
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int tc956x_logstat_SetConf(void __iomem *pconf_base_addr,
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enum ports nport,
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struct tc956x_ltssm_conf *plogstat_conf);
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int tc956x_logstat_GetConf(void __iomem *pconf_base_addr,
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enum ports nport,
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struct tc956x_ltssm_conf *plogstat_conf);
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int tc956x_logstat_GetLTSSMLogData(void __iomem *pbase_addr,
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enum ports nport,
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struct tc956x_ltssm_log *plogstat_conf);
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int tc956x_pcie_ioctl_SetDbgConf(const struct tc956xmac_priv *priv,
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void __user *data);
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int tc956x_pcie_ioctl_GetDbgConf(const struct tc956xmac_priv *priv,
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void __user *data);
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int tc956x_pcie_ioctl_GetLTSSMLogD(const struct tc956xmac_priv *priv,
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void __user *data);
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#endif /* #ifdef TC956X_PCIE_LOGSTAT */
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#endif /* __TC956X_PCIE_LOGSTAT_H__ */
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