98d2d3a264
The core houses infrastructure for decoder resources. A CXL port's dports are more closely related to decoder infrastructure than topology enumeration. Implement generic PCI based dport enumeration in the core, i.e. arrange for existing root port enumeration from cxl_acpi to share code with switch port enumeration which just amounts to a small difference in a pci_walk_bus() invocation once the appropriate 'struct pci_bus' has been retrieved. Set the convention that decoder objects are registered after all dports are enumerated. This enables userspace to know when the CXL core is finished establishing 'dportX' links underneath the 'portX' object. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Link: https://lore.kernel.org/r/164368114191.354031.5270501846455462665.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef __CXL_PCI_H__
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#define __CXL_PCI_H__
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#include "cxl.h"
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#define CXL_MEMORY_PROGIF 0x10
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/*
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* See section 8.1 Configuration Space Registers in the CXL 2.0
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* Specification. Names are taken straight from the specification with "CXL" and
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* "DVSEC" redundancies removed. When obvious, abbreviations may be used.
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*/
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#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
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#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
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/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
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#define CXL_DVSEC_PCIE_DEVICE 0
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/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
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#define CXL_DVSEC_FUNCTION_MAP 2
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/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
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#define CXL_DVSEC_PORT_EXTENSIONS 3
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/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
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#define CXL_DVSEC_PORT_GPF 4
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/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
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#define CXL_DVSEC_DEVICE_GPF 5
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/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
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#define CXL_DVSEC_PCIE_FLEXBUS_PORT 7
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/* CXL 2.0 8.1.9: Register Locator DVSEC */
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#define CXL_DVSEC_REG_LOCATOR 8
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#define CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET 0xC
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#define CXL_DVSEC_REG_LOCATOR_BIR_MASK GENMASK(2, 0)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK GENMASK(15, 8)
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#define CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK GENMASK(31, 16)
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/* Register Block Identifier (RBI) */
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enum cxl_regloc_type {
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CXL_REGLOC_RBI_EMPTY = 0,
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CXL_REGLOC_RBI_COMPONENT,
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CXL_REGLOC_RBI_VIRT,
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CXL_REGLOC_RBI_MEMDEV,
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CXL_REGLOC_RBI_TYPES
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};
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static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
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struct cxl_register_map *map)
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{
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if (map->block_offset == U64_MAX)
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return CXL_RESOURCE_NONE;
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return pci_resource_start(pdev, map->barno) + map->block_offset;
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}
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int devm_cxl_port_enumerate_dports(struct device *host, struct cxl_port *port);
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#endif /* __CXL_PCI_H__ */
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