Neil Armstrong 90b171f603 clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks,
CCF will use the SYS_PLL to handle these frequencies, but:
- using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise
- the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't
  handle entering suspend using SYS_PLL for these frequencies

Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL
cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source
for these frequencies.

Fixes: ffae8475b90c ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01 14:51:15 +02:00
..
2019-09-17 22:53:34 -07:00
2019-09-22 09:30:30 -07:00
2019-05-30 16:33:37 -07:00
2019-09-20 15:53:02 -07:00
2019-05-16 09:19:14 -07:00
2019-09-06 15:22:29 -07:00
2018-12-11 09:57:47 -08:00
2019-05-07 11:46:02 -07:00
2019-04-26 10:40:49 -07:00
2018-07-06 13:44:06 -07:00
2019-05-07 11:46:02 -07:00
2019-07-15 20:18:40 -07:00
2019-09-06 15:22:29 -07:00