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android_kernel_samsung_sm8650/arch/riscv/kernel
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Kefeng Wang 7d0ce3b2b4 riscv: sbi: Fix undefined reference to sbi_shutdown 
There is no shutdown call in SBI v0.2, only set pm_power_off
when RISCV_SBI_V01 enabled to fix following build error,

riscv64-linux-ld: arch/riscv/kernel/sbi.o: in function `sbi_power_off':
sbi.c:(.text+0xe): undefined reference to `sbi_shutdown

Fixes: efca13989250 ("RISC-V: Introduce a new config for SBI v0.1")
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-04-21 16:15:09 -07:00
..
vdso
riscv: fix vdso build with lld
2020-04-21 15:22:45 -07:00
.gitignore
.gitignore: add SPDX License Identifier
2020-03-25 11:50:48 +01:00
asm-offsets.c
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
cacheinfo.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
clint.c
riscv: provide native clint access for M-mode
2019-11-17 15:17:39 -08:00
cpu_ops_sbi.c
RISC-V: Support cpu hotplug
2020-03-31 11:28:30 -07:00
cpu_ops_spinwait.c
RISC-V: Add cpu_ops and modify default booting method
2020-03-31 11:25:56 -07:00
cpu_ops.c
RISC-V: Add supported for ordered booting method using HSM
2020-03-31 11:27:50 -07:00
cpu-hotplug.c
RISC-V: Support cpu hotplug
2020-03-31 11:28:30 -07:00
cpu.c
RISC-V: Remove unsupported isa string info print
2019-10-28 11:13:59 -07:00
cpufeature.c
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
entry.S
RISC-V Patches for the 5.7 Merge Window, Part 1
2020-04-09 10:51:30 -07:00
fpu.S
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
ftrace.c
riscv: patch code by fixmap mapping
2020-03-26 09:24:55 -07:00
head.h
riscv: add prototypes for assembly language functions from head.S
2019-10-28 00:46:00 -07:00
head.S
riscv: Add SOC early init support
2020-04-03 10:46:43 -07:00
irq.c
riscv: prefix IRQ_ macro names with an RV_ namespace
2020-01-04 21:48:59 -08:00
Makefile
riscv: Add SOC early init support
2020-04-03 10:46:43 -07:00
mcount-dyn.S
riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support
2018-04-02 19:59:13 -07:00
mcount.S
RISC-V: remove the unused return_to_handler export
2018-10-22 17:38:12 -07:00
module-sections.c
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
module.c
riscv: avoid the PIC offset of static percpu data in module beyond 2G limits
2020-03-03 10:27:45 -08:00
module.lds
RISC-V: Add section of GOT.PLT for kernel module
2018-04-02 20:00:54 -07:00
patch.c
riscv: introduce interfaces to patch kernel code
2020-03-26 09:24:52 -07:00
perf_callchain.c
riscv: abstract out CSR names for supervisor vs machine mode
2019-11-05 09:20:42 -08:00
perf_event.c
RISC-V: Access CSRs using CSR numbers
2019-05-16 20:42:11 -07:00
perf_regs.c
riscv: Add support for perf registers sampling
2019-09-05 00:48:58 -07:00
process.c
RISC-V: Stop relying on GCC's register allocator's hueristics
2020-03-03 10:28:13 -08:00
ptrace.c
riscv: fix seccomp reject syscall code path
2020-03-05 13:58:15 -08:00
reset.c
riscv: cleanup the default power off implementation
2019-11-13 13:22:52 -08:00
riscv_ksyms.c
riscv: Add KASAN support
2020-01-22 13:09:58 -08:00
sbi.c
riscv: sbi: Fix undefined reference to sbi_shutdown
2020-04-21 16:15:09 -07:00
setup.c
RISC-V: Support cpu hotplug
2020-03-31 11:28:30 -07:00
signal.c
riscv: add nommu support
2019-11-17 15:17:39 -08:00
smp.c
riscv: fix the IPI missing issue in nommu mode
2020-03-18 18:44:39 -07:00
smpboot.c
RISC-V: Add supported for ordered booting method using HSM
2020-03-31 11:27:50 -07:00
soc.c
riscv: Add SOC early init support
2020-04-03 10:46:43 -07:00
stacktrace.c
RISC-V: stacktrace: Declare sp_in_global outside ifdef
2020-04-21 10:50:45 -07:00
sys_riscv.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286
2019-06-05 17:36:37 +02:00
syscall_table.c
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
time.c
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
traps_misaligned.c
riscv: Unaligned load/store handling for M_MODE
2020-04-03 10:45:33 -07:00
traps.c
RISC-V Patches for the 5.7 Merge Window, Part 1
2020-04-09 10:51:30 -07:00
vdso.c
riscv: add missing header file includes
2019-10-28 00:46:01 -07:00
vmlinux.lds.S
riscv: Add SOC early init support
2020-04-03 10:46:43 -07:00