Mark Brown 0182dcc52c ASoC: Fix WM8993 MCLK configuration for high frequency MCLKs
When used without the PLL we were accidentally clearing the MCLK/2
divider, resulting in a double rate SYSCLK when the divider should
have been used.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
2009-08-17 18:53:44 +01:00
..
2009-03-30 15:21:59 +02:00
2009-02-05 15:08:53 +01:00
2008-01-31 17:29:48 +01:00
2007-05-21 09:18:19 -07:00