e8ee6c8cb6
DW DMA IP-core provides a way to synthesize the DMA controller with channels having different parameters like maximum burst-length, multi-block support, maximum data width, etc. Those parameters both explicitly and implicitly affect the channels performance. Since DMA slave devices might be very demanding to the DMA performance, let's provide a functionality for the slaves to be assigned with DW DMA channels, which performance according to the platform engineer fulfill their requirements. After this patch is applied it can be done by passing the mask of suitable DMA-channels either directly in the dw_dma_slave structure instance or as a fifth cell of the DMA DT-property. If mask is zero or not provided, then there is no limitation on the channels allocation. For instance Baikal-T1 SoC is equipped with a DW DMAC engine, which first two channels are synthesized with max burst length of 16, while the rest of the channels have been created with max-burst-len=4. It would seem that the first two channels must be faster than the others and should be more preferable for the time-critical DMA slave devices. In practice it turned out that the situation is quite the opposite. The channels with max-burst-len=4 demonstrated a better performance than the channels with max-burst-len=16 even when they both had been initialized with the same settings. The performance drop of the first two DMA-channels made them unsuitable for the DW APB SSI slave device. No matter what settings they are configured with, full-duplex SPI transfers occasionally experience the Rx FIFO overflow. It means that the DMA-engine doesn't keep up with incoming data pace even though the SPI-bus is enabled with speed of 25MHz while the DW DMA controller is clocked with 50MHz signal. There is no such problem has been noticed for the channels synthesized with max-burst-len=4. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20200731200826.9292-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Vinod Koul <vkoul@kernel.org>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Driver for the Synopsys DesignWare DMA Controller
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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*/
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#ifndef _PLATFORM_DATA_DMA_DW_H
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#define _PLATFORM_DATA_DMA_DW_H
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#include <linux/bits.h>
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#include <linux/types.h>
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#define DW_DMA_MAX_NR_MASTERS 4
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#define DW_DMA_MAX_NR_CHANNELS 8
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#define DW_DMA_MIN_BURST 1
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#define DW_DMA_MAX_BURST 256
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struct device;
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @src_id: src request line
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* @dst_id: dst request line
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* @m_master: memory master for transfers on allocated channel
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* @p_master: peripheral master for transfers on allocated channel
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* @channels: mask of the channels permitted for allocation (zero value means any)
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* @hs_polarity:set active low polarity of handshake interface
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u8 src_id;
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u8 dst_id;
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u8 m_master;
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u8 p_master;
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u8 channels;
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bool hs_polarity;
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};
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (in bytes, power of 2)
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* @multi_block: Multi block transfers supported by hardware per channel.
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* @max_burst: Maximum value of burst transaction size supported by hardware
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* per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
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* @protctl: Protection control signals setting per channel.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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unsigned int block_size;
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unsigned char nr_masters;
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unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
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unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS];
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u32 max_burst[DW_DMA_MAX_NR_CHANNELS];
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#define CHAN_PROTCTL_PRIVILEGED BIT(0)
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#define CHAN_PROTCTL_BUFFERABLE BIT(1)
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#define CHAN_PROTCTL_CACHEABLE BIT(2)
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#define CHAN_PROTCTL_MASK GENMASK(2, 0)
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unsigned char protctl;
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};
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#endif /* _PLATFORM_DATA_DMA_DW_H */
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