android_kernel_samsung_sm8650

Author	SHA1	Message	Date
Stephen Boyd	f9efefdba9	Merge branches 'clk-baikal', 'clk-broadcom', 'clk-vc5' and 'clk-versaclock' into clk-next - Convert Baikal-T1 CCU driver to platform driver - Split reset support out of primary Baikal-T1 CCU driver - Add some missing clks required for RPiVid Video Decoder on RaspberryPi - Mark PLLC critical on bcm2835 - Support for Renesas VersaClock7 clock generator family * clk-baikal: clk: baikal-t1: Convert to platform device driver clk: baikal-t1: Add DDR/PCIe directly controlled resets support dt-bindings: clk: baikal-t1: Add DDR/PCIe reset IDs clk: baikal-t1: Move reset-controls code into a dedicated module clk: baikal-t1: Add SATA internal ref clock buffer clk: baikal-t1: Add shared xGMAC ref/ptp clocks internal parent clk: baikal-t1: Fix invalid xGMAC PTP clock divider clk: vc5: Fix 5P49V6901 outputs disabling when enabling FOD * clk-broadcom: clk: bcm: rpi: Add support for VEC clock clk: bcm: rpi: Handle pixel clock in firmware clk: bcm: rpi: Add support HEVC clock clk: bcm2835: fix bcm2835_clock_rate_from_divisor declaration clk: bcm2835: Round UART input clock up clk: bcm2835: Make peripheral PLLC critical * clk-vc5: clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975 dt-bindings: clock: vc5: Add 5P49V6975 clk: vc5: Use regmap_{set,clear}_bits() where appropriate clk: vc5: Check IO access results * clk-versaclock: clk: Renesas versaclock7 ccf device driver dt-bindings: Renesas versaclock7 device tree bindings	2022-10-04 10:54:34 -07:00
Stephen Boyd	26bebbfed5	Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next * clk-rockchip: dt-bindings: clock: rockchip: change SPDX-License-Identifier dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML clk: rockchip: Add clock controller support for RV1126 SoC dt-bindings: clock: rockchip: Document RV1126 CRU clk: rockchip: Add dt-binding header for RV1126 clk: rockchip: Add MUXTBL variant * clk-renesas: clk: renesas: r8a779g0: Add EtherAVB clocks clk: renesas: r8a779g0: Add PFC/GPIO clocks clk: renesas: r8a779g0: Add I2C clocks clk: renesas: r8a779g0: Add watchdog clock dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC clk: renesas: r8a779f0: Add MSIOF clocks clk: renesas: r9a09g011: Add IIC clock and reset entries clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks clk: renesas: r8a779f0: Add CMT clocks clk: renesas: r8a779f0: Add SDH0 clock * clk-microchip: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation * clk-allwinner: clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper clk: sunxi-ng: d1: Limit PLL rates to stable ranges * clk-imx: clk: imx: scu: fix memleak on platform_device_add() fails clk: imx93: add SAI IPG clk clk: imx93: add MU1/2 clock clk: imx93: switch to use new clk gate API clk: imx: add i.MX93 clk gate clk: imx: clk-composite-93: check white_list clk: imx: clk-composite-93: check slice busy dt-bindings: clock: imx93-clock: add more MU/SAI clocks dt-bindings: clock: imx8mm: don't use multiple blank lines clk: imx8mp: tune the order of enet_qos_root_clk	2022-10-04 10:54:02 -07:00
Stephen Boyd	a64b79c01c	Merge branches 'clk-samsung', 'clk-mtk', 'clk-rm', 'clk-ast' and 'clk-qcom' into clk-next - Add resets for MediaTek MT8195 PCIe and USB - Remove DaVinci DM644x and DM646x clk driver support * clk-samsung: clk: samsung: MAINTAINERS: add Krzysztof Kozlowski clk: samsung: exynos850: Implement CMU_MFCMSCL domain clk: samsung: exynos850: Implement CMU_IS domain clk: samsung: exynos850: Implement CMU_AUD domain clk: samsung: exynos850: Style fixes clk: samsung: exynosautov9: add fsys1 clock support clk: samsung: exynosautov9: add fsys0 clock support clk: samsung: exynosautov9: correct register offsets of peric0/c1 clk: samsung: exynosautov9: add missing gate clks for peric0/c1 dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL dt-bindings: clock: exynos850: Add Exynos850 CMU_IS dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 dt-bindings: clock: exynosautov9: add fsys1 clock definitions dt-bindings: clock: exynosautov9: add fys0 clock definitions clk: samsung: exynos7885: Add TREX clocks clk: samsung: exynos7885: Implement CMU_FSYS domain dt-bindings: clock: exynosautov9: correct clock numbering of peric0/c1 clk: samsung: exynos-clkout: Use of_device_get_match_data() * clk-mtk: (42 commits) clk: mediatek: add driver for MT8365 SoC clk: mediatek: Export required common code symbols clk: mediatek: Provide mtk_devm_alloc_clk_data dt-bindings: clock: mediatek: add bindings for MT8365 SoC clk: mediatek: mt8192: deduplicate parent clock lists clk: mediatek: Migrate remaining clk_unregister_() to clk_hw_unregister_() clk: mediatek: fix unregister function in mtk_clk_register_dividers cleanup clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes clk: mediatek: mt8183: Add clk mux notifier for MFG mux clk: mediatek: mux: add clk notifier functions clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent clk: mediatek: Use mtk_clk_register_gates_with_dev in simple probe clk: mediatek: gate: Export mtk_clk_register_gates_with_dev clk: mediatek: add VDOSYS1 clock dt-bindings: clk: mediatek: Add MT8195 DPI clocks ... * clk-rm: clk: davinci: remove PLL and PSC clocks for DaVinci DM644x and DM646x * clk-ast: clk: ast2600: BCLK comes from EPLL * clk-qcom: (97 commits) clk: qcom: gcc-sm6375: Ensure unsigned long type clk: qcom: gcc-sm6375: Remove unused variables clk: qcom: kpss-xcc: convert to parent data API clk: introduce (devm_)hw_register_mux_parent_data_table API clk: qcom: gcc-msm8939: use ARRAY_SIZE instead of specifying num_parents clk: qcom: gcc-msm8939: use parent_hws where possible dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml clk: qcom: gcc-sm6350: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc8280xp: use retention for USB power domains clk: qcom: gdsc: add missing error handling dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos clk: qcom: Add global clock controller driver for SM6375 dt-bindings: clock: add SM6375 QCOM global clock bindings clk: qcom: alpha: Add support for programming the PLL_FSM_LEGACY_MODE bit clk: qcom: gcc-sc7280: Update the .pwrsts for usb gdscs clk: qcom: gcc-sc7180: Update the .pwrsts for usb gdsc clk: qcom: gdsc: Fix the handling of PWRSTS_RET support clk: qcom: Add SC8280XP GPU clock controller dt-bindings: clock: Add Qualcomm SC8280XP GPU binding clk: qcom: smd: Add SM6375 clocks ...	2022-10-04 10:53:41 -07:00
Stephen Boyd	49f4c2d101	Merge branches 'clk-ofnode', 'clk-bindings', 'clk-cleanup', 'clk-zynq' and 'clk-xilinx' into clk-next - Miscellaneous of_node_put() fixes - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock - Convert gpio-clk-gate binding to YAML - Various fixes to AMD/Xilinx Zynqmp clk driver - Graduate AMD/Xilinx "clocking wizard" driver from staging * clk-ofnode: clk: ti: Balance of_node_get() calls for of_find_node_by_name() clk: tegra20: Fix refcount leak in tegra20_clock_init clk: tegra: Fix refcount leak in tegra114_clock_init clk: tegra: Fix refcount leak in tegra210_clock_init clk: sprd: Hold reference returned by of_get_parent() clk: berlin: Add of_node_put() for of_get_parent() clk: at91: dt-compat: Hold reference returned by of_get_parent() clk: qoriq: Hold reference returned by of_get_parent() clk: oxnas: Hold reference returned by of_get_parent() clk: st: Hold reference returned by of_get_parent() clk: tegra: Add missing of_node_put() clk: meson: Hold reference returned by of_get_parent() clk: nomadik: Add missing of_node_put() * clk-bindings: dt-bindings: clock: drop minItems equal to maxItems dt-bindings: clock: gpio-gate-clock: Convert to json-schema dt-bindings: clock: Move versaclock.h to dt-bindings/clock dt-bindings: clock: Move lochnagar.h to dt-bindings/clock * clk-cleanup: clk: allow building lan966x as a module clk: clk-xgene: simplify if-if to if-else clk: nxp: fix typo in comment clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe clkdev: Simplify devm_clk_hw_register_clkdev() function clkdev: Remove never used devm_clk_release_clkdev() clk: Remove never used devm_of_clk_del_provider() clk: pistachio: Fix initconst confusion clk: clk-npcm7xx: Remove unused struct npcm7xx_clk_gate_data and npcm7xx_clk_div_fixed_data clk: do not initialize ret clk: remove extra empty line clk: Fix comment typo clk: move from strlcpy with unused retval to strscpy * clk-zynq: clk: zynqmp: pll: rectify rate rounding in zynqmp_pll_round_rate clk: zynqmp: Check the return type zynqmp_pm_query_data clk: zynqmp: Add a check for NULL pointer clk: zynqmp: Replaced strncpy() with strscpy() clk: zynqmp: Fix stack-out-of-bounds in strncpy` clk: zynqmp: make bestdiv unsigned * clk-xilinx: clk: clocking-wizard: Depend on HAS_IOMEM clk: clocking-wizard: Use dev_err_probe() helper clk: clocking-wizard: Update the compatible clk: clocking-wizard: Fix the reconfig for 5.2 clk: clocking-wizard: Rename nr-outputs to xlnx,nr-outputs clk: clocking-wizard: Move clocking-wizard out dt-bindings: add documentation of xilinx clocking wizard	2022-10-04 10:53:04 -07:00
Matthias Fend	f0fa3a3614	dt-bindings: clock: vc5: Add 5P49V6975 The 5P49V6975 is a member of the VersaClock 6E family and supports four fractional dividers (FODs), five clock outputs and an internal oscillator. Signed-off-by: Matthias Fend <matthias.fend@emfend.at> Link: https://lore.kernel.org/r/20220511053455.360335-1-matthias.fend@emfend.at Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-10-03 11:58:15 -07:00
Alex Helms	09d1855656	dt-bindings: Renesas versaclock7 device tree bindings Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms <alexander.helms.jy@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220912183613.22213-2-alexander.helms.jy@renesas.com Tested-by: Saeed Nowshadi <saeed.nowshadi@amd.com> [sboyd@kernel.org: Rename nodes in example to generic names] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-09-30 17:34:20 -07:00
Fabien Parent	c61978175a	dt-bindings: clock: mediatek: add bindings for MT8365 SoC Add the clock bindings for the MediaTek MT8365 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> Link: https://lore.kernel.org/r/20220822152652.3499972-2-msp@baylibre.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-09-30 15:07:43 -07:00
Dmitry Baryshkov	2ab5b56638	dt-bindings: clock: move qcom,gcc-msm8939 to qcom,gcc-msm8916.yaml The MSM8939 GCC bindings are fully comptible with MSM8916, the clock controller requires the same parent clocks, move MSM8939 GCC compatible to qcom,msm8916.yaml Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220928145609.375860-2-dmitry.baryshkov@linaro.org	2022-09-29 11:42:11 -05:00
Andrew Halaney	6632a6adae	dt-bindings: clocks: qcom,gcc-sc8280xp: Fix typos pipegmux and SuperSpeed are the proper spelling for those terms. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921153155.279182-1-ahalaney@redhat.com	2022-09-27 22:47:10 -05:00
Konrad Dybcio	43398afc0b	dt-bindings: clock: add SM6375 QCOM global clock bindings Add device tree bindings for global clock controller for SM6375 SoCs. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921001303.56151-2-konrad.dybcio@somainline.org	2022-09-27 22:25:57 -05:00
Bjorn Andersson	9f60eb3ec0	dt-bindings: clock: Add Qualcomm SC8280XP GPU binding Add compatible for the Qualcomm SC8280XP GPU. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220926173025.4747-2-quic_bjorande@quicinc.com	2022-09-27 12:07:30 -05:00
Konrad Dybcio	de55ec3b3a	dt-bindings: clock: qcom,rpmcc: Add compatible for SM6375 Add a compatible for RPMCC on SM6375. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220921004458.151842-1-konrad.dybcio@somainline.org	2022-09-27 12:07:17 -05:00
Richard Acayan	c6648a402c	dt-bindings: clock: add rpmhcc bindings for sdm670 The Snapdragon 670 uses the RPMh mailbox for some clocks. Document its support. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220920223734.151135-2-mailingradian@gmail.com	2022-09-27 11:40:29 -05:00
Krzysztof Kozlowski	46e0962ff2	dt-bindings: clock: qcom,a53pll: replace maintainer Emails to codeaurora.org bounce ("Recipient address rejected: undeliverable address: No such user here."). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220924081329.15141-1-krzysztof.kozlowski@linaro.org	2022-09-26 22:43:51 -05:00
Dmitry Baryshkov	a7edd29163	dt-bindings: clock: qcom: add bindings for dispcc on SM8450 Add device tree bindings for the display clock controller on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220908222850.3552050-2-dmitry.baryshkov@linaro.org	2022-09-26 22:17:14 -05:00
Adam Skladowski	38557c6fc0	dt-bindings: clock: add QCOM SM6115 display clock bindings Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM6115 SoC. Signed-off-by: Adam Skladowski <a39.skl@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> [bjorn: Minor fix of binding description] Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220911164635.182973-2-a39.skl@gmail.com	2022-09-26 22:17:13 -05:00
Robert Marko	d522c77aa8	dt-bindings: clock: qcom,a53pll: add IPQ8074 compatible Add IPQ8074 compatible to A53 PLL bindings. Signed-off-by: Robert Marko <robimarko@gmail.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220818220628.339366-4-robimarko@gmail.com	2022-09-26 21:40:10 -05:00
Yassine Oudjana	b4feed4a3d	dt-bindings: clock: qcom,msm8996-apcc: Fix clocks The clocks currently listed in clocks and clock-names are the ones supplied by this clock controller, not the ones it consumes. Replace them with the only clock it consumes - the on-board oscillator (XO), and make the properties required. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220621160621.24415-6-y.oudjana@protonmail.com	2022-09-26 11:12:35 -05:00
AngeloGioacchino Del Regno	e629bf40d3	dt-bindings: clock: mediatek: Add clock driver bindings for MT6795 Add the bindings for the clock drivers of the MediaTek Helio X10 MT6795 SoC. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-5-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>	2022-09-26 11:13:09 +08:00
AngeloGioacchino Del Regno	d5099c95c9	dt-bindings: mediatek: Document MT6795 system controllers bindings Document the MediaTek Helio X10 (MT6795) bindings for the apmixedsys, infracfg, topckgen, pericfg and mmsys system controllers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220921091455.41327-2-angelogioacchino.delregno@collabora.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>	2022-09-26 11:13:09 +08:00
Johan Jonker	fffa0fa4d0	dt-bindings: clock: rockchip: change SPDX-License-Identifier Change SPDX-License-Identifier to (GPL-2.0+ OR MIT) for Rockchip clock bindings. Cc: Heiko Stübner <heiko@sntech.de> Cc: Elaine Zhang <zhangqing@rock-chips.com> Cc: Xing Zheng <zhengxing@rock-chips.com> Cc: Jeffy Chen <jeffy.chen@rock-chips.com> Cc: Finley Xiao <finley.xiao@rock-chips.com> Cc: Andy Yan <andy.yan@rock-chips.com> Cc: Shawn Lin <shawn.lin@rock-chips.com> Cc: Eric Engestrom <eric@engestrom.ch> Cc: Mylène Josserand <mylene.josserand@collabora.com> Cc: Nícolas F. R. A. Prado <nfraprado@collabora.com> Signed-off-by: Johan Jonker <jbx6244@gmail.com> Acked-by: Eric Engestrom <eric@engestrom.ch> Acked-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20c6a502-2ff5-bdb1-fb4f-0741f3a2c19c@gmail.com [Rockchip Ack/request for dual licensing dt-bindings at https://lore.kernel.org/all/510d1180-bc8e-7820-c772-ed7f35447087@rock-chips.com/] Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2022-09-23 20:48:01 +02:00
Johan Jonker	f878a26a2a	dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML Convert rockchip,rk3128-cru.txt to YAML. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/4e69a06d-7b53-ab48-1e50-2b29ff3a54e6@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2022-09-23 12:28:49 +02:00
Jagan Teki	a1f65e64c6	dt-bindings: clock: rockchip: Document RV1126 CRU Document dt-bindings for Rockchip RV1126 clock controller. Cc: linux-clk@vger.kernel.org Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Link: https://lore.kernel.org/r/20220915163947.1922183-4-jagan@edgeble.ai Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2022-09-17 16:29:17 +02:00
Conor Dooley	3ffb5ad24d	dt-bindings: clk: document PolarFire SoC fabric clocks On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the ordinal corners of the chip, which our documentation refers to as "Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are highly configurable & many of the input clocks are optional. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-3-conor.dooley@microchip.com	2022-09-14 10:57:07 +03:00
Conor Dooley	803307a452	dt-bindings: clk: rename mpfs-clkcfg binding The filename for a binding is supposed to match the first compatible, but the mpfs-clkcfg file did not follow this policy. Rename it to match so that when other mpfs clock bindings are added things make more sense. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220908143651.1252601-2-conor.dooley@microchip.com	2022-09-14 10:57:07 +03:00
Conor Dooley	89b16523d9	dt-bindings: clk: microchip: mpfs: add reset controller support The "peripheral" devices on PolarFire SoC can be put into reset, so update the device tree binding to reflect the presence of a reset controller. Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220909123123.2699583-4-conor.dooley@microchip.com	2022-09-14 10:55:17 +03:00
Stephan Gerhold	1727a402c1	dt-bindings: clock: qcom,rpmcc: Add MSM8909 Document the "qcom,rpmcc-msm8909" compatible for the clocks available via the RPM on the MSM8909 SoC. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-6-stephan.gerhold@kernkonzept.com	2022-09-13 22:07:25 -05:00
Stephan Gerhold	c40668048f	dt-bindings: clock: Add schema for MSM8909 GCC The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a DT schema to describe it, similar to other Qualcomm SoCs. Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220706134132.3623415-2-stephan.gerhold@kernkonzept.com	2022-09-13 22:07:25 -05:00
Dmitry Baryshkov	861466d4fb	dt-bindings: clocks: qcom,mmcc: define clocks/clock-names for MSM8960 Define clock/clock-names properties of the MMCC device node to be used on MSM8960/APQ8064 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-3-dmitry.baryshkov@linaro.org	2022-09-13 21:58:34 -05:00
Dmitry Baryshkov	e18e181ca5	dt-bindings: clocks: qcom,gcc-apq8064: define clocks/-names properties Define clock/clock-names properties of the GCC device node to be used on MSM8960/APQ8064 platforms. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Tested-by: David Heidelberg <david@ixit.cz> # tested on Nexus 7 (2013) Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220623120418.250589-2-dmitry.baryshkov@linaro.org	2022-09-13 21:58:18 -05:00
Richard Acayan	657e932665	dt-bindings: clock: gcc-sdm845: add sdm670 global clocks The Snapdragon 670 clocks will be added into the sdm845 gcc driver. Most of the new clocks, GDSCs, and resets already have reserved IDs but there are some resources that don't. Add the new clock from Snapdragon 670 and document the differences between the SoC parent clocks. Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220914013922.198778-2-mailingradian@gmail.com	2022-09-13 21:20:33 -05:00
Dmitry Baryshkov	c027fa892b	dt-bindings: clock: qcom,gcc-msm8660: separate GCC bindings for MSM8660 Create a separate DT bindings for Global Clock Controller on MSM8660 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220909105136.3733919-2-dmitry.baryshkov@linaro.org	2022-09-13 16:44:54 -05:00
Bjorn Andersson	adb12f0636	Merge branch '1662005846-4838-1-git-send-email-quic_c_skakit@quicinc.com' into clk-for-6.1	2022-09-13 09:48:16 -05:00
Taniya Das	be9439df23	dt-bindings: clock: Add resets for LPASS audio clock controller for SC7280 Add support for LPASS audio clock gating for RX/TX/SWA core bus clocks for SC7280. Update reg property min/max items in YAML schema. Fixes: 4185b27b3bef ("dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7280") Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662005846-4838-4-git-send-email-quic_c_skakit@quicinc.com	2022-09-13 09:47:35 -05:00
Taniya Das	7afdf3afff	dt-bindings: clock: Add "qcom,adsp-pil-mode" property When this property is set, the remoteproc is used to boot the LPASS and therefore lpass_q6ss_ahbm_clk and lpass_q6ss_ahbs_clk clocks would be used to bring LPASS out of reset and the rest of the lpass clocks would be controlled directly by the remoteproc. This is a cleanup done to handle overlap of regmap of lpasscc and lpass_aon blocks. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya <quic_c_skakit@quicinc.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/1662005846-4838-2-git-send-email-quic_c_skakit@quicinc.com	2022-09-13 09:47:35 -05:00
Lad Prabhakar	e312ae9207	dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC The CPG block on the RZ/Five SoC is almost identical to one found on the RZ/G2UL SoC. "renesas,r9a07g043-cpg" compatible string will be used on the RZ/Five SoC so to make this clear, update the comment to include RZ/Five SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220726174525.620-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>	2022-09-02 10:47:30 +02:00
Krzysztof Kozlowski	4bafca8313	dt-bindings: clock: drop minItems equal to maxItems minItems, if missing, are implicitly equal to maxItems, so drop redundant piece to reduce size of code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220825113334.196908-3-krzysztof.kozlowski@linaro.org Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-08-30 15:07:08 -07:00
Dmitry Baryshkov	51b0a5e044	dt-bindings: clock: qcom,mmcc: define clocks/clock-names for MSM8996 Define clock/clock-names properties of the MMCC device node to be used on MSM8996 platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220705112734.1323355-3-dmitry.baryshkov@linaro.org	2022-08-29 15:43:40 -05:00
Dmitry Baryshkov	73e66ddfd9	dt-bindings: clock: qcom,mmcc: fix clocks/clock-names definitions Rather than defining (incorrect) global clocks and clock-names lists, define them per platform using conditionals. Also, while we are at it, mark these properties as required for all platforms for which DT files contained clocks/clock-names for the MMCC nodes from the beginning (in addition to existing MSM8998 this adds MSM8994, SDM630 and SDM660). Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220705112734.1323355-2-dmitry.baryshkov@linaro.org	2022-08-29 15:43:39 -05:00
Dmitry Baryshkov	bdeb3cf013	dt-bindings: clock: separate bindings for MSM8916 GCC device Separate bindings for GCC on Qualcomm MSM8916 platforms. This adds new clocks/clock-names properties to be used for clock links. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220704172453.838303-3-dmitry.baryshkov@linaro.org	2022-08-29 15:42:53 -05:00
Dmitry Baryshkov	0f71ae9457	dt-bindings: clk: qcom,gcc-*: use qcom,gcc.yaml Use qcom,gcc.yaml which contains a set of properties common to most Qualcomm GCC bindings. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20220704172453.838303-2-dmitry.baryshkov@linaro.org	2022-08-29 15:42:53 -05:00
Sam Protsenko	8f3fc0ed70	dt-bindings: clock: exynos850: Add Exynos850 CMU_MFCMSCL CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL. Add clock indices and binding documentation for CMU_MFCMSCL. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-4-semen.protsenko@linaro.org	2022-08-23 09:12:01 +03:00
Sam Protsenko	f20f35f46f	dt-bindings: clock: exynos850: Add Exynos850 CMU_IS CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add clock indices and bindings documentation for CMU_IS domain. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-3-semen.protsenko@linaro.org	2022-08-23 09:11:50 +03:00
Sam Protsenko	45bbf4d76a	dt-bindings: clock: exynos850: Add Exynos850 CMU_AUD CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for BLK_AUD. Add clock indices and binding documentation for CMU_AUD. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220809113323.29965-2-semen.protsenko@linaro.org	2022-08-23 09:11:36 +03:00
Chanho Park	4b6ec8d886	dt-bindings: clock: exynosautov9: add schema for cmu_fsys0/1 Add "samsung,exynosautov9-cmu-fsys0/1" compatibles to illustrate cmu_fsys0 and fsys1 for Exynos Auto v9 SoC. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/49eaadecfb346982dff46cffb870400b76a4e281.1659054220.git.chanho61.park@samsung.com	2022-08-23 09:07:17 +03:00
Shubhrajyoti Datta	35dbdcac51	dt-bindings: add documentation of xilinx clocking wizard Add the devicetree binding for the xilinx clocking wizard. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Link: https://lore.kernel.org/r/20220411100443.15132-2-shubhrajyoti.datta@xilinx.com Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-08-22 19:07:07 -07:00
Conor Dooley	450c787cec	dt-bindings: clock: gpio-gate-clock: Convert to json-schema Convert the simple GPIO clock gate Device Tree binding to json-schema and fix-up references to this file in other text format bindings. Jyri Sarha is the file's only editor/author so they have been added as maintainer of the new yaml binding. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20220727131015.2073100-1-conor.dooley@microchip.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-08-22 16:14:54 -07:00
Lukas Bulwahn	ba6165bc83	dt-bindings: clock: Move versaclock.h to dt-bindings/clock Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-3-lukas.bulwahn@gmail.com Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-08-22 16:04:01 -07:00
Lukas Bulwahn	0384759b3d	dt-bindings: clock: Move lochnagar.h to dt-bindings/clock Most of the clock-related dt-binding header files are located in include/dt-bindings/clock. It would be good to keep all the similar header files at a single location. This was discovered while investigating the state of ownership of the files in include/dt-bindings/ according to the MAINTAINERS file. This change here is similar to commit 8e28918a85a0 ("dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clock") and commit 35d35aae8177 ("dt-bindings: clock: Move at91.h to dt-bindigs/clock"). Signed-off-by: Lukas Bulwahn <lukas.bulwahn@gmail.com> Link: https://lore.kernel.org/r/20220613081632.2159-2-lukas.bulwahn@gmail.com Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2022-08-22 16:04:00 -07:00
Nick Desaulniers	a0a12c3ed0	asm goto: eradicate CC_HAS_ASM_GOTO GCC has supported asm goto since 4.5, and Clang has since version 9.0.0. The minimum supported versions of these tools for the build according to Documentation/process/changes.rst are 5.1 and 11.0.0 respectively. Remove the feature detection script, Kconfig option, and clean up some fallback code that is no longer supported. The removed script was also testing for a GCC specific bug that was fixed in the 4.7 release. Also remove workarounds for bpftrace using clang older than 9.0.0, since other BPF backend fixes are required at this point. Link: https://lore.kernel.org/lkml/CAK7LNATSr=BXKfkdW8f-H5VT_w=xBpT2ZQcZ7rm6JfkdE+QnmA@mail.gmail.com/ Link: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=48637 Acked-by: Borislav Petkov <bp@suse.de> Suggested-by: Masahiro Yamada <masahiroy@kernel.org> Suggested-by: Alexei Starovoitov <alexei.starovoitov@gmail.com> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com> Reviewed-by: Ingo Molnar <mingo@kernel.org> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>	2022-08-21 10:06:28 -07:00

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