Enable gcc, camcc, dispcc, gpucc and videocc so that clients can
vote on these clocks and also enable debugcc for clk_measure
support.
Change-Id: Ic342757a6276ac11d53439e6635ba5030d8626f6
Signed-off-by: shubham diwane <quic_sanantad@quicinc.com>
Add finer frequencies 51, 102, 112, 117.96Mhz to gcc_qupv3_wrap2_s6 clock's
freq table so client can vote on it as required to be in lowsvs, svs corner
with certain baud rates.
Change-Id: I0f9bd3bae69fae1a7c713533bf78bd534fa8f11d
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Tasks affined to a single cpu will be allowed to run on that
cpu regardless of the halt state of the cpu. This creates
an issue for thermally mitigated cpus that are also halted
by cooling devices.
Limit cpus to fmin that are halted by a thermal client only.
Since tasks can run on a halted cpu under some circumstances,
for example, if they've been affined to only one cpu, the
performance of a task affined to a single cpu should not
be reduced simply because the cpu is currently halted.
Therefore, only thermally induced halt shall cause the
frequency limit.
When a cpu is halted by a thermal client, changing the cpu's
frequency at the next update is critical to actually mitigate the
cpu's temperature. When the cpu is unhalted for thermal
reasons, the frequency requested by the cpu should be
restored just as quickly.
Thermal cooling devices can mitigate groups of cpus or
individual cpus, per the logic of the thermal drivers.
Since this cpu's frequency is tied to that of the other
cpus in the system, the frequency shall be limited for
every cpu in the cluster.
Change-Id: Idf19c6e41f05dd62f45262989fcf137b756f915a
Signed-off-by: Abhijeet Dharmapurikar <quic_adharmap@quicinc.com>
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Signed-off-by: Sai Harshini Nimmala <quic_snimmala@quicinc.com>
The implementation of cluster_paused_cpus is unoptimal
and dependent upon the fact that cpus_paused_by_us and
cpus_part_paused_by_us will not intersect.
Improve the implementation to simplify the code and eliminate
this assumption.
Change-Id: Id4d1b4274d57f196ca279d3016236f4d64b4ebb6
Signed-off-by: Stephen Dickey <quic_dickey@quicinc.com>
Currently GDSCR registers are not logged on set mode API failure,
hence add log for set mode failure and also consolidate gdsc failure
status logging for common use.
Change-Id: Icc389783d33d0267d6c094dccc1e22cb699528f2
Signed-off-by: Vivek Aknurwar <quic_viveka@quicinc.com>
Move cpu_latency_qos_add_request() and cpu_latency_qos_remove_request()
into msm_dwc3_perf_vote_enable(), it will make qos function clean in
dwc3_otg_start_host() and dwc3_otg_start_peripheral().
Remove msm_dwc3_perf_vote_enable() from dwc3_otg_start_host() and
dwc3_otg_start_peripheral(), add it in dwc3_msm_resume() and
dwc3_msm_suspend(), it will allow same qos setting after resume from
cable connect suspend.
Change-Id: Ic0b999a29f89e7ba513320b13047c5422dc76c55
Signed-off-by: Linyu Yuan <quic_linyyuan@quicinc.com>
Few alpha PLLs would require to be able to slew in the same VCO mode, which
means the PLL would be able to update the new frequency L value without
turning it off. But to be support this feature the PLL needs to calibrated
at the mid of the VCO range and then enabled.
Add support for dynamic update in which the frequency can be changed
without turning off the PLL. and also Update list_register operation
to read the pll offset defined in PLL register map to avoid mismatch
alpha PLL.
Change-Id: Idbb374be8710cdcd80ab3c4ed57f89f00ed15d23
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Add clock IDs for CAMCC, DISPCC and GCC for clients to
be able to request for clocks from these clock controllers.
Change-Id: Idbc1a1b058da6a49ddab9f302e98c012825c747f
Signed-off-by: Veera Vegivada <quic_vvegivad@quicinc.com>
Signed-off-by: Shubham Diwane <quic_sanantad@quicinc.com>
Add clock IDs for CAMCC, DISPCC, GPUCC, VIDEOCC for clients to
be able to request for clocks from these clock controllers.
Change-Id: I57cbb0924dde80d922bf36d8b85a4b78443f3caf
Signed-off-by: Veera Vegivada <quic_vvegivad@quicinc.com>
Signed-off-by: Shubham Diwane <quic_sanantad@quicinc.com>
