arm64: dts: ti: k3-am625: Correct L2 cache size to 512KB
[ Upstream commit 6974371cab1c488a53960945cb139b20ebb5f16b ]
Per AM62x SoC datasheet[0] L2 cache is 512KB.
[0] https://www.ti.com/lit/gpn/am625 Page 1.
Fixes: f1d17330a5
("arm64: dts: ti: Introduce base support for AM62x SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20230320044935.2512288-1-vigneshr@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -96,7 +96,7 @@ cpu3: cpu@3 {
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L2_0: l2-cache0 {
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compatible = "cache";
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cache-level = <2>;
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cache-size = <0x40000>;
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cache-size = <0x80000>;
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cache-line-size = <64>;
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cache-sets = <512>;
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};
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