soc: qcom: edac: Add kryo edac driver and configs for LLCC EDAC driver
Snapshot of kryo edac driver from msm-5.15 branch
commit 7ede5896b69c ("soc: qcom: edac: Add snapshot of kryo edac driver").
Add LLCC EDAC driver related configs.
Change-Id: Ic462be379615d2f65ddde95119ceca4e8d121c45
Signed-off-by: Abdul Salam <quic_asalam@quicinc.com>
Signed-off-by: Raghavendra Prasad N <quic_raghnaga@quicinc.com>
This commit is contained in:
Abdul Salam
Kishor Krishna Bhat
parent
15261b4cd5
commit
fd46cb4b1d
@ -504,6 +504,36 @@ config EDAC_TI
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help
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Support for error detection and correction on the TI SoCs.
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config EDAC_KRYO_ARM64
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depends on ARM64
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tristate "ARM KRYO Gold and Silver L1/L2/L3/SCU Caches"
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help
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Support for error detection and correction on the
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Kryo3xx Gold and Silver CPUs. Reports errors caught by Kryo3xx
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ECC mechanism.
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For debugging issues having to do with stability and overall system
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health, you should probably say 'Y' here.
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config EDAC_KRYO_ARM64_PANIC_ON_CE
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depends on EDAC_KRYO_ARM64
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bool "Panic on correctable errors - Kryo"
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help
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Forcibly cause a kernel panic on kryo if an correctable error (CE) is
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detected, even though the error is (by definition) correctable and
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would otherwise result in no adverse system effects. This can reduce
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debugging times on hardware which may be operating at voltages or
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frequencies outside normal specification.
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For production builds, you should definitely say 'N' here.
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config EDAC_KRYO_ARM64_PANIC_ON_UE
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depends on EDAC_KRYO_ARM64
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bool "Panic on uncorrectable errors - kryo"
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help
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Forcibly cause a kernel panic if an uncorrectable error (UE) is
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detected. This can reduce debugging times on hardware which may be
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operating at voltages or frequencies outside normal specification.
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For production builds, you should probably say 'N' here.
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config EDAC_QCOM
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tristate "QCOM EDAC Controller"
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depends on ARCH_QCOM && QCOM_LLCC
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@ -80,6 +80,7 @@ obj-$(CONFIG_EDAC_ARMADA_XP) += armada_xp_edac.o
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obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
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obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
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obj-$(CONFIG_EDAC_TI) += ti_edac.o
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obj-$(CONFIG_EDAC_KRYO_ARM64) += kryo_arm64_edac.o
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obj-$(CONFIG_EDAC_QCOM) += qcom_edac.o
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obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o
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obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o
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590
drivers/edac/kryo_arm64_edac.c
Normal file
590
drivers/edac/kryo_arm64_edac.c
Normal file
@ -0,0 +1,590 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/edac.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/smp.h>
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#include <linux/cpu.h>
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#include <linux/cpu_pm.h>
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#include <linux/interrupt.h>
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#include <linux/panic_notifier.h>
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#include <linux/of_irq.h>
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#include <asm/cputype.h>
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#include "edac_mc.h"
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#include "edac_device.h"
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#ifdef CONFIG_EDAC_KRYO_ARM64_PANIC_ON_UE
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#define ARM64_ERP_PANIC_ON_UE 1
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#else
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#define ARM64_ERP_PANIC_ON_UE 0
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#endif
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#define L1_SILVER_BIT 0x0
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#define L2_SILVER_BIT 0x1
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#define L3_BIT 0x2
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#define QCOM_CPU_PART_KRYO4XX_GOLD 0x804
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#define QCOM_CPU_PART_KRYO5XX_GOLD 0xD0D
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#define QCOM_CPU_PART_KRYO4XX_SILVER_V1 0x803
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#define QCOM_CPU_PART_KRYO4XX_SILVER_V2 0x805
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#define QCOM_CPU_PART_KRYO6XX_SILVER_V1 0xD05
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#define QCOM_CPU_PART_KRYO6XX_GOLDPLUS 0xD44
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#define L1_GOLD_IC_BIT 0x1
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#define L1_GOLD_DC_BIT 0x4
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#define L2_GOLD_BIT 0x8
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#define L2_GOLD_TLB_BIT 0x2
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#define L1 0x0
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#define L2 0x1
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#define L3 0x2
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#define EDAC_CPU "kryo_edac"
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#define KRYO_ERRXSTATUS_VALID(a) ((a >> 30) & 0x1)
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#define KRYO_ERRXSTATUS_UE(a) ((a >> 29) & 0x1)
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#define KRYO_ERRXSTATUS_SERR(a) (a & 0xFF)
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#define KRYO_ERRXMISC_LVL(a) ((a >> 1) & 0x7)
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#define KRYO_ERRXMISC_LVL_GOLD(a) (a & 0xF)
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#define KRYO_ERRXMISC_WAY(a) ((a >> 28) & 0xF)
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static inline void set_errxctlr_el1(void)
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{
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u64 val = 0x10f;
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asm volatile("msr s3_0_c5_c4_1, %0" : : "r" (val));
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}
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static inline void set_errxmisc_overflow(void)
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{
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u64 val = 0x7F7F00000000ULL;
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asm volatile("msr s3_0_c5_c5_0, %0" : : "r" (val));
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}
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static inline void write_errselr_el1(u64 val)
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{
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asm volatile("msr s3_0_c5_c3_1, %0" : : "r" (val));
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}
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static inline u64 read_errxstatus_el1(void)
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{
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u64 val;
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asm volatile("mrs %0, s3_0_c5_c4_2" : "=r" (val));
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return val;
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}
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static inline u64 read_errxmisc_el1(void)
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{
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u64 val;
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asm volatile("mrs %0, s3_0_c5_c5_0" : "=r" (val));
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return val;
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}
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static inline void clear_errxstatus_valid(u64 val)
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{
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asm volatile("msr s3_0_c5_c4_2, %0" : : "r" (val));
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}
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static void kryo_edac_handle_ce(struct edac_device_ctl_info *edac_dev,
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int inst_nr, int block_nr, const char *msg)
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{
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edac_device_handle_ce(edac_dev, inst_nr, block_nr, msg);
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#ifdef CONFIG_EDAC_KRYO_ARM64_PANIC_ON_CE
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panic("EDAC %s CE: %s\n", edac_dev->ctl_name, msg);
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#endif
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}
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struct errors_edac {
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const char * const msg;
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void (*func)(struct edac_device_ctl_info *edac_dev,
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int inst_nr, int block_nr, const char *msg);
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};
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static const struct errors_edac errors[] = {
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{"Kryo L1 Correctable Error", kryo_edac_handle_ce },
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{"Kryo L1 Uncorrectable Error", edac_device_handle_ue },
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{"Kryo L2 Correctable Error", kryo_edac_handle_ce },
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{"Kryo L2 Uncorrectable Error", edac_device_handle_ue },
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{"L3 Correctable Error", kryo_edac_handle_ce },
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{"L3 Uncorrectable Error", edac_device_handle_ue },
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};
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#define KRYO_L1_CE 0
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#define KRYO_L1_UE 1
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#define KRYO_L2_CE 2
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#define KRYO_L2_UE 3
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#define KRYO_L3_CE 4
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#define KRYO_L3_UE 5
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#define DATA_BUF_ERR 0x2
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#define CACHE_DATA_ERR 0x6
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#define CACHE_TAG_DIRTY_ERR 0x7
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#define TLB_PARITY_ERR_DATA 0x8
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#define TLB_PARITY_ERR_TAG 0x9
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#define BUS_ERROR 0x12
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struct erp_drvdata {
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struct edac_device_ctl_info *edev_ctl;
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struct erp_drvdata __percpu *erp_cpu_drvdata;
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struct notifier_block nb_pm;
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struct notifier_block nb_panic;
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int ppi;
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};
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static struct erp_drvdata *panic_handler_drvdata;
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static DEFINE_SPINLOCK(local_handler_lock);
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static void l1_l2_irq_enable(void *info)
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{
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int irq = *(int *)info;
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enable_percpu_irq(irq, IRQ_TYPE_LEVEL_HIGH);
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}
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static void l1_l2_irq_disable(void *info)
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{
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int irq = *(int *)info;
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disable_percpu_irq(irq);
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}
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static int request_erp_irq(struct platform_device *pdev, const char *propname,
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const char *desc, irq_handler_t handler,
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void *ed, int percpu)
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{
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int rc;
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struct resource *r;
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struct erp_drvdata *drv = ed;
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struct erp_drvdata *temp = NULL;
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r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, propname);
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if (!r) {
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pr_err("ARM64 CPU ERP: Could not find <%s> IRQ property. Proceeding anyway.\n",
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propname);
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goto out;
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}
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if (!percpu) {
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rc = devm_request_threaded_irq(&pdev->dev, r->start, NULL,
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handler,
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IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
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desc,
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ed);
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if (rc) {
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pr_err("ARM64 CPU ERP: Failed to request IRQ %d: %d (%s / %s). Proceeding anyway.\n",
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(int) r->start, rc, propname, desc);
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goto out;
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}
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} else {
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drv->erp_cpu_drvdata = alloc_percpu(struct erp_drvdata);
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if (!drv->erp_cpu_drvdata) {
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pr_err("Failed to allocate percpu erp data\n");
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goto out;
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}
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temp = raw_cpu_ptr(drv->erp_cpu_drvdata);
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temp->erp_cpu_drvdata = drv;
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rc = request_percpu_irq(r->start, handler, desc,
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drv->erp_cpu_drvdata);
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if (rc) {
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pr_err("ARM64 CPU ERP: Failed to request IRQ %d: %d (%s / %s). Proceeding anyway.\n",
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(int) r->start, rc, propname, desc);
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goto out_free;
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}
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drv->ppi = r->start;
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on_each_cpu(l1_l2_irq_enable, &(r->start), 1);
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}
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return 0;
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out_free:
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free_percpu(drv->erp_cpu_drvdata);
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drv->erp_cpu_drvdata = NULL;
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out:
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return -EINVAL;
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}
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static void dump_err_reg(int errorcode, int level, u64 errxstatus, u64 errxmisc,
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struct edac_device_ctl_info *edev_ctl)
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{
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edac_printk(KERN_CRIT, EDAC_CPU, "ERRXSTATUS_EL1: %llx\n", errxstatus);
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edac_printk(KERN_CRIT, EDAC_CPU, "ERRXMISC_EL1: %llx\n", errxmisc);
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edac_printk(KERN_CRIT, EDAC_CPU, "Cache level: L%d\n", level + 1);
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switch (KRYO_ERRXSTATUS_SERR(errxstatus)) {
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case DATA_BUF_ERR:
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edac_printk(KERN_CRIT, EDAC_CPU, "ECC Error from internal data buffer\n");
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break;
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case CACHE_DATA_ERR:
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edac_printk(KERN_CRIT, EDAC_CPU, "ECC Error from cache data RAM\n");
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break;
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case CACHE_TAG_DIRTY_ERR:
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edac_printk(KERN_CRIT, EDAC_CPU, "ECC Error from cache tag or dirty RAM\n");
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break;
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case TLB_PARITY_ERR_DATA:
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edac_printk(KERN_CRIT, EDAC_CPU, "Parity error on TLB DATA RAM\n");
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break;
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case TLB_PARITY_ERR_TAG:
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edac_printk(KERN_CRIT, EDAC_CPU, "Parity error on TLB TAG RAM\n");
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break;
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case BUS_ERROR:
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edac_printk(KERN_CRIT, EDAC_CPU, "Bus Error\n");
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break;
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}
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if (level == L3)
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc));
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else
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Way: %d\n", (int) KRYO_ERRXMISC_WAY(errxmisc) >> 2);
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errors[errorcode].func(edev_ctl, smp_processor_id(),
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level, errors[errorcode].msg);
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}
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static void kryo_parse_l1_l2_cache_error(u64 errxstatus, u64 errxmisc,
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struct edac_device_ctl_info *edev_ctl, int cpu)
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{
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int level = 0;
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u32 part_num;
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part_num = read_cpuid_part_number();
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switch (part_num) {
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case QCOM_CPU_PART_KRYO4XX_SILVER_V1:
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case QCOM_CPU_PART_KRYO4XX_SILVER_V2:
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case QCOM_CPU_PART_KRYO6XX_SILVER_V1:
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switch (KRYO_ERRXMISC_LVL(errxmisc)) {
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case L1_SILVER_BIT:
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level = L1;
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break;
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case L2_SILVER_BIT:
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level = L2;
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"silver cpu:%d unknown error location:%llu\n",
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cpu, KRYO_ERRXMISC_LVL(errxmisc));
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}
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break;
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case QCOM_CPU_PART_KRYO4XX_GOLD:
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case QCOM_CPU_PART_KRYO5XX_GOLD:
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case QCOM_CPU_PART_KRYO6XX_GOLDPLUS:
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switch (KRYO_ERRXMISC_LVL_GOLD(errxmisc)) {
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case L1_GOLD_DC_BIT:
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case L1_GOLD_IC_BIT:
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level = L1;
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break;
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case L2_GOLD_BIT:
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case L2_GOLD_TLB_BIT:
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level = L2;
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"gold cpu:%d unknown error location:%llu\n",
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cpu, KRYO_ERRXMISC_LVL_GOLD(errxmisc));
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}
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Error in matching cpu%d with part num:%u\n",
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cpu, part_num);
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return;
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}
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switch (level) {
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case L1:
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if (KRYO_ERRXSTATUS_UE(errxstatus))
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dump_err_reg(KRYO_L1_UE, level, errxstatus, errxmisc,
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edev_ctl);
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else
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dump_err_reg(KRYO_L1_CE, level, errxstatus, errxmisc,
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edev_ctl);
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break;
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case L2:
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if (KRYO_ERRXSTATUS_UE(errxstatus))
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dump_err_reg(KRYO_L2_UE, level, errxstatus, errxmisc,
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edev_ctl);
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else
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dump_err_reg(KRYO_L2_CE, level, errxstatus, errxmisc,
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edev_ctl);
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break;
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default:
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edac_printk(KERN_CRIT, EDAC_CPU, "Unknown KRYO_ERRXMISC_LVL value\n");
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}
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}
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static void kryo_check_l1_l2_ecc(void *info)
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{
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struct edac_device_ctl_info *edev_ctl = info;
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u64 errxstatus = 0;
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u64 errxmisc = 0;
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int cpu = 0;
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unsigned long flags;
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spin_lock_irqsave(&local_handler_lock, flags);
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write_errselr_el1(0);
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errxstatus = read_errxstatus_el1();
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cpu = smp_processor_id();
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if (KRYO_ERRXSTATUS_VALID(errxstatus)) {
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errxmisc = read_errxmisc_el1();
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edac_printk(KERN_CRIT, EDAC_CPU,
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"Kryo CPU%d detected a L1/L2 cache error, errxstatus = %llx, errxmisc = %llx\n",
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cpu, errxstatus, errxmisc);
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kryo_parse_l1_l2_cache_error(errxstatus, errxmisc, edev_ctl,
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cpu);
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clear_errxstatus_valid(errxstatus);
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}
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spin_unlock_irqrestore(&local_handler_lock, flags);
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}
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static bool l3_is_bus_error(u64 errxstatus)
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{
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if (KRYO_ERRXSTATUS_SERR(errxstatus) == BUS_ERROR) {
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edac_printk(KERN_CRIT, EDAC_CPU, "Bus Error\n");
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return true;
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}
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return false;
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}
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static void kryo_check_l3_scu_error(struct edac_device_ctl_info *edev_ctl)
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{
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u64 errxstatus = 0;
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u64 errxmisc = 0;
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unsigned long flags;
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spin_lock_irqsave(&local_handler_lock, flags);
|
||||
write_errselr_el1(1);
|
||||
errxstatus = read_errxstatus_el1();
|
||||
errxmisc = read_errxmisc_el1();
|
||||
|
||||
if (KRYO_ERRXSTATUS_VALID(errxstatus) &&
|
||||
KRYO_ERRXMISC_LVL(errxmisc) == L3_BIT) {
|
||||
if (l3_is_bus_error(errxstatus)) {
|
||||
if (edev_ctl->panic_on_ue) {
|
||||
spin_unlock_irqrestore(&local_handler_lock, flags);
|
||||
panic("Causing panic due to Bus Error\n");
|
||||
}
|
||||
goto unlock;
|
||||
}
|
||||
if (KRYO_ERRXSTATUS_UE(errxstatus)) {
|
||||
edac_printk(KERN_CRIT, EDAC_CPU, "Detected L3 uncorrectable error\n");
|
||||
dump_err_reg(KRYO_L3_UE, L3, errxstatus, errxmisc,
|
||||
edev_ctl);
|
||||
} else {
|
||||
edac_printk(KERN_CRIT, EDAC_CPU, "Detected L3 correctable error\n");
|
||||
dump_err_reg(KRYO_L3_CE, L3, errxstatus, errxmisc,
|
||||
edev_ctl);
|
||||
}
|
||||
|
||||
clear_errxstatus_valid(errxstatus);
|
||||
}
|
||||
unlock:
|
||||
spin_unlock_irqrestore(&local_handler_lock, flags);
|
||||
}
|
||||
|
||||
static int kryo_cpu_panic_notify(struct notifier_block *this,
|
||||
unsigned long event, void *ptr)
|
||||
{
|
||||
struct edac_device_ctl_info *edev_ctl =
|
||||
panic_handler_drvdata->edev_ctl;
|
||||
|
||||
edev_ctl->panic_on_ue = 0;
|
||||
|
||||
kryo_check_l3_scu_error(edev_ctl);
|
||||
kryo_check_l1_l2_ecc(edev_ctl);
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static irqreturn_t kryo_l1_l2_handler(int irq, void *drvdata)
|
||||
{
|
||||
kryo_check_l1_l2_ecc(panic_handler_drvdata->edev_ctl);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t kryo_l3_scu_handler(int irq, void *drvdata)
|
||||
{
|
||||
struct erp_drvdata *drv = drvdata;
|
||||
struct edac_device_ctl_info *edev_ctl = drv->edev_ctl;
|
||||
|
||||
kryo_check_l3_scu_error(edev_ctl);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static void initialize_registers(void *info)
|
||||
{
|
||||
set_errxctlr_el1();
|
||||
set_errxmisc_overflow();
|
||||
}
|
||||
|
||||
static void init_regs_on_cpu(bool all_cpus)
|
||||
{
|
||||
int cpu;
|
||||
|
||||
write_errselr_el1(0);
|
||||
if (all_cpus) {
|
||||
for_each_possible_cpu(cpu)
|
||||
smp_call_function_single(cpu, initialize_registers,
|
||||
NULL, 1);
|
||||
} else
|
||||
initialize_registers(NULL);
|
||||
|
||||
write_errselr_el1(1);
|
||||
initialize_registers(NULL);
|
||||
}
|
||||
|
||||
static int kryo_pmu_cpu_pm_notify(struct notifier_block *self,
|
||||
unsigned long action, void *v)
|
||||
{
|
||||
switch (action) {
|
||||
case CPU_PM_EXIT:
|
||||
init_regs_on_cpu(false);
|
||||
kryo_check_l3_scu_error(panic_handler_drvdata->edev_ctl);
|
||||
kryo_check_l1_l2_ecc(panic_handler_drvdata->edev_ctl);
|
||||
break;
|
||||
}
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
static int kryo_cpu_erp_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct erp_drvdata *drv;
|
||||
int rc = 0;
|
||||
int fail = 0;
|
||||
int num_irqs = 0;
|
||||
|
||||
init_regs_on_cpu(true);
|
||||
|
||||
drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
|
||||
|
||||
if (!drv)
|
||||
return -ENOMEM;
|
||||
|
||||
drv->edev_ctl = edac_device_alloc_ctl_info(0, "cpu",
|
||||
num_possible_cpus(), "L", 3, 1, NULL, 0,
|
||||
edac_device_alloc_index());
|
||||
|
||||
if (!drv->edev_ctl)
|
||||
return -ENOMEM;
|
||||
|
||||
drv->edev_ctl->dev = dev;
|
||||
drv->edev_ctl->mod_name = dev_name(dev);
|
||||
drv->edev_ctl->dev_name = dev_name(dev);
|
||||
drv->edev_ctl->ctl_name = "cache";
|
||||
drv->edev_ctl->panic_on_ue = ARM64_ERP_PANIC_ON_UE;
|
||||
drv->nb_pm.notifier_call = kryo_pmu_cpu_pm_notify;
|
||||
drv->nb_panic.notifier_call = kryo_cpu_panic_notify;
|
||||
atomic_notifier_chain_register(&panic_notifier_list,
|
||||
&drv->nb_panic);
|
||||
platform_set_drvdata(pdev, drv);
|
||||
|
||||
rc = edac_device_add_device(drv->edev_ctl);
|
||||
if (rc)
|
||||
goto out_mem;
|
||||
|
||||
panic_handler_drvdata = drv;
|
||||
|
||||
if (request_erp_irq(pdev, "l1-l2-faultirq",
|
||||
"KRYO L1-L2 ECC FAULTIRQ",
|
||||
kryo_l1_l2_handler, drv, 1))
|
||||
fail++;
|
||||
|
||||
if (request_erp_irq(pdev, "l3-scu-faultirq",
|
||||
"KRYO L3-SCU ECC FAULTIRQ",
|
||||
kryo_l3_scu_handler, drv, 0))
|
||||
fail++;
|
||||
|
||||
num_irqs = platform_irq_count(pdev);
|
||||
if (num_irqs == 0) {
|
||||
pr_err("KRYO ERP: No irqs found for error reporting\n");
|
||||
rc = -EINVAL;
|
||||
goto out_dev;
|
||||
}
|
||||
|
||||
if (num_irqs < 0) {
|
||||
rc = num_irqs;
|
||||
goto out_dev;
|
||||
}
|
||||
|
||||
if (fail == platform_irq_count(pdev)) {
|
||||
pr_err("KRYO ERP: Could not request any IRQs. Giving up.\n");
|
||||
rc = -ENODEV;
|
||||
goto out_dev;
|
||||
}
|
||||
|
||||
cpu_pm_register_notifier(&(drv->nb_pm));
|
||||
|
||||
return 0;
|
||||
|
||||
out_dev:
|
||||
edac_device_del_device(dev);
|
||||
out_mem:
|
||||
edac_device_free_ctl_info(drv->edev_ctl);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int kryo_cpu_erp_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct erp_drvdata *drv = dev_get_drvdata(&pdev->dev);
|
||||
struct edac_device_ctl_info *edac_ctl = drv->edev_ctl;
|
||||
|
||||
if (drv->erp_cpu_drvdata != NULL) {
|
||||
on_each_cpu(l1_l2_irq_disable, &(drv->ppi), 1);
|
||||
free_percpu_irq(drv->ppi, drv->erp_cpu_drvdata);
|
||||
free_percpu(drv->erp_cpu_drvdata);
|
||||
}
|
||||
|
||||
cpu_pm_unregister_notifier(&(drv->nb_pm));
|
||||
edac_device_del_device(edac_ctl->dev);
|
||||
edac_device_free_ctl_info(edac_ctl);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id kryo_cpu_erp_match_table[] = {
|
||||
{ .compatible = "arm,arm64-kryo-cpu-erp" },
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct platform_driver kryo_cpu_erp_driver = {
|
||||
.probe = kryo_cpu_erp_probe,
|
||||
.remove = kryo_cpu_erp_remove,
|
||||
.driver = {
|
||||
.name = "kryo_cpu_cache_erp",
|
||||
.of_match_table = of_match_ptr(kryo_cpu_erp_match_table),
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(kryo_cpu_erp_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("Kryo EDAC driver");
|
||||
Loading…
Reference in New Issue
Block a user