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Merge ed4643521e ("Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") into android-mainline

Browse Source 
Steps on the way to 5.18-rc1

Signed-off-by: Greg Kroah-Hartman <gregkh@google.com>
Change-Id: I13d27b9fb4b19af2c713623e0bbcfd0b114647cd
This commit is contained in:
Greg Kroah-Hartman 2022-04-04 09:36:26 +02:00
commit faab30bdcc
1217 changed files with 51094 additions and 29463 deletions
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28
Documentation/devicetree/bindings/arm/airoha.yaml Normal file
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@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/airoha.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Airoha SoC based Platforms Device Tree Bindings
maintainers:
- Felix Fietkau <nbd@nbd.name>
- John Crispin <john@phrozen.org>
description:
Boards with an Airoha SoC shall have the following properties.
properties:
$nodename:
const: '/'
compatible:
oneOf:
- items:
- enum:
- airoha,en7523-evb
- const: airoha,en7523
additionalProperties: true
...

46
Documentation/devicetree/bindings/arm/altera.yaml
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@ -13,12 +13,46 @@ properties:
$nodename: $nodename:
const: "/" const: "/"
compatible: compatible:
items: oneOf:
- enum: - description: Arria 5 boards
- altr,socfpga-cyclone5 items:
- altr,socfpga-arria5 - enum:
- altr,socfpga-arria10 - altr,socfpga-arria5-socdk
- const: altr,socfpga - const: altr,socfpga-arria5
- const: altr,socfpga
- description: Arria 10 boards
items:
- enum:
- altr,socfpga-arria10-socdk
- enclustra,mercury-aa1
- const: altr,socfpga-arria10
- const: altr,socfpga
- description: Cyclone 5 boards
items:
- enum:
- altr,socfpga-cyclone5-socdk
- denx,mcvevk
- ebv,socrates
- macnica,sodia
- novtech,chameleon96
- samtec,vining
- terasic,de0-atlas
- terasic,socfpga-cyclone5-sockit
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Stratix 10 boards
items:
- enum:
- altr,socfpga-stratix10-socdk
- const: altr,socfpga-stratix10
- description: SoCFPGA VT
items:
- const: altr,socfpga-vt
- const: altr,socfpga
additionalProperties: true additionalProperties: true

12
Documentation/devicetree/bindings/arm/amlogic.yaml
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@ -108,6 +108,7 @@ properties:
- amlogic,p230 - amlogic,p230
- amlogic,p231 - amlogic,p231
- libretech,aml-s905d-pc - libretech,aml-s905d-pc
- osmc,vero4k-plus
- phicomm,n1 - phicomm,n1
- smartlabs,sml5442tw - smartlabs,sml5442tw
- videostrong,gxl-kii-pro - videostrong,gxl-kii-pro
@ -170,9 +171,14 @@ properties:
- description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC - description: Boards with the Amlogic Meson SM1 S905X3/D3/Y3 SoC
items: items:
- enum: - enum:
- amediatech,x96-air
- amediatech,x96-air-gbit
- bananapi,bpi-m5 - bananapi,bpi-m5
- cyx,a95xf3-air
- cyx,a95xf3-air-gbit
- hardkernel,odroid-c4 - hardkernel,odroid-c4
- hardkernel,odroid-hc4 - hardkernel,odroid-hc4
- haochuangyi,h96-max
- khadas,vim3l - khadas,vim3l
- seirobotics,sei610 - seirobotics,sei610
- const: amlogic,sm1 - const: amlogic,sm1
@ -183,6 +189,12 @@ properties:
- amlogic,ad401 - amlogic,ad401
- const: amlogic,a1 - const: amlogic,a1
- description: Boards with the Amlogic Meson S4 S805X2 SoC
items:
- enum:
- amlogic,aq222
- const: amlogic,s4
additionalProperties: true additionalProperties: true
... ...

9
Documentation/devicetree/bindings/arm/atmel-at91.yaml
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@ -175,6 +175,15 @@ properties:
- const: microchip,lan9668 - const: microchip,lan9668
- const: microchip,lan966 - const: microchip,lan966
- description: Kontron KSwitch D10 MMT series
items:
- enum:
- kontron,kswitch-d10-mmt-8g
- kontron,kswitch-d10-mmt-6g-2gs
- const: kontron,s1921
- const: microchip,lan9668
- const: microchip,lan966
- items: - items:
- enum: - enum:
- atmel,sams70j19 - atmel,sams70j19

1
Documentation/devicetree/bindings/arm/bcm/bcm2835.yaml
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@ -51,6 +51,7 @@ properties:
- raspberrypi,3-model-b-plus - raspberrypi,3-model-b-plus
- raspberrypi,3-compute-module - raspberrypi,3-compute-module
- raspberrypi,3-compute-module-lite - raspberrypi,3-compute-module-lite
- raspberrypi,model-zero-2-w
- const: brcm,bcm2837 - const: brcm,bcm2837
additionalProperties: true additionalProperties: true

1
Documentation/devicetree/bindings/arm/cpus.yaml
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@ -173,6 +173,7 @@ properties:
- nvidia,tegra194-carmel - nvidia,tegra194-carmel
- qcom,krait - qcom,krait
- qcom,kryo - qcom,kryo
- qcom,kryo250
- qcom,kryo260 - qcom,kryo260
- qcom,kryo280 - qcom,kryo280
- qcom,kryo385 - qcom,kryo385

24
Documentation/devicetree/bindings/arm/fsl.yaml
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@ -762,6 +762,7 @@ properties:
- enum: - enum:
- beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit
- boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board
- emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base
- fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board
- fsl,imx8mm-evk # i.MX8MM EVK Board - fsl,imx8mm-evk # i.MX8MM EVK Board
- gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw71xx-0x # i.MX8MM Gateworks Development Kit
@ -769,8 +770,13 @@ properties:
- gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit - gw,imx8mm-gw73xx-0x # i.MX8MM Gateworks Development Kit
- gw,imx8mm-gw7901 # i.MX8MM Gateworks Board - gw,imx8mm-gw7901 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7902 # i.MX8MM Gateworks Board - gw,imx8mm-gw7902 # i.MX8MM Gateworks Board
- gw,imx8mm-gw7903 # i.MX8MM Gateworks Board
- kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-n801x-som # i.MX8MM Kontron SL (N801X) SOM
- toradex,verdin-imx8mm # Verdin iMX8M Mini Modules
- toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT
- toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules
- variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module - variscite,var-som-mx8mm # i.MX8MM Variscite VAR-SOM-MX8MM module
- prt,prt8mm # i.MX8MM Protonic PRT8MM Board
- const: fsl,imx8mm - const: fsl,imx8mm
- description: Engicam i.Core MX8M Mini SoM based boards - description: Engicam i.Core MX8M Mini SoM based boards
@ -787,6 +793,24 @@ properties:
- const: kontron,imx8mm-n801x-som - const: kontron,imx8mm-n801x-som
- const: fsl,imx8mm - const: fsl,imx8mm
- description: Toradex Boards with Verdin iMX8M Mini Modules
items:
- enum:
- toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia
- toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board
- const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
- description: Toradex Boards with Verdin iMX8M Mini Wi-Fi / BT Modules
items:
- enum:
- toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B.
- const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module
- const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module
- const: fsl,imx8mm
- description: Variscite VAR-SOM-MX8MM based boards - description: Variscite VAR-SOM-MX8MM based boards
items: items:
- const: variscite,var-som-mx8mm-symphony - const: variscite,var-som-mx8mm-symphony

26
Documentation/devicetree/bindings/arm/intel,socfpga.yaml Normal file
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@ -0,0 +1,26 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/intel,socfpga.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA platform device tree bindings
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: AgileX boards
items:
- enum:
- intel,n5x-socdk
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
additionalProperties: true
...

4
Documentation/devicetree/bindings/arm/mediatek.yaml
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@ -30,6 +30,10 @@ properties:
- enum: - enum:
- mediatek,mt6580-evbp1 - mediatek,mt6580-evbp1
- const: mediatek,mt6580 - const: mediatek,mt6580
- items:
- enum:
- prestigio,pmt5008-3g
- const: mediatek,mt6582
- items: - items:
- enum: - enum:
- fairphone,fp1 - fairphone,fp1

1
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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@ -29,6 +29,7 @@ properties:
- mediatek,mt8167-mmsys - mediatek,mt8167-mmsys
- mediatek,mt8173-mmsys - mediatek,mt8173-mmsys
- mediatek,mt8183-mmsys - mediatek,mt8183-mmsys
- mediatek,mt8186-mmsys
- mediatek,mt8192-mmsys - mediatek,mt8192-mmsys
- mediatek,mt8365-mmsys - mediatek,mt8365-mmsys
- const: syscon - const: syscon

2
Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
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@ -27,6 +27,8 @@ properties:
- qcom,sm6350-llcc - qcom,sm6350-llcc
- qcom,sm8150-llcc - qcom,sm8150-llcc
- qcom,sm8250-llcc - qcom,sm8250-llcc
- qcom,sm8350-llcc
- qcom,sm8450-llcc
reg: reg:
items: items:

4
Documentation/devicetree/bindings/arm/mstar/mstar.yaml
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@ -23,8 +23,12 @@ properties:
- description: infinity2m boards - description: infinity2m boards
items: items:
- enum: - enum:
- 100ask,dongshanpione # 100ask DongShanPiOne
- honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit - honestar,ssd201htv2 # Honestar SSD201_HT_V2 devkit
- m5stack,unitv2 # M5Stack UnitV2 - m5stack,unitv2 # M5Stack UnitV2
- miyoo,miyoo-mini # Miyoo Mini
- wirelesstag,ido-som2d01 # Wireless Tag IDO-SOM2D01
- wirelesstag,ido-sbc2d06-v1b-22w # Wireless Tag IDO-SBC2D06-1VB-22W
- const: mstar,infinity2m - const: mstar,infinity2m
- description: infinity3 boards - description: infinity3 boards

48
Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml Normal file
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@ -0,0 +1,48 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/npcm/nuvoton,gcr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Global Control Registers block in Nuvoton SoCs
maintainers:
- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
description:
The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
that expose misc functionality such as chip model and version information or
pinmux settings.
properties:
compatible:
items:
- enum:
- nuvoton,wpcm450-gcr
- nuvoton,npcm750-gcr
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties:
type: object
examples:
- |
gcr: syscon@800000 {
compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
reg = <0x800000 0x1000>;
mux-controller {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x38 0x07>;
idle-states = <2>;
};
};

23
Documentation/devicetree/bindings/arm/qcom.yaml
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@ -42,6 +42,7 @@ description: |
sc7180 sc7180
sc7280 sc7280
sdm630 sdm630
sdm632
sdm660 sdm660
sdm845 sdm845
sdx55 sdx55
@ -172,7 +173,21 @@ properties:
- const: qcom,apq8094 - const: qcom,apq8094
- items: - items:
- const: qcom,msm8996-mtp - enum:
- arrow,apq8096-db820c
- inforce,ifc6640
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- enum:
- qcom,msm8996-mtp
- sony,dora-row
- sony,kagura-row
- sony,keyaki-row
- xiaomi,gemini
- xiaomi,scorpio
- const: qcom,msm8996
- items: - items:
- enum: - enum:
@ -210,6 +225,11 @@ properties:
- google,senor - google,senor
- const: qcom,sc7280 - const: qcom,sc7280
- items:
- enum:
- fairphone,fp3
- const: qcom,sdm632
- items: - items:
- enum: - enum:
- xiaomi,lavender - xiaomi,lavender
@ -262,6 +282,7 @@ properties:
- items: - items:
- enum: - enum:
- qcom,sm8450-hdk
- qcom,sm8450-qrd - qcom,sm8450-qrd
- const: qcom,sm8450 - const: qcom,sm8450

9
Documentation/devicetree/bindings/arm/renesas.yaml
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@ -421,6 +421,15 @@ properties:
- renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L
- const: renesas,r9a07g044 - const: renesas,r9a07g044
- description: RZ/V2L (R9A07G054)
items:
- enum:
- renesas,smarc-evk # SMARC EVK
- enum:
- renesas,r9a07g054l1 # Single Cortex-A55 RZ/V2L
- renesas,r9a07g054l2 # Dual Cortex-A55 RZ/V2L
- const: renesas,r9a07g054
additionalProperties: true additionalProperties: true
... ...

13
Documentation/devicetree/bindings/arm/rockchip.yaml
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@ -481,6 +481,14 @@ properties:
- const: pine64,pinebook-pro - const: pine64,pinebook-pro
- const: rockchip,rk3399 - const: rockchip,rk3399
- description: Pine64 PineNote
items:
- enum:
- pine64,pinenote-v1.1
- pine64,pinenote-v1.2
- const: pine64,pinenote
- const: rockchip,rk3566
- description: Pine64 Rock64 - description: Pine64 Rock64
items: items:
- const: pine64,rock64 - const: pine64,rock64
@ -651,6 +659,11 @@ properties:
- const: rockchip,rk3568-evb1-v10 - const: rockchip,rk3568-evb1-v10
- const: rockchip,rk3568 - const: rockchip,rk3568
- description: Rockchip RK3568 Banana Pi R2 Pro
items:
- const: rockchip,rk3568-bpi-r2pro
- const: rockchip,rk3568
additionalProperties: true additionalProperties: true
... ...

2
Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
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@ -140,6 +140,8 @@ properties:
items: items:
- enum: - enum:
- insignal,arndale-octa # Insignal Arndale Octa - insignal,arndale-octa # Insignal Arndale Octa
- samsung,chagall-wifi # Samsung SM-T800
- samsung,klimt-wifi # Samsung SM-T700
- samsung,smdk5420 # Samsung SMDK5420 eval - samsung,smdk5420 # Samsung SMDK5420 eval
- const: samsung,exynos5420 - const: samsung,exynos5420
- const: samsung,exynos5 - const: samsung,exynos5

6
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
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@ -28,6 +28,12 @@ properties:
- enum: - enum:
- st,stm32mp153 - st,stm32mp153
- st,stm32mp157 - st,stm32mp157
- description: emtrion STM32MP1 Argon based Boards
items:
- const: emtrion,stm32mp157c-emsbc-argon
- const: emtrion,stm32mp157c-emstamp-argon
- const: st,stm32mp157
- items: - items:
- enum: - enum:
- st,stm32f429i-disco - st,stm32f429i-disco

5
Documentation/devicetree/bindings/arm/sunxi.yaml
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@ -444,6 +444,11 @@ properties:
- const: haoyu,a10-marsboard - const: haoyu,a10-marsboard
- const: allwinner,sun4i-a10 - const: allwinner,sun4i-a10
- description: HAOYU Electronics Marsboard A20
items:
- const: haoyu,a20-marsboard
- const: allwinner,sun7i-a20
- description: MapleBoard MP130 - description: MapleBoard MP130
items: items:
- const: mapleboard,mp130 - const: mapleboard,mp130

27
Documentation/devicetree/bindings/arm/tesla.yaml Normal file
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@ -0,0 +1,27 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/tesla.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tesla Full Self Driving(FSD) platforms device tree bindings
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
- linux-fsd@tesla.com
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: FSD SoC board
items:
- enum:
- tesla,fsd-evb # Tesla FSD Evaluation
- const: tesla,fsd
additionalProperties: true
...

6
Documentation/devicetree/bindings/arm/ti/k3.yaml
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@ -46,6 +46,12 @@ properties:
- ti,j7200-evm - ti,j7200-evm
- const: ti,j7200 - const: ti,j7200
- description: K3 AM625 SoC
items:
- enum:
- ti,am625-sk
- const: ti,am625
- description: K3 AM642 SoC - description: K3 AM642 SoC
items: items:
- enum: - enum:

20
Documentation/devicetree/bindings/clock/intc_stratix10.txt
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@ -1,20 +0,0 @@
Device Tree Clock bindings for Intel's SoCFPGA Stratix10 platform
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be
"intel,stratix10-clkmgr"
- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
- #clock-cells : from common clock binding, shall be set to 1.
Example:
clkmgr: clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

35
Documentation/devicetree/bindings/clock/intel,stratix10.yaml Normal file
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@ -0,0 +1,35 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel SoCFPGA Stratix10 platform clock controller binding
maintainers:
- Dinh Nguyen <dinguyen@kernel.org>
properties:
compatible:
const: intel,stratix10-clkmgr
'#clock-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@ffd10000 {
compatible = "intel,stratix10-clkmgr";
reg = <0xffd10000 0x1000>;
#clock-cells = <1>;
};

45
Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml Normal file
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@ -0,0 +1,45 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MStar/Sigmastar MSC313 CPU PLL
maintainers:
- Daniel Palmer <daniel@thingy.jp>
description: |
The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
PLL that can be used as the clock source for the CPU(s).
properties:
compatible:
const: mstar,msc313-cpupll
"#clock-cells":
const: 1
clocks:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- "#clock-cells"
- clocks
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mstar-msc313-mpll.h>
cpupll: cpupll@206400 {
compatible = "mstar,msc313-cpupll";
reg = <0x206400 0x200>;
#clock-cells = <1>;
clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
};

198
Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml Normal file
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@ -0,0 +1,198 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/tesla,fsd-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tesla FSD (Full Self-Driving) SoC clock controller
maintainers:
- Alim Akhtar <alim.akhtar@samsung.com>
- linux-fsd@tesla.com
description: |
FSD clock controller consist of several clock management unit
(CMU), which generates clocks for various inteernal SoC blocks.
The root clock comes from external OSC clock (24 MHz).
All available clocks are defined as preprocessor macros in
'dt-bindings/clock/fsd-clk.h' header.
properties:
compatible:
enum:
- tesla,fsd-clock-cmu
- tesla,fsd-clock-imem
- tesla,fsd-clock-peric
- tesla,fsd-clock-fsys0
- tesla,fsd-clock-fsys1
- tesla,fsd-clock-mfc
- tesla,fsd-clock-cam_csi
clocks:
minItems: 1
maxItems: 6
clock-names:
minItems: 1
maxItems: 6
"#clock-cells":
const: 1
reg:
maxItems: 1
allOf:
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-cmu
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
clock-names:
items:
- const: fin_pll
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-imem
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
- description: IMEM TCU clock (from CMU_CMU)
- description: IMEM bus clock (from CMU_CMU)
- description: IMEM DMA clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: dout_cmu_imem_tcuclk
- const: dout_cmu_imem_aclk
- const: dout_cmu_imem_dmaclk
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-peric
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
- description: Shared0 PLL div4 clock (from CMU_CMU)
- description: PERIC shared1 div36 clock (from CMU_CMU)
- description: PERIC shared0 div3 TBU clock (from CMU_CMU)
- description: PERIC shared0 div20 clock (from CMU_CMU)
- description: PERIC shared1 div4 DMAclock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: dout_cmu_pll_shared0_div4
- const: dout_cmu_peric_shared1div36
- const: dout_cmu_peric_shared0div3_tbuclk
- const: dout_cmu_peric_shared0div20
- const: dout_cmu_peric_shared1div4_dmaclk
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-fsys0
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
- description: Shared0 PLL div6 clock (from CMU_CMU)
- description: FSYS0 shared1 div4 clock (from CMU_CMU)
- description: FSYS0 shared0 div4 clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: dout_cmu_pll_shared0_div6
- const: dout_cmu_fsys0_shared1div4
- const: dout_cmu_fsys0_shared0div4
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-fsys1
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
- description: FSYS1 shared0 div8 clock (from CMU_CMU)
- description: FSYS1 shared0 div4 clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: dout_cmu_fsys1_shared0div8
- const: dout_cmu_fsys1_shared0div4
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-mfc
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
clock-names:
items:
- const: fin_pll
- if:
properties:
compatible:
contains:
const: tesla,fsd-clock-cam_csi
then:
properties:
clocks:
items:
- description: External reference clock (24 MHz)
clock-names:
items:
- const: fin_pll
required:
- compatible
- "#clock-cells"
- clocks
- clock-names
- reg
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS1
- |
#include <dt-bindings/clock/fsd-clk.h>
clock_fsys1: clock-controller@16810000 {
compatible = "tesla,fsd-clock-fsys1";
reg = <0x16810000 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
clock-names = "fin_pll",
"dout_cmu_fsys1_shared0div8",
"dout_cmu_fsys1_shared0div4";
};
...

75
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View File

@ -38,6 +38,9 @@ properties:
The virtio transport only supports a single device. The virtio transport only supports a single device.
items: items:
- const: arm,scmi-virtio - const: arm,scmi-virtio
- description: SCMI compliant firmware with OP-TEE transport
items:
- const: linaro,scmi-optee
interrupts: interrupts:
description: description:
@ -78,11 +81,24 @@ properties:
'#size-cells': '#size-cells':
const: 0 const: 0
atomic-threshold-us:
description:
An optional time value, expressed in microseconds, representing, on this
platform, the threshold above which any SCMI command, advertised to have
an higher-than-threshold execution latency, should not be considered for
atomic mode of operation, even if requested.
default: 0
arm,smc-id: arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
description: description:
SMC id required when using smc or hvc transports SMC id required when using smc or hvc transports
linaro,optee-channel-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Channel specifier required when using OP-TEE transport.
protocol@11: protocol@11:
type: object type: object
properties: properties:
@ -195,6 +211,12 @@ patternProperties:
minItems: 1 minItems: 1
maxItems: 2 maxItems: 2
linaro,optee-channel-id:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Channel specifier required when using OP-TEE transport and
protocol has a dedicated communication channel.
required: required:
- reg - reg
@ -226,6 +248,16 @@ else:
- arm,smc-id - arm,smc-id
- shmem - shmem
else:
if:
properties:
compatible:
contains:
const: linaro,scmi-optee
then:
required:
- linaro,optee-channel-id
examples: examples:
- | - |
firmware { firmware {
@ -240,6 +272,8 @@ examples:
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
atomic-threshold-us = <10000>;
scmi_devpd: protocol@11 { scmi_devpd: protocol@11 {
reg = <0x11>; reg = <0x11>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
@ -340,7 +374,48 @@ examples:
reg = <0x11>; reg = <0x11>;
#power-domain-cells = <1>; #power-domain-cells = <1>;
}; };
};
};
- |
firmware {
scmi {
compatible = "linaro,scmi-optee";
linaro,optee-channel-id = <0>;
#address-cells = <1>;
#size-cells = <0>;
scmi_dvfs1: protocol@13 {
reg = <0x13>;
linaro,optee-channel-id = <1>;
shmem = <&cpu_optee_lpri0>;
#clock-cells = <1>;
};
scmi_clk0: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
sram@51000000 {
compatible = "mmio-sram";
reg = <0x0 0x51000000 0x0 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x51000000 0x10000>;
cpu_optee_lpri0: optee-sram-section@0 {
compatible = "arm,scmi-shmem";
reg = <0x0 0x80>;
};
}; };
}; };

19
Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt
View File

@ -1,19 +0,0 @@
* Andestech Internal Vector Interrupt Controller
The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
suitable for a simpler SoC platform not requiring a more sophisticated and
bigger External Vector Interrupt Controller.
Main node required properties:
- compatible : should at least contain "andestech,ativic32".
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells: 1 cells and refer to interrupt-controller/interrupts
Examples:
intc: interrupt-controller {
compatible = "andestech,ativic32";
#interrupt-cells = <1>;
interrupt-controller;
};

135
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2-timings.yaml Normal file
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@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: jedec,lpddr2-timings
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tDQSCK-max:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c in pico seconds.
tDQSCK-max-derated:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tRAS-max-ns:
description: |
Row active time in nano seconds.
tRAS-min:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tZQCL:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Long calibration time in pico seconds.
tZQCS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Short calibration time in pico seconds.
tZQinit:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Initialization calibration time in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
timings {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tRAS-max-ns = <70000>;
tRAS-min = <42000>;
tRPab = <21000>;
tRCD = <18000>;
tRRD = <10000>;
tRTP = <7500>;
tWR = <15000>;
tWTR = <7500>;
tXP = <7500>;
tZQCL = <360000>;
tZQCS = <90000>;
tZQinit = <1000000>;
};

23
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr2.yaml
View File

@ -30,12 +30,26 @@ properties:
maximum: 255 maximum: 255
description: | description: |
Revision 1 value of SDRAM chip. Obtained from device datasheet. Revision 1 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id2: revision-id2:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
maximum: 255 maximum: 255
description: | description: |
Revision 2 value of SDRAM chip. Obtained from device datasheet. Revision 2 value of SDRAM chip. Obtained from device datasheet.
Property is deprecated, use revision-id instead.
deprecated: true
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
minItems: 2
maxItems: 2
items:
minimum: 0
maximum: 255
density: density:
$ref: /schemas/types.yaml#/definitions/uint32 $ref: /schemas/types.yaml#/definitions/uint32
@ -142,14 +156,12 @@ properties:
patternProperties: patternProperties:
"^lpddr2-timings": "^lpddr2-timings":
type: object $ref: jedec,lpddr2-timings.yaml
description: | description: |
The lpddr2 node may have one or more child nodes of type "lpddr2-timings". The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
"lpddr2-timings" provides AC timing parameters of the device for "lpddr2-timings" provides AC timing parameters of the device for
a given speed-bin. The user may provide the timings for as many a given speed-bin. The user may provide the timings for as many
speed-bins as is required. Please see Documentation/devicetree/ speed-bins as is required.
bindings/memory-controllers/ddr/lpddr2-timings.txt for more information
on "lpddr2-timings".
required: required:
- compatible - compatible
@ -164,8 +176,7 @@ examples:
compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4"; compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
density = <2048>; density = <2048>;
io-width = <32>; io-width = <32>;
revision-id1 = <1>; revision-id = <1 0>;
revision-id2 = <0>;
tRPab-min-tck = <3>; tRPab-min-tck = <3>;
tRCD-min-tck = <3>; tRCD-min-tck = <3>;

157
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3-timings.yaml Normal file
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@ -0,0 +1,157 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
const: jedec,lpddr3-timings
reg:
maxItems: 1
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
Property is deprecated, use max-freq.
deprecated: true
max-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum DDR clock frequency for the speed-bin, in Hz.
min-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Minimum DDR clock frequency for the speed-bin, in Hz.
tCKE:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in pico seconds.
tCKESR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in pico seconds.
tFAW:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Four-bank activate window in pico seconds.
tMRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Mode register set command delay in pico seconds.
tR2R-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional READ-to-READ delay in chip-to-chip cases in pico seconds.
tRAS:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row active time in pico seconds.
tRC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
ACTIVATE-to-ACTIVATE command period in pico seconds.
tRCD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
RAS-to-CAS delay in pico seconds.
tRFC:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Refresh Cycle time in pico seconds.
tRPab:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (all banks) in pico seconds.
tRPpb:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Row precharge time (single banks) in pico seconds.
tRRD:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Active bank A to active bank B in pico seconds.
tRTP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal READ to PRECHARGE command delay in pico seconds.
tW2W-C2C:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in pico seconds.
tWR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
WRITE recovery time in pico seconds.
tWTR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Internal WRITE-to-READ command delay in pico seconds.
tXP:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Exit power-down to next valid command delay in pico seconds.
tXSR:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
SELF REFRESH exit to next valid command delay in pico seconds.
required:
- compatible
- min-freq
- max-freq
additionalProperties: false
examples:
- |
lpddr3 {
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};

263
Documentation/devicetree/bindings/memory-controllers/ddr/jedec,lpddr3.yaml Normal file
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@ -0,0 +1,263 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
items:
- enum:
- samsung,K3QF2F20DB
- const: jedec,lpddr3
'#address-cells':
const: 1
deprecated: true
density:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Density in megabits of SDRAM chip.
enum:
- 4096
- 8192
- 16384
- 32768
io-width:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
IO bus width in bits of SDRAM chip.
enum:
- 32
- 16
manufacturer-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Manufacturer ID value read from Mode Register 5. The property is
deprecated, manufacturer should be derived from the compatible.
deprecated: true
revision-id:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
items:
maximum: 255
description: |
Revision value of SDRAM chip read from Mode Registers 6 and 7.
'#size-cells':
const: 0
deprecated: true
tCKE-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
of clock cycles.
tCKESR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
CKE minimum pulse width during SELF REFRESH (low pulse width during
SELF REFRESH) in terms of number of clock cycles.
tDQSCK-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
DQS output data access time from CK_t/CK_c in terms of number of clock
cycles.
tFAW-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Four-bank activate window in terms of number of clock cycles.
tMRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Mode register set command delay in terms of number of clock cycles.
tR2R-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional READ-to-READ delay in chip-to-chip cases in terms of number
of clock cycles.
tRAS-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
Row active time in terms of number of clock cycles.
tRC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 63
description: |
ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
tRCD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
RAS-to-CAS delay in terms of number of clock cycles.
tRFC-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Refresh Cycle time in terms of number of clock cycles.
tRL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
READ data latency in terms of number of clock cycles.
tRPab-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (all banks) in terms of number of clock cycles.
tRPpb-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Row precharge time (single banks) in terms of number of clock cycles.
tRRD-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Active bank A to active bank B in terms of number of clock cycles.
tRTP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal READ to PRECHARGE command delay in terms of number of clock
cycles.
tW2W-C2C-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description: |
Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
of clock cycles.
tWL-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE data latency in terms of number of clock cycles.
tWR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
WRITE recovery time in terms of number of clock cycles.
tWTR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 15
description: |
Internal WRITE-to-READ command delay in terms of number of clock cycles.
tXP-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 255
description: |
Exit power-down to next valid command delay in terms of number of clock
cycles.
tXSR-min-tck:
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1023
description: |
SELF REFRESH exit to next valid command delay in terms of number of clock
cycles.
patternProperties:
"^timings((-[0-9])+|(@[0-9a-f]+))?$":
$ref: jedec,lpddr3-timings.yaml
description: |
The lpddr3 node may have one or more child nodes with timings.
Each timing node provides AC timing parameters of the device for a given
speed-bin. The user may provide the timings for as many speed-bins as is
required.
required:
- compatible
- density
- io-width
additionalProperties: false
examples:
- |
lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tDQSCK-min-tck = <5>;
tFAW-min-tck = <5>;
tMRD-min-tck = <5>;
tR2R-C2C-min-tck = <0>;
tRAS-min-tck = <5>;
tRC-min-tck = <6>;
tRCD-min-tck = <3>;
tRFC-min-tck = <17>;
tRL-min-tck = <14>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRRD-min-tck = <2>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tWR-min-tck = <7>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tXSR-min-tck = <12>;
timings {
compatible = "jedec,lpddr3-timings";
max-freq = <800000000>;
min-freq = <100000000>;
tCKE = <3750>;
tCKESR = <3750>;
tFAW = <25000>;
tMRD = <7000>;
tR2R-C2C = <0>;
tRAS = <23000>;
tRC = <33750>;
tRCD = <10000>;
tRFC = <65000>;
tRPab = <12000>;
tRPpb = <12000>;
tRRD = <6000>;
tRTP = <3750>;
tW2W-C2C = <0>;
tWR = <7500>;
tWTR = <3750>;
tXP = <3750>;
tXSR = <70000>;
};
};

52
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@ -1,52 +0,0 @@
* AC timing parameters of LPDDR2(JESD209-2) memories for a given speed-bin
Required properties:
- compatible : Should be "jedec,lpddr2-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds). Parameters with
a different unit have a suffix indicating the unit such as 'tRAS-max-ns'
- tRCD
- tWR
- tRAS-min
- tRRD
- tWTR
- tXP
- tRTP
- tDQSCK-max
- tFAW
- tZQCS
- tZQinit
- tRPab
- tZQCL
- tCKESR
- tRAS-max-ns
- tDQSCK-max-derated
Example:
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
};

58
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@ -1,58 +0,0 @@
* AC timing parameters of LPDDR3 memories for a given speed-bin.
The structures are based on LPDDR2 and extended where needed.
Required properties:
- compatible : Should be "jedec,lpddr3-timings"
- min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
- reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
Optional properties:
The following properties represent AC timing parameters from the memory
data-sheet of the device for a given speed-bin. All these properties are
of type <u32> and the default unit is ps (pico seconds).
- tRFC
- tRRD
- tRPab
- tRPpb
- tRCD
- tRC
- tRAS
- tWTR
- tWR
- tRTP
- tW2W-C2C
- tR2R-C2C
- tFAW
- tXSR
- tXP
- tCKE
- tCKESR
- tMRD
Example:
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
reg = <800000000>; /* workaround: it shows max-freq */
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};

107
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@ -1,107 +0,0 @@
* LPDDR3 SDRAM memories compliant to JEDEC JESD209-3C
Required properties:
- compatible : Should be "<vendor>,<type>", and generic value "jedec,lpddr3".
Example "<vendor>,<type>" values:
"samsung,K3QF2F20DB"
- density : <u32> representing density in Mb (Mega bits)
- io-width : <u32> representing bus width. Possible values are 8, 16, 32, 64
- #address-cells: Must be set to 1
- #size-cells: Must be set to 0
Optional properties:
- manufacturer-id : <u32> Manufacturer ID value read from Mode Register 5
- revision-id : <u32 u32> Revision IDs read from Mode Registers 6 and 7
The following optional properties represent the minimum value of some AC
timing parameters of the DDR device in terms of number of clock cycles.
These values shall be obtained from the device data-sheet.
- tRFC-min-tck
- tRRD-min-tck
- tRPab-min-tck
- tRPpb-min-tck
- tRCD-min-tck
- tRC-min-tck
- tRAS-min-tck
- tWTR-min-tck
- tWR-min-tck
- tRTP-min-tck
- tW2W-C2C-min-tck
- tR2R-C2C-min-tck
- tWL-min-tck
- tDQSCK-min-tck
- tRL-min-tck
- tFAW-min-tck
- tXSR-min-tck
- tXP-min-tck
- tCKE-min-tck
- tCKESR-min-tck
- tMRD-min-tck
Child nodes:
- The lpddr3 node may have one or more child nodes of type "lpddr3-timings".
"lpddr3-timings" provides AC timing parameters of the device for
a given speed-bin. Please see
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3-timings.txt
for more information on "lpddr3-timings"
Example:
samsung_K3QF2F20DB: lpddr3 {
compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
density = <16384>;
io-width = <32>;
manufacturer-id = <1>;
revision-id = <123 234>;
#address-cells = <1>;
#size-cells = <0>;
tRFC-min-tck = <17>;
tRRD-min-tck = <2>;
tRPab-min-tck = <2>;
tRPpb-min-tck = <2>;
tRCD-min-tck = <3>;
tRC-min-tck = <6>;
tRAS-min-tck = <5>;
tWTR-min-tck = <2>;
tWR-min-tck = <7>;
tRTP-min-tck = <2>;
tW2W-C2C-min-tck = <0>;
tR2R-C2C-min-tck = <0>;
tWL-min-tck = <8>;
tDQSCK-min-tck = <5>;
tRL-min-tck = <14>;
tFAW-min-tck = <5>;
tXSR-min-tck = <12>;
tXP-min-tck = <2>;
tCKE-min-tck = <2>;
tCKESR-min-tck = <2>;
tMRD-min-tck = <5>;
timings_samsung_K3QF2F20DB_800mhz: lpddr3-timings@800000000 {
compatible = "jedec,lpddr3-timings";
/* workaround: 'reg' shows max-freq */
reg = <800000000>;
min-freq = <100000000>;
tRFC = <65000>;
tRRD = <6000>;
tRPab = <12000>;
tRPpb = <12000>;
tRCD = <10000>;
tRC = <33750>;
tRAS = <23000>;
tWTR = <3750>;
tWR = <7500>;
tRTP = <3750>;
tW2W-C2C = <0>;
tR2R-C2C = <0>;
tFAW = <25000>;
tXSR = <70000>;
tXP = <3750>;
tCKE = <3750>;
tCKESR = <3750>;
tMRD = <7000>;
};
}

113
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@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: FSL/NXP Integrated Flash Controller
maintainers:
- Li Yang <leoyang.li@nxp.com>
description: |
NXP's integrated flash controller (IFC) is an advanced version of the
enhanced local bus controller which includes similar programming and signal
interfaces with an extended feature set. The IFC provides access to multiple
external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
SRAM and other memories where address and data are shared on a bus.
properties:
$nodename:
pattern: "^memory-controller@[0-9a-f]+$"
compatible:
const: fsl,ifc
"#address-cells":
enum: [2, 3]
description: |
Should be either two or three. The first cell is the chipselect
number, and the remaining cells are the offset into the chipselect.
"#size-cells":
enum: [1, 2]
description: |
Either one or two, depending on how large each chipselect can be.
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
description: |
IFC may have one or two interrupts. If two interrupt specifiers are
present, the first is the "common" interrupt (CM_EVTER_STAT), and the
second is the NAND interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
little-endian:
type: boolean
description: |
If this property is absent, the big-endian mode will be in use as default
for registers.
ranges:
description: |
Each range corresponds to a single chipselect, and covers the entire
access window as configured.
patternProperties:
"^.*@[a-f0-9]+(,[a-f0-9]+)+$":
type: object
description: |
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
required:
- compatible
- reg
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
memory-controller@ffe1e000 {
compatible = "fsl,ifc";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000>,
<0x1 0x0 0x0 0xffa00000 0x00010000>,
<0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
};
};

82
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@ -1,82 +0,0 @@
Integrated Flash Controller
Properties:
- name : Should be ifc
- compatible : should contain "fsl,ifc". The version of the integrated
flash controller can be found in the IFC_REV register at
offset zero.
- #address-cells : Should be either two or three. The first cell is the
chipselect number, and the remaining cells are the
offset into the chipselect.
- #size-cells : Either one or two, depending on how large each chipselect
can be.
- reg : Offset and length of the register set for the device
- interrupts: IFC may have one or two interrupts. If two interrupt
specifiers are present, the first is the "common"
interrupt (CM_EVTER_STAT), and the second is the NAND
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
- little-endian : If this property is absent, the big-endian mode will
be in use as default for registers.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
Child device nodes describe the devices connected to IFC such as NOR (e.g.
cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
like FPGAs, CPLDs, etc.
Example:
ifc@ffe1e000 {
compatible = "fsl,ifc", "simple-bus";
#address-cells = <2>;
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
0x1 0x0 0x0 0xffa00000 0x00010000
0x3 0x0 0x0 0xffb00000 0x00020000>;
flash@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x2000000>;
bank-width = <2>;
device-width = <1>;
partition@0 {
/* 32MB for user data */
reg = <0x0 0x02000000>;
label = "NOR Data";
};
};
flash@1,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ifc-nand";
reg = <0x1 0x0 0x10000>;
partition@0 {
/* This location must not be altered */
/* 1MB for u-boot Bootloader Image */
reg = <0x0 0x00100000>;
label = "NAND U-Boot Image";
read-only;
};
};
cpld@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p1010rdb-cpld";
reg = <0x3 0x0 0x000001f>;
};
};

32
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
View File

@ -16,7 +16,7 @@ description: |
MediaTek SMI have two generations of HW architecture, here is the list MediaTek SMI have two generations of HW architecture, here is the list
which generation the SoCs use: which generation the SoCs use:
generation 1: mt2701 and mt7623. generation 1: mt2701 and mt7623.
generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8192 and mt8195. generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8192 and mt8195.
There's slight differences between the two SMI, for generation 2, the There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But register which control the iommu port is at each larb's register base. But
@ -35,6 +35,7 @@ properties:
- mediatek,mt8167-smi-common - mediatek,mt8167-smi-common
- mediatek,mt8173-smi-common - mediatek,mt8173-smi-common
- mediatek,mt8183-smi-common - mediatek,mt8183-smi-common
- mediatek,mt8186-smi-common
- mediatek,mt8192-smi-common - mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp - mediatek,mt8195-smi-common-vpp
@ -88,10 +89,9 @@ allOf:
- mediatek,mt2701-smi-common - mediatek,mt2701-smi-common
then: then:
properties: properties:
clock: clocks:
items: minItems: 3
minItems: 3 maxItems: 3
maxItems: 3
clock-names: clock-names:
items: items:
- const: apb - const: apb
@ -108,10 +108,9 @@ allOf:
required: required:
- mediatek,smi - mediatek,smi
properties: properties:
clock: clocks:
items: minItems: 3
minItems: 3 maxItems: 3
maxItems: 3
clock-names: clock-names:
items: items:
- const: apb - const: apb
@ -127,16 +126,16 @@ allOf:
enum: enum:
- mediatek,mt6779-smi-common - mediatek,mt6779-smi-common
- mediatek,mt8183-smi-common - mediatek,mt8183-smi-common
- mediatek,mt8186-smi-common
- mediatek,mt8192-smi-common - mediatek,mt8192-smi-common
- mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vdo
- mediatek,mt8195-smi-common-vpp - mediatek,mt8195-smi-common-vpp
then: then:
properties: properties:
clock: clocks:
items: minItems: 4
minItems: 4 maxItems: 4
maxItems: 4
clock-names: clock-names:
items: items:
- const: apb - const: apb
@ -146,10 +145,9 @@ allOf:
else: # for gen2 HW that don't have gals else: # for gen2 HW that don't have gals
properties: properties:
clock: clocks:
items: minItems: 2
minItems: 2 maxItems: 2
maxItems: 2
clock-names: clock-names:
items: items:
- const: apb - const: apb

19
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
View File

@ -23,6 +23,7 @@ properties:
- mediatek,mt8167-smi-larb - mediatek,mt8167-smi-larb
- mediatek,mt8173-smi-larb - mediatek,mt8173-smi-larb
- mediatek,mt8183-smi-larb - mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8192-smi-larb - mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb - mediatek,mt8195-smi-larb
@ -75,15 +76,16 @@ allOf:
compatible: compatible:
enum: enum:
- mediatek,mt8183-smi-larb - mediatek,mt8183-smi-larb
- mediatek,mt8186-smi-larb
- mediatek,mt8195-smi-larb - mediatek,mt8195-smi-larb
then: then:
properties: properties:
clock: clocks:
items: minItems: 2
minItems: 3 maxItems: 3
maxItems: 3
clock-names: clock-names:
minItems: 2
items: items:
- const: apb - const: apb
- const: smi - const: smi
@ -91,10 +93,9 @@ allOf:
else: else:
properties: properties:
clock: clocks:
items: minItems: 2
minItems: 2 maxItems: 2
maxItems: 2
clock-names: clock-names:
items: items:
- const: apb - const: apb
@ -108,7 +109,7 @@ allOf:
- mediatek,mt2701-smi-larb - mediatek,mt2701-smi-larb
- mediatek,mt2712-smi-larb - mediatek,mt2712-smi-larb
- mediatek,mt6779-smi-larb - mediatek,mt6779-smi-larb
- mediatek,mt8167-smi-larb - mediatek,mt8186-smi-larb
- mediatek,mt8192-smi-larb - mediatek,mt8192-smi-larb
- mediatek,mt8195-smi-larb - mediatek,mt8195-smi-larb

3
Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml
View File

@ -40,7 +40,8 @@ properties:
- items: - items:
- enum: - enum:
- renesas,r9a07g044-rpc-if # RZ/G2{L,LC} - renesas,r9a07g044-rpc-if # RZ/G2{L,LC}
- const: renesas,rzg2l-rpc-if # RZ/G2L family - renesas,r9a07g054-rpc-if # RZ/V2L
- const: renesas,rzg2l-rpc-if
reg: reg:
items: items:

3
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
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@ -51,8 +51,7 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle' $ref: '/schemas/types.yaml#/definitions/phandle'
description: | description: |
phandle of the connected DRAM memory device. For more information please phandle of the connected DRAM memory device. For more information please
refer to documentation file: refer to jedec,lpddr3.yaml.
Documentation/devicetree/bindings/memory-controllers/ddr/lpddr3.txt
operating-points-v2: true operating-points-v2: true

40
Documentation/devicetree/bindings/nds32/andestech-boards
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@ -1,40 +0,0 @@
Andestech(nds32) AE3XX Platform
-----------------------------------------------------------------------------
The AE3XX prototype demonstrates the AE3XX example platform on the FPGA. It
is composed of one Andestech(nds32) processor and AE3XX.
Required properties (in root node):
- compatible = "andestech,ae3xx";
Example:
/dts-v1/;
/ {
compatible = "andestech,ae3xx";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
};
Andestech(nds32) AG101P Platform
-----------------------------------------------------------------------------
AG101P is a generic SoC Platform IP that works with any of Andestech(nds32)
processors to provide a cost-effective and high performance solution for
majority of embedded systems in variety of application domains. Users may
simply attach their IP on one of the system buses together with certain glue
logics to complete a SoC solution for a specific application. With
comprehensive simulation and design environments, users may evaluate the
system performance of their applications and track bugs of their designs
efficiently. The optional hardware development platform further provides real
system environment for early prototyping and software/hardware co-development.
Required properties (in root node):
compatible = "andestech,ag101p";
Example:
/dts-v1/;
/ {
compatible = "andestech,ag101p";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
};

28
Documentation/devicetree/bindings/nds32/atl2c.txt
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@ -1,28 +0,0 @@
* Andestech L2 cache Controller
The level-2 cache controller plays an important role in reducing memory latency
for high performance systems, such as thoese designs with AndesCore processors.
Level-2 cache controller in general enhances overall system performance
signigicantly and the system power consumption might be reduced as well by
reducing DRAM accesses.
This binding specifies what properties must be available in the device tree
representation of an Andestech L2 cache controller.
Required properties:
- compatible:
Usage: required
Value type: <string>
Definition: "andestech,atl2c"
- reg : Physical base address and size of cache controller's memory mapped
- cache-unified : Specifies the cache is a unified cache.
- cache-level : Should be set to 2 for a level 2 cache.
* Example
cache-controller@e0500000 {
compatible = "andestech,atl2c";
reg = <0xe0500000 0x1000>;
cache-unified;
cache-level = <2>;
};

38
Documentation/devicetree/bindings/nds32/cpus.txt
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@ -1,38 +0,0 @@
* Andestech Processor Binding
This binding specifies what properties must be available in the device tree
representation of a Andestech Processor Core, which is the root node in the
tree.
Required properties:
- compatible:
Usage: required
Value type: <string>
Definition: Should be "andestech,<core_name>", "andestech,nds32v3" as fallback.
Must contain "andestech,nds32v3" as the most generic value, in addition to
one of the following identifiers for a particular CPU core:
"andestech,n13"
"andestech,n15"
"andestech,d15"
"andestech,n10"
"andestech,d10"
- device_type
Usage: required
Value type: <string>
Definition: must be "cpu"
- reg: Contains CPU index.
- clock-frequency: Contains the clock frequency for CPU, in Hz.
* Examples
/ {
cpus {
cpu@0 {
device_type = "cpu";
compatible = "andestech,n13", "andestech,nds32v3";
reg = <0x0>;
clock-frequency = <60000000>
};
};
};

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* NDS32 Performance Monitor Units
NDS32 core have a PMU for counting cpu and cache events like cache misses.
The NDS32 PMU representation in the device tree should be done as under:
Required properties:
- compatible :
"andestech,nds32v3-pmu"
- interrupts : The interrupt number for NDS32 PMU is 13.
Example:
pmu{
compatible = "andestech,nds32v3-pmu";
interrupts = <13>;
}

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@ -9,6 +9,7 @@ PROPERTIES
following: following:
"qcom,usb-hs-phy-apq8064" "qcom,usb-hs-phy-apq8064"
"qcom,usb-hs-phy-msm8226"
"qcom,usb-hs-phy-msm8916" "qcom,usb-hs-phy-msm8916"
"qcom,usb-hs-phy-msm8974" "qcom,usb-hs-phy-msm8974"

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
additional information and example.
properties:
'#gpio-cells':
const: 2
gpio-controller: true
'#interrupt-cells':
description:
For GPIO banks supporting external GPIO interrupts or external wake-up
interrupts.
const: 2
interrupt-controller:
description:
For GPIO banks supporting external GPIO interrupts or external wake-up
interrupts.
interrupts:
description:
For GPIO banks supporting direct external wake-up interrupts (without
multiplexing). Number of interrupts must match number of wake-up capable
pins of this bank.
minItems: 1
maxItems: 8
required:
- '#gpio-cells'
- gpio-controller
additionalProperties: false

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-pins-cfg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC pin controller - pins configuration
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
Pins configuration for Samsung S3C/S5P/Exynos SoC pin controller.
The values used for config properties should be derived from the hardware
manual and these values are programmed as-is into the pin pull up/down and
driver strength register of the pin-controller.
See also include/dt-bindings/pinctrl/samsung.h with useful constants.
See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
additional information and example.
properties:
samsung,pins:
description: |
List of pins to configure. For initial and sleep states, the maximum
number is one pin. In other cases there is no upper limit.
The pins should use lowercase names matching hardware manual, e.g. for
GPA0 bank: gpa0-0, gpa0-1, gpa0-2.
$ref: /schemas/types.yaml#/definitions/string-array
samsung,pin-function:
description: |
The pin function selection that should be applied on the pins listed in the
child node is specified using the "samsung,pin-function" property. The value
of this property that should be applied to each of the pins listed in the
"samsung,pins" property should be picked from the hardware manual of the SoC
for the specified pin group. This property is optional in the child node if
no specific function selection is desired for the pins listed in the child
node. The value of this property is used as-is to program the pin-controller
function selector register of the pin-bank.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
samsung,pin-drv:
description: Drive strength configuration.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 15
samsung,pin-pud:
description: Pull up/down configuration.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
samsung,pin-val:
description: Initial value of pin output buffer.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
samsung,pin-con-pdn:
description: Function in power down mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
samsung,pin-pud-pdn:
description: Pull up/down configuration in power down mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
required:
- samsung,pins
additionalProperties: false

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC pin controller - wake-up interrupt controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
External wake-up interrupts for Samsung S3C/S5P/Exynos SoC pin controller.
For S3C24xx, S3C64xx, S5PV210 and Exynos4210 compatible wake-up interrupt
controllers, only one pin-controller device node can include external wake-up
interrupts child node (in other words, only one External wake-up interrupts
pin-controller is supported).
For newer controllers, multiple pin-controller device node can include
external wake-up interrupts child node.
See also Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml for
additional information and example.
properties:
compatible:
enum:
- samsung,s3c2410-wakeup-eint
- samsung,s3c2412-wakeup-eint
- samsung,s3c64xx-wakeup-eint
- samsung,s5pv210-wakeup-eint
- samsung,exynos4210-wakeup-eint
- samsung,exynos7-wakeup-eint
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
interrupts:
description:
Interrupt used by multiplexed external wake-up interrupts.
minItems: 1
maxItems: 6
required:
- compatible
allOf:
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2410-wakeup-eint
- samsung,s3c2412-wakeup-eint
then:
properties:
interrupts:
minItems: 6
maxItems: 6
required:
- interrupts
- if:
properties:
compatible:
contains:
const: samsung,s3c64xx-wakeup-eint
then:
properties:
interrupts:
minItems: 4
maxItems: 4
required:
- interrupts
- if:
properties:
compatible:
contains:
enum:
- samsung,s5pv210-wakeup-eint
- samsung,exynos4210-wakeup-eint
- samsung,exynos7-wakeup-eint
then:
properties:
interrupts:
minItems: 1
maxItems: 1
required:
- interrupts
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos850-wakeup-eint
- samsung,exynosautov9-wakeup-eint
then:
properties:
interrupts: false
additionalProperties: false

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# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC pin controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
- Sylwester Nawrocki <s.nawrocki@samsung.com>
- Tomasz Figa <tomasz.figa@gmail.com>
description: |
This is a part of device tree bindings for Samsung S3C/S5P/Exynos SoC pin
controller.
Pin group settings (like drive strength, pull up/down) are available as
macros in include/dt-bindings/pinctrl/samsung.h.
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
The controller supports three types of interrupts::
- External GPIO interrupts (see interrupts property in pin controller node);
- External wake-up interrupts - multiplexed (capable of waking up the system
see interrupts property in external wake-up interrupt controller node -
samsung,pinctrl-wakeup-interrupt.yaml);
- External wake-up interrupts - direct (capable of waking up the system, see
interrupts property in every bank of pin controller with external wake-up
interrupt controller - samsung,pinctrl-gpio-bank.yaml).
properties:
$nodename:
pattern: "^pinctrl(@.*)?"
compatible:
enum:
- samsung,s3c2412-pinctrl
- samsung,s3c2416-pinctrl
- samsung,s3c2440-pinctrl
- samsung,s3c2450-pinctrl
- samsung,s3c64xx-pinctrl
- samsung,s5pv210-pinctrl
- samsung,exynos3250-pinctrl
- samsung,exynos4210-pinctrl
- samsung,exynos4x12-pinctrl
- samsung,exynos5250-pinctrl
- samsung,exynos5260-pinctrl
- samsung,exynos5410-pinctrl
- samsung,exynos5420-pinctrl
- samsung,exynos5433-pinctrl
- samsung,exynos7-pinctrl
- samsung,exynos7885-pinctrl
- samsung,exynos850-pinctrl
- samsung,exynosautov9-pinctrl
interrupts:
description:
Required for GPIO banks supporting external GPIO interrupts.
maxItems: 1
power-domains:
maxItems: 1
reg:
description:
Second base address of the pin controller if the specific registers of
the pin controller are separated into the different base address.
Only certain banks of certain pin controller might need it.
minItems: 1
maxItems: 2
wakeup-interrupt-controller:
$ref: samsung,pinctrl-wakeup-interrupt.yaml
patternProperties:
"^[a-z]+[0-9]*-gpio-bank$":
description:
Pin banks of the controller are represented by child nodes of the
controller node. Bank name is taken from name of the node.
$ref: samsung,pinctrl-gpio-bank.yaml
"^[a-z0-9-]+-pins$":
oneOf:
- $ref: samsung,pinctrl-pins-cfg.yaml
required:
- samsung,pins
- type: object
patternProperties:
"^[a-z0-9-]+-pins$":
$ref: samsung,pinctrl-pins-cfg.yaml
additionalProperties: false
"^(initial|sleep)-state$":
patternProperties:
"^(pin-[a-z0-9-]+|[a-z0-9-]+-pin)$":
$ref: samsung,pinctrl-pins-cfg.yaml
properties:
samsung,pins:
description: See samsung,pinctrl-pins-cfg.yaml
$ref: /schemas/types.yaml#/definitions/string-array
maxItems: 1
required:
- samsung,pins
unevaluatedProperties: false
required:
- compatible
- reg
allOf:
- $ref: "pinctrl.yaml#"
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-pinctrl
then:
properties:
reg:
minItems: 1
maxItems: 2
else:
properties:
reg:
minItems: 1
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@7f008000 {
compatible = "samsung,s3c64xx-pinctrl";
reg = <0x7f008000 0x1000>;
interrupt-parent = <&vic1>;
interrupts = <21>;
wakeup-interrupt-controller {
compatible = "samsung,s3c64xx-wakeup-eint";
interrupts-extended = <&vic0 0>,
<&vic0 1>,
<&vic1 0>,
<&vic1 1>;
};
/* Pin bank with external GPIO or muxed external wake-up interrupts */
gpa-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
// ...
uart0-data-pins {
samsung,pins = "gpa-0", "gpa-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <S3C64XX_PIN_PULL_NONE>;
};
// ...
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sleep0>;
/* Pin bank with external GPIO or muxed external wake-up interrupts */
gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
// ...
uart0-data-pins {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
// ...
sleep0: sleep-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_INPUT>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
};
gpa0-1-pin {
samsung,pins = "gpa0-1";
samsung,pin-con-pdn = <EXYNOS_PIN_PDN_OUT0>;
samsung,pin-pud-pdn = <EXYNOS_PIN_PULL_NONE>;
};
// ...
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
};
/* Pin bank with external GPIO or muxed external wake-up interrupts */
gpj0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* Pin bank without external interrupts */
gpy0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
};
/* Pin bank with external direct wake-up interrupts */
gpx0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
// ...
sd0-clk-pins {
samsung,pins = "gpk0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
sd4-bus-width8-pins {
part-1-pins {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
part-2-pins {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
};
// ...
otg-gp-pins {
samsung,pins = "gpx3-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_OUTPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
samsung,pin-val = <0>;
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
pinctrl-names = "default";
pinctrl-0 = <&initial_alive>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
};
/* Pin bank with external direct wake-up interrupts */
gpa0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
};
// ...
te-irq-pins {
samsung,pins = "gpf1-3";
samsung,pin-function = <0xf>;
};
// ..
initial_alive: initial-state {
gpa0-0-pin {
samsung,pins = "gpa0-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
// ...
};
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/samsung.h>
pinctrl@114b0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x114b0000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_aud>;
/* Pin bank with external GPIO or muxed external wake-up interrupts */
gpz0-gpio-bank {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
// ...
i2s0-bus-pins {
samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
"gpz0-4", "gpz0-5", "gpz0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR1>;
};
// ...
};

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Samsung GPIO and Pin Mux/Config controller
Samsung's ARM based SoC's integrates a GPIO and Pin mux/config hardware
controller. It controls the input/output settings on the available pads/pins
and also provides ability to multiplex and configure the output of various
on-chip controllers onto these pads.
Required Properties:
- compatible: should be one of the following.
- "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
- "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
- "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
- "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
- "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
- "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
- "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
- "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
- "samsung,exynos4x12-pinctrl": for Exynos4x12 compatible pin-controller.
- "samsung,exynos5250-pinctrl": for Exynos5250 compatible pin-controller.
- "samsung,exynos5260-pinctrl": for Exynos5260 compatible pin-controller.
- "samsung,exynos5410-pinctrl": for Exynos5410 compatible pin-controller.
- "samsung,exynos5420-pinctrl": for Exynos5420 compatible pin-controller.
- "samsung,exynos5433-pinctrl": for Exynos5433 compatible pin-controller.
- "samsung,exynos7-pinctrl": for Exynos7 compatible pin-controller.
- "samsung,exynos7885-pinctrl": for Exynos7885 compatible pin-controller.
- "samsung,exynos850-pinctrl": for Exynos850 compatible pin-controller.
- "samsung,exynosautov9-pinctrl": for ExynosAutov9 compatible pin-controller.
- reg: Base address of the pin controller hardware module and length of
the address space it occupies.
- reg: Second base address of the pin controller if the specific registers
of the pin controller are separated into the different base address.
Eg: GPF[1-5] of Exynos5433 are separated into the two base address.
- First base address is for GPAx and GPF[1-5] external interrupt
registers.
- Second base address is for GPF[1-5] pinctrl registers.
pinctrl_0: pinctrl@10580000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
wakeup-interrupt-controller {
compatible = "samsung,exynos7-wakeup-eint";
interrupts = <0 16 0>;
};
};
- Pin banks as child nodes: Pin banks of the controller are represented by child
nodes of the controller node. Bank name is taken from name of the node. Each
bank node must contain following properties:
- gpio-controller: identifies the node as a gpio controller and pin bank.
- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
Eg: <&gpx2 6 0>
<[phandle of the gpio controller node]
[pin number within the gpio controller]
[flags]>
Values for gpio specifier:
- Pin number: is a value between 0 to 7.
- Flags: 0 - Active High
1 - Active Low
- Pin mux/config groups as child nodes: The pin mux (selecting pin function
mode) and pin config (pull up/down, driver strength) settings are represented
as child nodes of the pin-controller node. There should be at least one
child node and there is no limit on the count of these child nodes. It is
also possible for a child node to consist of several further child nodes
to allow grouping multiple pinctrl groups into one. The format of second
level child nodes is exactly the same as for first level ones and is
described below.
The child node should contain a list of pin(s) on which a particular pin
function selection or pin configuration (or both) have to applied. This
list of pins is specified using the property name "samsung,pins". There
should be at least one pin specified for this property and there is no upper
limit on the count of pins that can be specified. The pins are specified
using pin names which are derived from the hardware manual of the SoC. As
an example, the pins in GPA0 bank of the pin controller can be represented
as "gpa0-0", "gpa0-1", "gpa0-2" and so on. The names should be in lower case.
The format of the pin names should be (as per the hardware manual)
"[pin bank name]-[pin number within the bank]".
The pin function selection that should be applied on the pins listed in the
child node is specified using the "samsung,pin-function" property. The value
of this property that should be applied to each of the pins listed in the
"samsung,pins" property should be picked from the hardware manual of the SoC
for the specified pin group. This property is optional in the child node if
no specific function selection is desired for the pins listed in the child
node. The value of this property is used as-is to program the pin-controller
function selector register of the pin-bank.
The child node can also optionally specify one or more of the pin
configuration that should be applied on all the pins listed in the
"samsung,pins" property of the child node. The following pin configuration
properties are supported.
- samsung,pin-val: Initial value of pin output buffer.
- samsung,pin-pud: Pull up/down configuration.
- samsung,pin-drv: Drive strength configuration.
- samsung,pin-pud-pdn: Pull up/down configuration in power down mode.
- samsung,pin-drv-pdn: Drive strength configuration in power down mode.
The values specified by these config properties should be derived from the
hardware manual and these values are programmed as-is into the pin
pull up/down and driver strength register of the pin-controller.
Note: A child should include at least a pin function selection property or
pin configuration property (one or more) or both.
The client nodes that require a particular pin function selection and/or
pin configuration should use the bindings listed in the "pinctrl-bindings.txt"
file.
External GPIO and Wakeup Interrupts:
The controller supports two types of external interrupts over gpio. The first
is the external gpio interrupt and second is the external wakeup interrupts.
The difference between the two is that the external wakeup interrupts can be
used as system wakeup events.
A. External GPIO Interrupts: For supporting external gpio interrupts, the
following properties should be specified in the pin-controller device node.
- interrupts: interrupt specifier for the controller. The format and value of
the interrupt specifier depends on the interrupt parent for the controller.
In addition, following properties must be present in node of every bank
of pins supporting GPIO interrupts:
- interrupt-controller: identifies the controller node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2.
- First Cell: represents the external gpio interrupt number local to the
external gpio interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
child node representing the external wakeup interrupt controller should be
included in the pin-controller device node.
Only one pin-controller device node can include external wakeup interrupts
child node (in other words, only one External Wakeup Interrupts
pin-controller is supported).
This child node should include following properties:
- compatible: identifies the type of the external wakeup interrupt controller
The possible values are:
- samsung,s3c2410-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C24xx SoCs except S3C2412 and S3C2413,
- samsung,s3c2412-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C2412 and S3C2413 SoCs,
- samsung,s3c64xx-wakeup-eint: represents wakeup interrupt controller
found on Samsung S3C64xx SoCs,
- samsung,s5pv210-wakeup-eint: represents wakeup interrupt controller
found on Samsung S5Pv210 SoCs,
- samsung,exynos4210-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos4210 and S5PC110/S5PV210 SoCs.
- samsung,exynos7-wakeup-eint: represents wakeup interrupt controller
found on Samsung Exynos7 SoC.
- interrupts: interrupt used by multiplexed wakeup interrupts.
In addition, following properties must be present in node of every bank
of pins supporting wake-up interrupts:
- interrupt-controller: identifies the node as interrupt-parent.
- #interrupt-cells: the value of this property should be 2
- First Cell: represents the external wakeup interrupt number local to
the external wakeup interrupt space of the controller.
- Second Cell: flags to identify the type of the interrupt
- 1 = rising edge triggered
- 2 = falling edge triggered
- 3 = rising and falling edge triggered
- 4 = high level triggered
- 8 = low level triggered
Node of every bank of pins supporting direct wake-up interrupts (without
multiplexing) must contain following properties:
- interrupts: interrupts of the interrupt parent which are used for external
wakeup interrupts from pins of the bank, must contain interrupts for all
pins of the bank.
Aliases:
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
Aliases for controllers compatible with "samsung,exynos7-pinctrl":
- pinctrl0: pin controller of ALIVE block,
- pinctrl1: pin controller of BUS0 block,
- pinctrl2: pin controller of NFC block,
- pinctrl3: pin controller of TOUCH block,
- pinctrl4: pin controller of FF block,
- pinctrl5: pin controller of ESE block,
- pinctrl6: pin controller of FSYS0 block,
- pinctrl7: pin controller of FSYS1 block,
- pinctrl8: pin controller of BUS1 block,
- pinctrl9: pin controller of AUDIO block,
Example: A pin-controller node with pin banks:
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
/* ... */
/* Pin bank without external interrupts */
gpy0: gpy0 {
gpio-controller;
#gpio-cells = <2>;
};
/* ... */
/* Pin bank with external GPIO or muxed wake-up interrupts */
gpj0: gpj0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
/* ... */
/* Pin bank with external direct wake-up interrupts */
gpx0: gpx0 {
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
interrupt-parent = <&gic>;
interrupts = <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>;
#interrupt-cells = <2>;
};
/* ... */
};
Example 1: A pin-controller node with pin groups.
#include <dt-bindings/pinctrl/samsung.h>
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
interrupts = <0 47 0>;
/* ... */
uart0_data: uart0-data {
samsung,pins = "gpa0-0", "gpa0-1";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart0_fctl: uart0-fctl {
samsung,pins = "gpa0-2", "gpa0-3";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart1_data: uart1-data {
samsung,pins = "gpa0-4", "gpa0-5";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
uart1_fctl: uart1-fctl {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
i2c2_bus: i2c2-bus {
samsung,pins = "gpa0-6", "gpa0-7";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
};
sd4_bus8: sd4-bus-width8 {
part-1 {
samsung,pins = "gpk0-3", "gpk0-4",
"gpk0-5", "gpk0-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
part-2 {
samsung,pins = "gpk1-3", "gpk1-4",
"gpk1-5", "gpk1-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_4>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
};
};
Example 2: A pin-controller node with external wakeup interrupt controller node.
pinctrl_1: pinctrl@11000000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11000000 0x1000>;
interrupts = <0 46 0>
/* ... */
wakeup-interrupt-controller {
compatible = "samsung,exynos4210-wakeup-eint";
interrupt-parent = <&gic>;
interrupts = <0 32 0>;
};
};
Example 3: A uart client node that supports 'default' and 'flow-control' states.
uart@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 52 0>;
pinctrl-names = "default", "flow-control;
pinctrl-0 = <&uart0_data>;
pinctrl-1 = <&uart0_data>, <&uart0_fctl>;
};
Example 4: Set up the default pin state for uart controller.
static int s3c24xx_serial_probe(struct platform_device *pdev) {
struct pinctrl *pinctrl;
/* ... */
pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
}
Example 5: A display port client node that supports 'default' pinctrl state
and gpio binding.
display-port-controller {
/* ... */
samsung,hpd-gpio = <&gpx2 6 0>;
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
};
Example 6: Request the gpio for display port controller
static int exynos_dp_probe(struct platform_device *pdev)
{
int hpd_gpio, ret;
struct device *dev = &pdev->dev;
struct device_node *dp_node = dev->of_node;
/* ... */
hpd_gpio = of_get_named_gpio(dp_node, "samsung,hpd-gpio", 0);
/* ... */
ret = devm_gpio_request_one(&pdev->dev, hpd_gpio, GPIOF_IN,
"hpd_gpio");
/* ... */
}

3
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
View File

@ -12,13 +12,14 @@ maintainers:
- Jianxin Pan <jianxin.pan@amlogic.com> - Jianxin Pan <jianxin.pan@amlogic.com>
description: |+ description: |+
Secure Power Domains used in Meson A1/C1 SoCs, and should be the child node Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node
of secure-monitor. of secure-monitor.
properties: properties:
compatible: compatible:
enum: enum:
- amlogic,meson-a1-pwrc - amlogic,meson-a1-pwrc
- amlogic,meson-s4-pwrc
"#power-domain-cells": "#power-domain-cells":
const: 1 const: 1

2
Documentation/devicetree/bindings/power/fsl,imx-gpcv2.yaml
View File

@ -28,6 +28,7 @@ properties:
- fsl,imx8mn-gpc - fsl,imx8mn-gpc
- fsl,imx8mq-gpc - fsl,imx8mq-gpc
- fsl,imx8mm-gpc - fsl,imx8mm-gpc
- fsl,imx8mp-gpc
reg: reg:
maxItems: 1 maxItems: 1
@ -57,6 +58,7 @@ properties:
include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and include/dt-bindings/power/imx7-power.h for fsl,imx7d-gpc and
include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc include/dt-bindings/power/imx8m-power.h for fsl,imx8mq-gpc
include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc include/dt-bindings/power/imx8mm-power.h for fsl,imx8mm-gpc
include/dt-bindings/power/imx8mp-power.h for fsl,imx8mp-gpc
maxItems: 1 maxItems: 1
clocks: clocks:

3
Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
View File

@ -26,7 +26,9 @@ properties:
- mediatek,mt8167-power-controller - mediatek,mt8167-power-controller
- mediatek,mt8173-power-controller - mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller - mediatek,mt8183-power-controller
- mediatek,mt8186-power-controller
- mediatek,mt8192-power-controller - mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
'#power-domain-cells': '#power-domain-cells':
const: 1 const: 1
@ -64,6 +66,7 @@ patternProperties:
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
maxItems: 1 maxItems: 1
clocks: clocks:

1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
View File

@ -17,6 +17,7 @@ properties:
compatible: compatible:
enum: enum:
- qcom,mdm9607-rpmpd - qcom,mdm9607-rpmpd
- qcom,msm8226-rpmpd
- qcom,msm8916-rpmpd - qcom,msm8916-rpmpd
- qcom,msm8939-rpmpd - qcom,msm8939-rpmpd
- qcom,msm8953-rpmpd - qcom,msm8953-rpmpd

7
Documentation/devicetree/bindings/power/renesas,rzg2l-sysc.yaml
View File

@ -4,14 +4,14 @@
$id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#" $id: "http://devicetree.org/schemas/power/renesas,rzg2l-sysc.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Renesas RZ/G2L System Controller (SYSC) title: Renesas RZ/{G2L,V2L} System Controller (SYSC)
maintainers: maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be> - Geert Uytterhoeven <geert+renesas@glider.be>
description: description:
The RZ/G2L System Controller (SYSC) performs system control of the LSI and The RZ/{G2L,V2L} System Controller (SYSC) performs system control of the LSI
supports following functions, and supports following functions,
- External terminal state capture function - External terminal state capture function
- 34-bit address space access function - 34-bit address space access function
- Low power consumption control - Low power consumption control
@ -21,6 +21,7 @@ properties:
compatible: compatible:
enum: enum:
- renesas,r9a07g044-sysc # RZ/G2{L,LC} - renesas,r9a07g044-sysc # RZ/G2{L,LC}
- renesas,r9a07g054-sysc # RZ/V2L
reg: reg:
maxItems: 1 maxItems: 1

16
Documentation/devicetree/bindings/remoteproc/qcom,adsp.yaml
View File

@ -47,6 +47,10 @@ properties:
- qcom,sm8350-cdsp-pas - qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas - qcom,sm8350-slpi-pas
- qcom,sm8350-mpss-pas - qcom,sm8350-mpss-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-cdsp-pas
- qcom,sm8450-mpss-pas
- qcom,sm8450-slpi-pas
reg: reg:
maxItems: 1 maxItems: 1
@ -175,6 +179,10 @@ allOf:
- qcom,sm8350-cdsp-pas - qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas - qcom,sm8350-slpi-pas
- qcom,sm8350-mpss-pas - qcom,sm8350-mpss-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-cdsp-pas
- qcom,sm8450-slpi-pas
- qcom,sm8450-mpss-pas
then: then:
properties: properties:
clocks: clocks:
@ -283,6 +291,9 @@ allOf:
- qcom,sm8350-adsp-pas - qcom,sm8350-adsp-pas
- qcom,sm8350-cdsp-pas - qcom,sm8350-cdsp-pas
- qcom,sm8350-slpi-pas - qcom,sm8350-slpi-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-cdsp-pas
- qcom,sm8450-slpi-pas
then: then:
properties: properties:
interrupts: interrupts:
@ -312,6 +323,7 @@ allOf:
- qcom,sm6350-mpss-pas - qcom,sm6350-mpss-pas
- qcom,sm8150-mpss-pas - qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas - qcom,sm8350-mpss-pas
- qcom,sm8450-mpss-pas
then: then:
properties: properties:
interrupts: interrupts:
@ -434,6 +446,7 @@ allOf:
- qcom,sm6350-mpss-pas - qcom,sm6350-mpss-pas
- qcom,sm8150-mpss-pas - qcom,sm8150-mpss-pas
- qcom,sm8350-mpss-pas - qcom,sm8350-mpss-pas
- qcom,sm8450-mpss-pas
then: then:
properties: properties:
power-domains: power-domains:
@ -458,6 +471,8 @@ allOf:
- qcom,sm8250-slpi-pas - qcom,sm8250-slpi-pas
- qcom,sm8350-adsp-pas - qcom,sm8350-adsp-pas
- qcom,sm8350-slpi-pas - qcom,sm8350-slpi-pas
- qcom,sm8450-adsp-pas
- qcom,sm8450-slpi-pas
then: then:
properties: properties:
power-domains: power-domains:
@ -475,6 +490,7 @@ allOf:
contains: contains:
enum: enum:
- qcom,sm8350-cdsp-pas - qcom,sm8350-cdsp-pas
- qcom,sm8450-cdsp-pas
then: then:
properties: properties:
power-domains: power-domains:

78
Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml Normal file
View File

@ -0,0 +1,78 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MP HSIO blk-ctrl
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the high-speed IO
(USB an PCIe) peripherals located in the HSIO domain of the SoC.
properties:
compatible:
items:
- const: fsl,imx8mp-hsio-blk-ctrl
- const: syscon
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
minItems: 6
maxItems: 6
power-domain-names:
items:
- const: bus
- const: usb
- const: usb-phy1
- const: usb-phy2
- const: pcie
- const: pcie-phy
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: usb
- const: pcie
required:
- compatible
- reg
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
hsio_blk_ctrl: blk-ctrl@32f10000 {
compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
reg = <0x32f10000 0x24>;
clocks = <&clk IMX8MP_CLK_USB_ROOT>,
<&clk IMX8MP_CLK_PCIE_ROOT>;
clock-names = "usb", "pcie";
power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
<&pgc_usb1_phy>, <&pgc_usb2_phy>,
<&pgc_hsiomix>, <&pgc_pcie_phy>;
power-domain-names = "bus", "usb", "usb-phy1",
"usb-phy2", "pcie", "pcie-phy";
#power-domain-cells = <1>;
};

71
Documentation/devicetree/bindings/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml Normal file
View File

@ -0,0 +1,71 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8MQ VPU blk-ctrl
maintainers:
- Lucas Stach <l.stach@pengutronix.de>
description:
The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
the NoC and ensuring proper power sequencing of the VPU peripherals
located in the VPU domain of the SoC.
properties:
compatible:
items:
- const: fsl,imx8mq-vpu-blk-ctrl
reg:
maxItems: 1
'#power-domain-cells':
const: 1
power-domains:
minItems: 3
maxItems: 3
power-domain-names:
items:
- const: bus
- const: g1
- const: g2
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: g1
- const: g2
required:
- compatible
- reg
- power-domains
- power-domain-names
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mq-clock.h>
#include <dt-bindings/power/imx8mq-power.h>
vpu_blk_ctrl: blk-ctrl@38320000 {
compatible = "fsl,imx8mq-vpu-blk-ctrl";
reg = <0x38320000 0x100>;
power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
power-domain-names = "bus", "g1", "g2";
clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>,
<&clk IMX8MQ_CLK_VPU_G2_ROOT>;
clock-names = "g1", "g2";
#power-domain-cells = <1>;
};

1
Documentation/devicetree/bindings/soc/mediatek/pwrap.txt
View File

@ -27,6 +27,7 @@ Required properties in pwrap device node.
"mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs
"mediatek,mt8173-pwrap" for MT8173 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs
"mediatek,mt8183-pwrap" for MT8183 SoCs "mediatek,mt8183-pwrap" for MT8183 SoCs
"mediatek,mt8186-pwrap" for MT8186 SoCs
"mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs
"mediatek,mt8516-pwrap" for MT8516 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs
- interrupts: IRQ for pwrap in SOC - interrupts: IRQ for pwrap in SOC

1
Documentation/devicetree/bindings/soc/rockchip/grf.yaml
View File

@ -15,6 +15,7 @@ properties:
- items: - items:
- enum: - enum:
- rockchip,rk3288-sgrf - rockchip,rk3288-sgrf
- rockchip,rk3568-usb2phy-grf
- rockchip,rv1108-usbgrf - rockchip,rv1108-usbgrf
- const: syscon - const: syscon
- items: - items:

20
Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml
View File

@ -17,13 +17,6 @@ description: |
child nodes, each representing a serial sub-node device. The mode setting child nodes, each representing a serial sub-node device. The mode setting
selects which particular function will be used. selects which particular function will be used.
Refer to next bindings documentation for information on protocol subnodes that
can exist under USI node:
[1] Documentation/devicetree/bindings/serial/samsung_uart.yaml
[2] Documentation/devicetree/bindings/i2c/i2c-exynos5.txt
[3] Documentation/devicetree/bindings/spi/samsung,spi.yaml
properties: properties:
$nodename: $nodename:
pattern: "^usi@[0-9a-f]+$" pattern: "^usi@[0-9a-f]+$"
@ -71,10 +64,17 @@ properties:
This property is optional. This property is optional.
patternProperties: patternProperties:
# All other properties should be child nodes "^i2c@[0-9a-f]+$":
"^(serial|spi|i2c)@[0-9a-f]+$": $ref: /schemas/i2c/i2c-exynos5.yaml
description: Child node describing underlying I2C
"^serial@[0-9a-f]+$":
$ref: /schemas/serial/samsung_uart.yaml
description: Child node describing underlying UART/serial
"^spi@[0-9a-f]+$":
type: object type: object
description: Child node describing underlying USI serial protocol description: Child node describing underlying SPI
required: required:
- compatible - compatible

33
Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt
View File

@ -1,33 +0,0 @@
Andestech ATCPIT100 timer
------------------------------------------------------------------
ATCPIT100 is a generic IP block from Andes Technology, embedded in
Andestech AE3XX platforms and other designs.
This timer is a set of compact multi-function timers, which can be
used as pulse width modulators (PWM) as well as simple timers.
It supports up to 4 PIT channels. Each PIT channel is a
multi-function timer and provide the following usage scenarios:
One 32-bit timer
Two 16-bit timers
Four 8-bit timers
One 16-bit PWM
One 16-bit timer and one 8-bit PWM
Two 8-bit timer and one 8-bit PWM
Required properties:
- compatible : Should be "andestech,atcpit100"
- reg : Address and length of the register set
- interrupts : Reference to the timer interrupt
- clocks : a clock to provide the tick rate for "andestech,atcpit100"
- clock-names : should be "PCLK" for the peripheral clock source.
Examples:
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0xf0400000 0x1000>;
interrupts = <2>;
clocks = <&apb>;
clock-names = "PCLK";
};

1
Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt
View File

@ -12,6 +12,7 @@ Required properties:
For those SoCs that use GPT For those SoCs that use GPT
* "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT)
* "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT)
* "mediatek,mt6582-timer" for MT6582 compatible timers (GPT)
* "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT)
* "mediatek,mt7623-timer" for MT7623 compatible timers (GPT) * "mediatek,mt7623-timer" for MT7623 compatible timers (GPT)
* "mediatek,mt8127-timer" for MT8127 compatible timers (GPT) * "mediatek,mt8127-timer" for MT8127 compatible timers (GPT)

8
Documentation/devicetree/bindings/usb/dwc2.yaml
View File

@ -41,6 +41,7 @@ properties:
- amlogic,meson8b-usb - amlogic,meson8b-usb
- amlogic,meson-gxbb-usb - amlogic,meson-gxbb-usb
- amlogic,meson-g12a-usb - amlogic,meson-g12a-usb
- intel,socfpga-agilex-hsotg
- const: snps,dwc2 - const: snps,dwc2
- const: amcc,dwc-otg - const: amcc,dwc-otg
- const: apm,apm82181-dwc-otg - const: apm,apm82181-dwc-otg
@ -68,6 +69,13 @@ properties:
items: items:
- const: otg - const: otg
disable-over-current:
type: boolean
description: whether to disable detection of over-current condition.
iommus:
maxItems: 1
resets: resets:
items: items:
- description: common reset - description: common reset

18
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -23,6 +23,8 @@ patternProperties:
"^(simple-audio-card|st-plgpio|st-spics|ts),.*": true "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true
# Keep list in alphabetical order. # Keep list in alphabetical order.
"^100ask,.*":
description: Baiwen.com (100ask).
"^70mai,.*": "^70mai,.*":
description: 70mai Co., Ltd. description: 70mai Co., Ltd.
"^8dev,.*": "^8dev,.*":
@ -61,6 +63,8 @@ patternProperties:
description: Aeroflex Gaisler AB description: Aeroflex Gaisler AB
"^aesop,.*": "^aesop,.*":
description: AESOP Embedded Forum description: AESOP Embedded Forum
"^airoha,.*":
description: Airoha
"^al,.*": "^al,.*":
description: Annapurna Labs description: Annapurna Labs
"^alcatel,.*": "^alcatel,.*":
@ -277,12 +281,16 @@ patternProperties:
description: Hangzhou C-SKY Microsystems Co., Ltd description: Hangzhou C-SKY Microsystems Co., Ltd
"^csq,.*": "^csq,.*":
description: Shenzen Chuangsiqi Technology Co.,Ltd. description: Shenzen Chuangsiqi Technology Co.,Ltd.
"^ctera,.*":
description: CTERA Networks Intl.
"^cubietech,.*": "^cubietech,.*":
description: Cubietech, Ltd. description: Cubietech, Ltd.
"^cui,.*": "^cui,.*":
description: CUI Devices description: CUI Devices
"^cypress,.*": "^cypress,.*":
description: Cypress Semiconductor Corporation description: Cypress Semiconductor Corporation
"^cyx,.*":
description: Shenzhen CYX Industrial Co., Ltd
"^cznic,.*": "^cznic,.*":
description: CZ.NIC, z.s.p.o. description: CZ.NIC, z.s.p.o.
"^dallas,.*": "^dallas,.*":
@ -489,6 +497,8 @@ patternProperties:
deprecated: true deprecated: true
"^hannstar,.*": "^hannstar,.*":
description: HannStar Display Corporation description: HannStar Display Corporation
"^haochuangyi,.*":
description: Shenzhen Haochuangyi Technology Co.,Ltd
"^haoyu,.*": "^haoyu,.*":
description: Haoyu Microelectronic Co. Ltd. description: Haoyu Microelectronic Co. Ltd.
"^hardkernel,.*": "^hardkernel,.*":
@ -769,6 +779,8 @@ patternProperties:
description: MiraMEMS Sensing Technology Co., Ltd. description: MiraMEMS Sensing Technology Co., Ltd.
"^mitsubishi,.*": "^mitsubishi,.*":
description: Mitsubishi Electric Corporation description: Mitsubishi Electric Corporation
"^miyoo,.*":
description: Miyoo
"^mntre,.*": "^mntre,.*":
description: MNT Research GmbH description: MNT Research GmbH
"^modtronix,.*": "^modtronix,.*":
@ -892,6 +904,8 @@ patternProperties:
description: Ortus Technology Co., Ltd. description: Ortus Technology Co., Ltd.
"^osddisplays,.*": "^osddisplays,.*":
description: OSD Displays description: OSD Displays
"^osmc,.*":
description: Sam Nazarko Trading Ltd. (Open Source Media Centre)
"^ouya,.*": "^ouya,.*":
description: Ouya Inc. description: Ouya Inc.
"^overkiz,.*": "^overkiz,.*":
@ -1205,6 +1219,8 @@ patternProperties:
description: Shenzhen Techstar Electronics Co., Ltd. description: Shenzhen Techstar Electronics Co., Ltd.
"^terasic,.*": "^terasic,.*":
description: Terasic Inc. description: Terasic Inc.
"^tesla,.*":
description: Tesla, Inc.
"^tfc,.*": "^tfc,.*":
description: Three Five Corp description: Three Five Corp
"^thead,.*": "^thead,.*":
@ -1350,6 +1366,8 @@ patternProperties:
description: WinLink Co., Ltd description: WinLink Co., Ltd
"^winstar,.*": "^winstar,.*":
description: Winstar Display Corp. description: Winstar Display Corp.
"^wirelesstag,.*":
description: Wireless Tag (qiming yunduan)
"^wits,.*": "^wits,.*":
description: Shenzhen Merrii Technology Co., Ltd. (WITS) description: Shenzhen Merrii Technology Co., Ltd. (WITS)
"^wlf,.*": "^wlf,.*":

1
Documentation/devicetree/bindings/watchdog/mtk-wdt.txt
View File

@ -8,6 +8,7 @@ Required properties:
- compatible should contain: - compatible should contain:
"mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701
"mediatek,mt2712-wdt": for MT2712 "mediatek,mt2712-wdt": for MT2712
"mediatek,mt6582-wdt", "mediatek,mt6589-wdt": for MT6582
"mediatek,mt6589-wdt": for MT6589 "mediatek,mt6589-wdt": for MT6589
"mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797
"mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622

1
Documentation/features/core/cBPF-JIT/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/core/eBPF-JIT/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/core/generic-idle-thread/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | ok | | openrisc: | ok |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/core/jump-labels/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/core/thread-info-in-task/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | ok |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/core/tracehook/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | ok | | openrisc: | ok |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/KASAN/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/debug-vm-pgtable/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/gcov-profile-all/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kcov/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kgdb/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | ok | | nios2: | ok |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/kmemleak/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | ok |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/kprobes-on-ftrace/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/kprobes/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/kretprobes/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/debug/optprobes/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/stackprotector/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/uprobes/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/debug/user-ret-profiler/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/io/dma-contiguous/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/cmpxchg-local/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/lockdep/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | ok |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | ok | | openrisc: | ok |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/queued-rwlocks/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | ok | | openrisc: | ok |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/locking/queued-spinlocks/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | ok | | openrisc: | ok |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/perf/kprobes-event/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | ok |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/perf/perf-regs/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/perf/perf-stackdump/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/sched/membarrier-sync-core/arch-support.txt
View File

@ -40,7 +40,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/sched/numa-balancing/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | .. | | m68k: | .. |
| microblaze: | .. | | microblaze: | .. |
| mips: | TODO | | mips: | TODO |
| nds32: | TODO |
| nios2: | .. | | nios2: | .. |
| openrisc: | .. | | openrisc: | .. |
| parisc: | .. | | parisc: | .. |

1
Documentation/features/seccomp/seccomp-filter/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | ok | | parisc: | ok |

1
Documentation/features/time/arch-tick-broadcast/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/clockevents/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | ok | | microblaze: | ok |
| mips: | ok | | mips: | ok |
| nds32: | ok |
| nios2: | ok | | nios2: | ok |
| openrisc: | ok | | openrisc: | ok |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/context-tracking/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | TODO | | parisc: | TODO |

1
Documentation/features/time/irq-time-acct/arch-support.txt
View File

@ -17,7 +17,6 @@
| m68k: | TODO | | m68k: | TODO |
| microblaze: | TODO | | microblaze: | TODO |
| mips: | ok | | mips: | ok |
| nds32: | TODO |
| nios2: | TODO | | nios2: | TODO |
| openrisc: | TODO | | openrisc: | TODO |
| parisc: | .. | | parisc: | .. |

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